Hi Ralf,
Do you know of a difference in the way SPI and PPI are treated by the
hypervisor?
A timer that is specific for a certain core is wired to GIC by PPI. Would
its processing be influenced by heavy load running on another core?
The GIC is facing the same load, but handles PPI instead of
Hi,
Exactly I reference to 'jailhouse cell stats'
We enabled TSC in Hypervisor init, and printed value to dmsg.
But *after* start of Linux it gets disabled again.
*** Is there a place in hypervisor that runs at kernel space after start of
linux where we can put re-enabling of TSC?
We would like
Hi Rasty,
(reply-to-all :) )
On 13/12/2022 19:31, Rasty Slutsker wrote:
We learned how you export some statistics from Jailhouse as you guys do
and added 3 variables
You reference to 'jailhouse cell stats'?
1. At the entry Jailhouse IRQ (if irq==xxx counter ++)
2. At injection point of
We learned how you export some statistics from Jailhouse as you guys do and
added 3 variables
1. At the entry Jailhouse IRQ (if irq==xxx counter ++)
2. At injection point of the same IRQ to inmate, still in Jailhouse
3. At the beginning of ISR in inmate (RTOS).
We let system run, introduce
Hi Rasty,
Please reply-to-all, then your reply will also pop up in my Inbox.
On 10/12/2022 08:52, Rasty Slutsker wrote:
Hi,
We did some performance measurements.
Added counters in 3 places (per Irq source)
1. entry to jailhouse ISR
2. dispatch of interrupt to particular vector to particular
Hi,
We did some performance measurements.
Added counters in 3 places (per Irq source)
1. entry to jailhouse ISR
2. dispatch of interrupt to particular vector to particular core
3. in RTOS isr.
*We see that all 3 counters have the same value*, but we measure time gaps
in RTOS in ISR invocation
Hi,
On 05/12/2022 17:30, Rasty Slutsker wrote:
Hi Ralf,
Thank you for the answer.
We have periodic interrupt each 30 u(!)Sec. Linux cannot deal with such
rate, so we need hypervisor/RTOS.
I understand.
We managed to read a code of hypervisor. It appears that all interrupts
to all cores are
Hi Ralf,
Thank you for the answer.
We have periodic interrupt each 30 u(!)Sec. Linux cannot deal with such
rate, so we need hypervisor/RTOS.
We managed to read a code of hypervisor. It appears that all interrupts to
all cores are intercepted by hypervisor and then forwarded to guests (per
Hi Nir,
On 29/11/2022 14:21, nirge...@gmail.com wrote:
Hi there,
Our target is Sitara AM5726 , CortexA15 dual core on which we are
running Linux on A15 core0 and RTOS on core1.
__
RTOS gets periodic interrupt from external hardware via nirq1 pin
(dedicated input into ARM gic).
Under
Hi there,
Our target is Sitara AM5726 , CortexA15 dual core on which we are running
Linux on A15 core0 and RTOS on core1.
RTOS gets periodic interrupt from external hardware via nirq1 pin
(dedicated input into ARM gic).
Under heavy load in Linux (core 0!), RTOS, which runs on core1 misses
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