Hello Jeff,
I just checked and that doesn't seem to be the case here.
R1 /a0cec481-6d12-448f-86cc-c28b78945760
R2 /2b22cd25-9b07-4b44-9454-a447c5deb022
R3 /5728510b-9b66-4b52-a87f-214fd4df2e61
R4 /305018a5-34e0-410a-bff5-1eb7a79bc504
R5 /36178733-2e55-42eb-8e00-ab3976b16d92
R6
Hello Jeff,
I was using github instead of gitlab, this lags gitlab by a day it seems.
The problem fixed with ae852e17f987b77e2acf141285edbbbdaf27548f.
I am not able to reproduce the overflow, but it seems it might be
something else. The attached project does contain a DRC error, but the
wrong
Hello Jeff,
I just tried version 9ff09aa784551264e89350368f61ed6b35266f7a, but
it still fails. I tells me that it requires 1.3mm clearance, but both
the hole and the track are in the "Net-(C1-Pad1)" netclass, which should
only require 0.25mm. The plane clearances are as expected.
With this
Hello Jeff,
I've tried my big board and the clearances seem to work OK for planes.
I still have to compare the gerbers and check if they are exactly as
expected.
However I get a lot of clearance error on holes in the board, and am
unable to solve this. I've attached an example project. There is
Hello Jeff,
I assume in that case the last selector is applied and not the last
rule, correct?
To be honest I prefer the selector/rule seperation, is that going to stay?
regards,
Mark.
Jeff Young wrote:
Hi Mark,
The condition syntax was just a preview. It???s not
I just tested the old simple testcase, the new rule file is:
(rule "Max_Net-(C1-Pad1)"
(constraint clearance (min 1.3mm))
(condition "A.netclass == Net-(C1-Pad1)"))
(rule "Min_Net-(C1-Pad1)"
Hello Jeff,
I tried to give the big board a new attempt, previously a lot of strange
things happened which I quite couldn't figure out. I noticed the priority
was no longer accepted. Can you give a quick update on the intended way
the rules are supposed to be used?
regards,
Mark.
Hello Jeff,
It works correctly with 4f14769ce1ca587f72b51024a71e12a97d9d42f8. I will
have to update the rules before I can check the big board. This will take
some time, I'll let you know the result.
regards,
Mark.
Jeff Young wrote:
Hi Mark,
There are 4 or 5 bug
Hello Jeff,
That works fine on the plane, but when I do a DRC check if fails on the
pads of C1 and C2. I'm using cec857c0f49d4fd984a4095896306ff5d3a5930e,
not sure if you changed anything after that.
To me the syntax is just fine, as long as these things can be specified
correcly.
regards,
Hello Jeff,
I've tried to get the big board working, but I'm unable to set a default
clearance on a netclass. What I want to achieve is that a certain netclass
has a small clearance (0.2mm) with itself, but a large clearance to
other netclasses, for example 5.5mm. For some netclasses I would like
Excellent, now it works :-)
I'll test the big board tomorrow. For me this was the most important
feature missing from kicad, thanks for making it work.
regards,
Mark.
Jeff Young wrote:
Congrats on the first bug!
Actually 4 separate ones: the caching mechanism was
Sorry, forgot to attach the project.
<>
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Hello Jeff,
Seems easy to reproduce, so here is a test project. There are just two
netclasses and three nets. I expected the cutout in the zone to create
a 1.3mm clearance for Net-(R1-Pad2).
regards,
Mark.
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I've just tested this on a design and the drc-rules is read, which I
know because if I don't add "(version 1)" at the first line I get an
error message. Other than that I doesn't seem to do anything.
I tried to add "(priority 100)" to the rules, but that is refused when
reading the drc file. It's
Just gave this a try, but pcbnew also fails immediately.
I'll file a bugreport this evening.
regards,
Mark
Andrew Lutsenko wrote:
Another good thing to check would be if the issue only happens when
trying
to run pcbnew standalone. If launched from kicad process there
I've seen the following problem for some time when wxpython is enabled:
[xcb] Unknown sequence number while processing reply
[xcb] Most likely this is a multi-threaded client and XInitThreads has not been
called
You need to use:
cmake -DBoost_NO_BOOST_CMAKE=ON
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Sorry about that, here's the patch
From e7586acb334955de22786d76e28f5374d2446d2c Mon Sep 17 00:00:00 2001
From: Mark
Date: Thu, 9 May 2019 09:53:46 +0200
Subject: [PATCH] Fix for SWIG 4.0.0
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="2.21.0"
This is a multi-part
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Hallo Wayne,
Sorry for the repeat message, but I never managed to subscribe to the
mailing list using my usual e-mail account.
I would be glad to elaborate on that. But the main point is that for
power electronics a net clearance is not all that usefull. The simplest
example is when you have a
Hello Wayne,
Please consider it on hold for now. Once kicad supports netclass to
netclass clearances I will have another look. The dimensions are not
copied yet, since I stopped working on it once I found out that all
the unnamed nets lost their netclass after the first update from the
schematic.
I am removing all BOARD_CONNECTED_ITEM::GetClearance with aItem==NULL
for the purpose of checking net<->net clearances only. Does it make sense
to send this patch, or should I just wait until v6 development is started?
regards,
Mark
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Here's a patch to import the netclasses from eagle.
As already mentioned, all nets without a label are in the default
netclass. The clearances are ignored because I have no idea what clearance
to use. The trackwidths are ignored, I've never used that and saw no
reason to fix this since the patch
Eagle is also very limited in that regard. But at least they can create
a 32x32 matrix with clearances.
Converting a PCB with contraints works (except the clearance matrix),
but unfortunately many of the nets in the design I converted were unnamed
nets. At the first conversion from the schematic
I just had a look at the pending buglist and saw #1754130 Eagle import
ignores net class and net class settings.
I have a patch for that, but the reason I did not post it, is because
it is pretty useless (for me at least). Kicad does not support setting
netclass to netclass clearances, but eagle
I've seen it is possible to write action plugins in python, I would
rather do this kind of stuff in C++. In the sources I've found only some
file loaders/savers and 3D stuff. Is the kind of plugin like "replicate
layout" possible from C++? And if it is, is there some kind of example?
regards,
Hello Seth,
I never even knew this feature existed. So basically copper which is
not a pad is ignored during DRC? That's fine, you should not do that
unless you're doing something weird.
regards,
Mark.
Seth Hillbrand wrote:
Hi Mark-
This is the current 5.0 behavior, so
Ignoring clearances in a footprint sound scary to me. Doing 1kV
designs I want the clearances checked, so Ik know I've chosen the wrong
footprint. How about creating special pin names xxx_nettie just like
the special netnames for differential pairs?
regards,
Mark.
Seth Hillbrand wrote:
Found another bug. When importing sheet pins, the pin can be placed and
is visible during placement. Once placed it is no-longer visible. When I
quit eeschema and start it with the same file, the sheet label is visible
and right where I left it.
regards,
Mark.
I don't think I mailed the list, but also found another issue.
I noticed the sheet text is the same color as "notes", and not "sheet
label".
The cursor cross-hair is always black.
Otherwise it works fine for me on a quick test.
regards,
Mark.
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I've given the GAL version a test-drive. Here are some issues I noted.
I guess most of it is because the black background was not tested before.
1. Grid color always black. (Not visible on black background)
2. Hierarchical sheet color always white.
3. When using another background color (for
Hello Seth,
As requested an example eagle project using variants.
regards
Mark.
eagle_variant.tgz
Description: Binary data
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Hello Seth,
I don't know how to use eagle myself, but will ask a colleague to create
a small sample project. He's on vacation right now but will be back
next week.
regards,
Mark.
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From: Mark van Doesburg
Here is a patch that copies all attributes from an original eagle
schematic. This is necessary for me to keep the BOM the same.
Since kicad does not yet support variants, it creates additional fields
for values that differ for variants. It prefixes them with "VARIANT_"
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