Re: [Kicad-developers] DRC rules
Hello Jeff, I just checked and that doesn't seem to be the case here. R1 /a0cec481-6d12-448f-86cc-c28b78945760 R2 /2b22cd25-9b07-4b44-9454-a447c5deb022 R3 /5728510b-9b66-4b52-a87f-214fd4df2e61 R4 /305018a5-34e0-410a-bff5-1eb7a79bc504 R5 /36178733-2e55-42eb-8e00-ab3976b16d92 R6 /17490a70-e00b-49eb-b458-1c72867c2424 The actual DRC violation involves R1,R2,R4 and R5 but is reported on R3. regards, Mark Jeff Young wrote: Hi Mark, We???ve seen something like that DRC error before. I think it was because the two items (the reported item and the correct item) had the same UUID. Can you check to see if that???s the case here? Thanks, Jeff. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I was using github instead of gitlab, this lags gitlab by a day it seems. The problem fixed with ae852e17f987b77e2acf141285edbbbdaf27548f. I am not able to reproduce the overflow, but it seems it might be something else. The attached project does contain a DRC error, but the wrong pads are identified. The actual error is in the middle of the board, where Net-(R4-Pad2) and Net-(R1-Pad2) are too close. The reported error is between Net-(C2-Pad1) and Net-(C1-Pad2), the location of the error arrows are correct however. The violated constraint is also correct. regards, Mark Jeff Young wrote: Hi Mark, That???s 6 change-lists too early for the fix. You need at least d2cd4de280353b02ab66dab8e22e8da88415dc13. Cheers, Jeff. <> ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I just tried version 9ff09aa784551264e89350368f61ed6b35266f7a, but it still fails. I tells me that it requires 1.3mm clearance, but both the hole and the track are in the "Net-(C1-Pad1)" netclass, which should only require 0.25mm. The plane clearances are as expected. With this version I can fix the problem by changing the drc file to remove the default clearance of the netclass. So what I have now is: (selector (match_netclass "Net-(C1-Pad1)") (rule "1.3mm")) # the "default" rule (selector (match_netclass "Net-(C1-Pad1)") (match_netclass "Net-(C1-Pad1)") (rule "Default")) If the "default" rule is removed everything is OK. Now obviously I can do this, but it has consequences for the number of drc-rules I need. For the big design I can constrain with 451 lines when I can use a default, if that's not possible I need 7437 lines. There is also an overflow at some point. Two pads, one at (364, 218.5) and the other at (124.45, 50.4) are only 4.351mm apart according to the DRC check. I'll create a testcase if you want me to. regards, Mark. Jeff Young wrote: Hi Mark, The hole clearance logic never got updated to pass both items (the track and the hole). It should work now. Cheers, Jeff. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I've tried my big board and the clearances seem to work OK for planes. I still have to compare the gerbers and check if they are exactly as expected. However I get a lot of clearance error on holes in the board, and am unable to solve this. I've attached an example project. There is a plane which has the correct clearance, there is a track in this plane as well. I don't expect this track to give a DRC error, but it does. I've tried (match_type pth) and also hole but I cannot make the error disappear. Any help would be welcome. regards, Mark. <> ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I assume in that case the last selector is applied and not the last rule, correct? To be honest I prefer the selector/rule seperation, is that going to stay? regards, Mark. Jeff Young wrote: Hi Mark, The condition syntax was just a preview. It???s not implemented yet. You???ll need to use the selector syntax for now. So, for instance: (selector (match_netclass "Net-(C1-Pad1)") (match_netclass "Net-(C1-Pad1)???) (rule ???Min_Net-(C1-Pad1)") Cheers, Jeff. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
I just tested the old simple testcase, the new rule file is: (rule "Max_Net-(C1-Pad1)" (constraint clearance (min 1.3mm)) (condition "A.netclass == Net-(C1-Pad1)")) (rule "Min_Net-(C1-Pad1)" (constraint clearance (min 0.25mm)) (condition "A.netclass == Net-(C1-Pad1) && B.netclass == Net-(C1-Pad1)")) (rule "Max_Net-(R1-Pad2)" (constraint clearance (min 1.3mm)) (condition "A.netclass == Net-(R1-Pad2)")) (rule "Min_Net-(R1-Pad2)" (constraint clearance (min 0.25mm)) (condition "A.netclass == Net-(R1-Pad2) && B.netclass == Net-(R1-Pad2)")) (rule "Max_Net-(R4-Pad2)" (constraint clearance (min 1.3mm)) (condition "A.netclass == Net-(R4-Pad2)")) (rule "Min_Net-(R4-Pad2)" (constraint clearance (min 0.25mm)) (condition "A.netclass == Net-(R4-Pad2) && B.netclass == Net-(R4-Pad2)")) (rule "Specific_Net-(C1-Pad1)__Net-(R1-Pad2)" (constraint clearance (min 1.3mm)) (condition "A.netclass == Net-(C1-Pad1) && B.netclass == Net-(R1-Pad2)")) (rule "Specific_Net-(C1-Pad1)__Net-(R4-Pad2)" (constraint clearance (min 1.3mm)) (condition "A.netclass == Net-(C1-Pad1) && B.netclass == Net-(R4-Pad2)")) I'm probably completely missing the point, but everything seems to be constrained at 0.25mm clearance. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I tried to give the big board a new attempt, previously a lot of strange things happened which I quite couldn't figure out. I noticed the priority was no longer accepted. Can you give a quick update on the intended way the rules are supposed to be used? regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, It works correctly with 4f14769ce1ca587f72b51024a71e12a97d9d42f8. I will have to update the rules before I can check the big board. This will take some time, I'll let you know the result. regards, Mark. Jeff Young wrote: Hi Mark, There are 4 or 5 bug fixes after the hash you???re using. The one I just pushed is most likely to address your pad-to-pad DRC issue. Cheers, Jeff. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, That works fine on the plane, but when I do a DRC check if fails on the pads of C1 and C2. I'm using cec857c0f49d4fd984a4095896306ff5d3a5930e, not sure if you changed anything after that. To me the syntax is just fine, as long as these things can be specified correcly. regards, Mark. Jeff Young wrote: Hi Mark, That???s expected. The effective clearance is the largest specified in all rules that match. Since both selectors match in the same-net case, the effective clearance is 1.3mm. There is a ???relaxed??? token to address this, which allows a higher-priority rule to relax a constraint. So try: (version 1) (selector (priority 150) (match_netclass "Net-(C1-Pad1)") (match_netclass "Net-(C1-Pad1)") (rule "0.2mm")) (selector (priority 100) (match_netclass "Net-(C1-Pad1)") (rule "1.3mm")) (rule "1.3mm" (clearance 1.3)) (rule "0.2mm" (clearance relaxed 0.2)) It???s worth noting that we???re not very happy with this syntax and are working on some other ways to address it. Cheers, Jeff. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, I've tried to get the big board working, but I'm unable to set a default clearance on a netclass. What I want to achieve is that a certain netclass has a small clearance (0.2mm) with itself, but a large clearance to other netclasses, for example 5.5mm. For some netclasses I would like to set a smaller clearance. I've tried the following approach (with and without priority, and in reverse priority). But in this case it always uses the 1.3mm, also within the netclass itself. I've attached the test project. (version 1) (selector (priority 100) (match_netclass "Net-(C1-Pad1)") (match_netclass "Net-(C1-Pad1)") (rule "0.2mm")) (selector (priority 150) (match_netclass "Net-(C1-Pad1)") (rule "1.3mm")) (rule "1.3mm" (clearance 1.3)) (rule "0.2mm" (clearance 0.2)) regards, Mark. <> ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Excellent, now it works :-) I'll test the big board tomorrow. For me this was the most important feature missing from kicad, thanks for making it work. regards, Mark. Jeff Young wrote: Congrats on the first bug! Actually 4 separate ones: the caching mechanism was causing the rules to not be loaded when the board was read, the zone cutout stuff wasn???t fully hooked up to the new rules engine, there???s no "Net-(C1-Pad2)" netclass in the document (only "Net-(C1-Pad1)???), and the code responded poorly to failing to find a net (putting subsequent nets off-by-one). The third one is yours. ;) Fixes for the other three are now in master (if you build your own); otherwise you can get them from tonight???s nightly. Cheers, Jeff. > On 18 May 2020, at 12:01, mdoes...@xs4all.nl wrote: > > Sorry, forgot to attach the project. > > > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Sorry, forgot to attach the project. <> ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
Hello Jeff, Seems easy to reproduce, so here is a test project. There are just two netclasses and three nets. I expected the cutout in the zone to create a 1.3mm clearance for Net-(R1-Pad2). regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] DRC rules
I've just tested this on a design and the drc-rules is read, which I know because if I don't add "(version 1)" at the first line I get an error message. Other than that I doesn't seem to do anything. I tried to add "(priority 100)" to the rules, but that is refused when reading the drc file. It's also not clear to me what the clearance dimension is, so I assumed nanometers. I've been using a hack to get clearance rules working for some time, so the design is already pretty large and uses 209 different netclasses. I did a clean built of 0658d297e528616e233b4074c27f1bdcb870dede,created drc-rules and edited the pcb file to create all the netclasses. I then loaded the board and rebuilt the planes, but all the rules seem to be ignored. I've attached the drc-rules file for reference. regards, Mark (version 1) (selector (match_netclass "+12V_ui") (match_netclass "+16P") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "+800V") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "+SOLAR") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/B+") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/B-") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/Flyback_control/DISABLE") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/Flyback_control/sw") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/M+") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/battery/M-") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "/control/CAN1_N") (rule "1mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(J45-Pad1)") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(J46-Pad1)") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(J47-Pad1)") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(J48-Pad1)") (rule "5.5mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R15-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R25-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R269-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R270-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R28-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R306-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R426-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R429-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R432-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R435-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R438-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R440-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R45-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R78-Pad2)") (rule "1.3mm")) (selector (match_netclass "+12V_ui") (match_netclass "Net-(R79-Pad2)") (rule "1.3mm")) (selector (match_netclass "+16P") (match_netclass "+800V") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/NEUTRAL_out") (rule "1.3mm")) (selector (match_netclass "+16P") (match_netclass "/Vin-") (rule "5.5mm")) (selector (match_netclass "+16P") (match_netclass "/balancer/GH+") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/battery/B-") (rule "5.5mm")) (selector (match_netclass "+16P") (match_netclass "/battery/Flyback/sw") (rule "5.5mm")) (selector (match_netclass "+16P") (match_netclass "/battery/M+") (rule "5.5mm")) (selector (match_netclass "+16P") (match_netclass "/battery/M-") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/flyback_mains/sw") (rule "5.5mm")) (selector (match_netclass "+16P") (match_netclass "/half-bridge1/-5V_hs") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/half-bridge2/-5V_hs") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/half-bridge3/-5V_hs") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar0/hv") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar0/pf1") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar0/pf2") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar0/sw1") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar0/sw2") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar1/hv") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass "/solar1/pf1") (rule "2.4mm")) (selector (match_netclass "+16P") (match_netclass
Re: [Kicad-developers] kicad aborts when wxpython is enabled
Just gave this a try, but pcbnew also fails immediately. I'll file a bugreport this evening. regards, Mark Andrew Lutsenko wrote: Another good thing to check would be if the issue only happens when trying to run pcbnew standalone. If launched from kicad process there should be no race since kicad binary doesn't touch any python afaik. On Thu, May 16, 2019 at 5:53 AM Seth Hillbrand wrote: > Am 2019-05-16 06:29, schrieb mdoes...@xs4all.nl: > > I've seen the following problem for some time when wxpython is enabled: > > > > > > > [xcb] Unknown sequence number while processing reply > > [xcb] Most likely this is a multi-threaded client and XInitThreads has > > not been called > > [xcb] Aborting, sorry about that. > > kicad: xcb_io.c:643: _XReply: Assertion > > `!xcb_xlib_threads_sequence_lost' failed. > > Aborted > > > > > > > If I disable wxpython everything just works. I suspect it's a problem > > with my configuration, since it's almost impossible to start pcbnew. Is > > there anyone who has a suggestion where to look? > > This looks like a race condition in the wxInit() between python and > pcbnew. Can you please open a bug report for this? > > -Seth > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] kicad aborts when wxpython is enabled
I've seen the following problem for some time when wxpython is enabled: [xcb] Unknown sequence number while processing reply [xcb] Most likely this is a multi-threaded client and XInitThreads has not been called [xcb] Aborting, sorry about that. kicad: xcb_io.c:643: _XReply: Assertion `!xcb_xlib_threads_sequence_lost' failed. Aborted If I disable wxpython everything just works. I suspect it's a problem with my configuration, since it's almost impossible to start pcbnew. Is there anyone who has a suggestion where to look? regards, Mark van Doesburg ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Problems with Boost library building Kicad from git sources on Slackware64-current Linux
You need to use: cmake -DBoost_NO_BOOST_CMAKE=ON ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] swig 4.0.0 patch
Sorry about that, here's the patch From e7586acb334955de22786d76e28f5374d2446d2c Mon Sep 17 00:00:00 2001 From: Mark Date: Thu, 9 May 2019 09:53:46 +0200 Subject: [PATCH] Fix for SWIG 4.0.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="2.21.0" This is a multi-part message in MIME format. --2.21.0 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: 8bit --- scripting/build_tools/fix_swig_imports.py | 3 +++ 1 file changed, 3 insertions(+) --2.21.0 Content-Type: text/x-patch; name="0001-Fix-for-SWIG-4.0.0.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="0001-Fix-for-SWIG-4.0.0.patch" diff --git a/scripting/build_tools/fix_swig_imports.py b/scripting/build_tools/fix_swig_imports.py index 160d7e2d9..4f97df079 100644 --- a/scripting/build_tools/fix_swig_imports.py +++ b/scripting/build_tools/fix_swig_imports.py @@ -40,6 +40,9 @@ if (len(lines)<4000): txt = b"" for l in lines: +if l.startswith(b"if _swig_python_version_info < (2, 7, 0):"): # ok with swig version >= 4.0.0 +l = l.replace(b"_swig_python_version_info < (2, 7, 0)", b"False") +doneOk = True if l.startswith(b"if _swig_python_version_info >= (2, 7, 0):"): # ok with swig version >= 3.0.10 l = l.replace(b"_swig_python_version_info >= (2, 7, 0)", b"False") doneOk = True --2.21.0-- ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] swig 4.0.0 patch
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Re: [Kicad-developers] Bug 1754130
Hallo Wayne, Sorry for the repeat message, but I never managed to subscribe to the mailing list using my usual e-mail account. I would be glad to elaborate on that. But the main point is that for power electronics a net clearance is not all that usefull. The simplest example is when you have a DC-DC converter which is supposed to have 4kV isolation between input and output, but both the primary and secondary circuits are 12V. Another example is a high voltage half bridge. You have for example the 1kV and the 0V rail, and a switching node which is either 1kV or 0V. This switching node has a gate driver attached to it which is low voltage (for example 12V) within itself and needs only 0.2mm clearance. The gate driver group of nets needs 3.2mm clearance from both the 1kV and 0V rail however. What Eagle does is that you can have 32 netclasses (I need more please ;-) ). A clearance matrix gives the clearance between the netclasses (and within the netclass itself on the diagonal), obviously this matrix is symmetric. regards, Mark Wayne Stambaugh wrote: Hey Mark, Will do. This will give us a chance to better understand how to even map this over to KiCad. I'm still no sure I even understand what is meant by netclass to netclass clearance. Cheers, Wayne ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Hello Wayne, Please consider it on hold for now. Once kicad supports netclass to netclass clearances I will have another look. The dimensions are not copied yet, since I stopped working on it once I found out that all the unnamed nets lost their netclass after the first update from the schematic. This may be easy to fix or not, but at that point I decided to simply forget it. regards, Mark Wayne Stambaugh wrote: Hey Mark, On 1/11/2019 5:11 AM, mdoes...@xs4all.nl wrote: > Here's a patch to import the netclasses from eagle. There are a few minor coding policy issues. We now have clang formatting available when you perform a git commit if you would prefer not to have to remember KiCad's formatting. You just have to enable it in your git repo if that is your preference. It looks like there is some left over debugging code (using std::cerr) that needs to be removed. If you want leave debugging support in your code, please use wxLogTrace[1]. I looks like you are translating Eagle units directly to kicad's pcb units. Is this valid? I don't know what internal units Eagle uses for boards but KiCad uses 1nm. If Eagle doesn't use 1nm, then your unit conversions are wrong. > > As already mentioned, all nets without a label are in the default > netclass. The clearances are ignored because I have no idea what clearance > to use. The trackwidths are ignored, I've never used that and saw no > reason to fix this since the patch isn't that usefull anyway. Does Eagle specify a default net clearance? If so, we should be using that instead of the KiCad default net clearance for the nets not assigned to a netclass. Would our resident Eagle file format expert please take a look at this patch to see if it makes sense? I'm not terribly familiar with the Eagle file format. Cheers, Wayne [1]: https://docs.wxwidgets.org/3.0/group__group__funcmacro__log.html#gae28a46b220921cd87a6f75f0842294c5 > > regards, > > Mark. > > Seth Hillbrand wrote: > > Hi Mark-That would be great, thanks!-Seth > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] BOARD_CONNECTED_ITEM::GetClearance
I am removing all BOARD_CONNECTED_ITEM::GetClearance with aItem==NULL for the purpose of checking net<->net clearances only. Does it make sense to send this patch, or should I just wait until v6 development is started? regards, Mark ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Bug 1754130
Here's a patch to import the netclasses from eagle.
As already mentioned, all nets without a label are in the default
netclass. The clearances are ignored because I have no idea what clearance
to use. The trackwidths are ignored, I've never used that and saw no
reason to fix this since the patch isn't that usefull anyway.
regards,
Mark.
Seth Hillbrand wrote:
Hi Mark-That
would be great, thanks!-Seth
>From c5f78b33f2020ac78b0fb7b40f457b7e73bbd4db Mon Sep 17 00:00:00 2001
From: Mark van Doesburg
Date: Fri, 13 Jul 2018 09:31:13 +0200
Subject: [PATCH] Copy netclasses during eagle import.
---
pcbnew/eagle_plugin.cpp | 51 +
pcbnew/eagle_plugin.h | 19 +++
2 files changed, 65 insertions(+), 5 deletions(-)
diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp
index b676bad50..e9bd51e77 100644
--- a/pcbnew/eagle_plugin.cpp
+++ b/pcbnew/eagle_plugin.cpp
@@ -171,7 +171,6 @@ void ERULES::parse( wxXmlNode* aRules )
}
}
-
EAGLE_PLUGIN::EAGLE_PLUGIN() :
m_rules( new ERULES() ),
m_xpath( new XPATH() ),
@@ -341,6 +340,9 @@ void EAGLE_PLUGIN::loadAllSections( wxXmlNode* aDoc )
wxXmlNode* designrules = boardChildren["designrules"];
loadDesignRules( designrules );
+wxXmlNode* net_classes = boardChildren["classes"];
+loadNetClasses( net_classes );
+
m_xpath->pop();
}
@@ -385,6 +387,40 @@ void EAGLE_PLUGIN::loadDesignRules( wxXmlNode*
aDesignRules )
}
}
+void EAGLE_PLUGIN::loadNetClasses( wxXmlNode* NetClasses )
+{
+m_xpath->push( "classes" );
+auto stod = []( wxString i ) { return std::stod( static_cast(
i ) ); };
+auto stoul = []( wxString i ) { return std::stoul(
static_cast( i ) ); };
+for( wxXmlNode* child = NetClasses->GetChildren(); child; child =
child->GetNext() )
+{
+if( child->GetName() != "class" )
+continue;
+auto name = child->GetAttribute( "name" );
+auto number = stoul( child->GetAttribute( "number" ) );
+auto width = stod( child->GetAttribute( "width" ) );
+auto drill = stod( child->GetAttribute( "drill" ) );
+if( m_classes.size() <= number )
+m_classes.resize( number + 1 );
+m_classes[number] = ECLASS( name, number, width, drill );
+std::cerr << "Netclass " << name << " " << number << " " << width << "
" << drill
+ << std::endl;
+for( auto& p : m_classes )
+p.clearance.resize( m_classes.size() );
+/* Doesn't work ?
+ for(wxXmlNode* clearance = child->GetChildren(); clearance; clearance =
clearance->GetNext()) {
+ if(clearance->GetName() != "clearance")
+ continue;
+ auto other=stoi(child->GetAttribute("class"));
+ auto value=stod(child->GetAttribute("value"));
+ m_classes[number].clearance[other]=value;
+ }
+ */
+m_classes[number].ptr = std::make_shared( name );
+m_board->GetDesignSettings().m_NetClasses.Add( m_classes[number].ptr );
+}
+m_xpath->pop(); // "classes"
+}
void EAGLE_PLUGIN::loadLayerDefs( wxXmlNode* aLayers )
{
@@ -843,7 +879,6 @@ void EAGLE_PLUGIN::loadLibraries( wxXmlNode* aLibs )
m_xpath->pop();
}
-
void EAGLE_PLUGIN::loadElements( wxXmlNode* aElements )
{
if( !aElements )
@@ -1903,8 +1938,15 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
zones.clear();
const wxString& netName = escapeName( net->GetAttribute( "name" ) );
+
m_board->Add( new NETINFO_ITEM( m_board, netName, netCode ) );
+ auto netClass = net -> GetAttribute( "class" );
+ if( netClass.length() )
+ {
+ m_classes[std::stoi( static_cast( netClass )
)].ptr->Add( netName );
+ }
+
m_xpath->Value( netName.c_str() );
// Get the first net item and iterate
@@ -1996,7 +2038,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
m_xpath->pop();
}
-
else if( itemName == "via" )
{
m_xpath->push( "via" );
@@ -2064,7 +2105,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
m_xpath->pop();
}
-
else if( itemName == "contactref" )
{
m_xpath->push( "contactref" );
@@ -2082,7 +2122,6 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
sawPad = true;
}
-
else if( itemName == "polygon" )
{
m_xpath->push( "polygon" );
@@ -2117,6 +2156,8 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals )
// Get next signal
net = net->GetNext();
}
+m_board->SynchronizeNetsAndNetClasses();
+
m_xpath->pop(); // "signals.signal"
}
diff --git a/pcbnew/eagle_plugin.h b/pcbnew/eagle_plugin.h
index e3df6d535..0a7b0605f 100644
--- a/pcbnew/eagle_plugin.h
+++
Re: [Kicad-developers] Bug 1754130
Eagle is also very limited in that regard. But at least they can create a 32x32 matrix with clearances. Converting a PCB with contraints works (except the clearance matrix), but unfortunately many of the nets in the design I converted were unnamed nets. At the first conversion from the schematic all those nets lost their netclass. I'll cleanup the patch I have, hopefully tomorrow. regards, Mark. Maciej Suminski wrote: Hi Mark, I do not remember exactly how net classes work in Eagle, but if you can specify there anything that is supported by KiCad (track width, via size, etc.) then it makes sense to handle at least that part. We can implement the remaining settings as soon as the DRC receives the planned upgrade. Cheers, Orson On 1/10/19 3:56 PM, Wayne Stambaugh wrote: > Hi Mark, > > Thanks for the information. Part of version 6 development is to design > a better constraint system which netclass to netclass clearance will > most likely be included. At that point, importing this form Eagle will > make sense assuming your assessment is correct. This obviously requires > a file format change which which would violate the project policy of not > making file format changes during a stable version series. I will > change the bug report milestone to v6 unless someone else can think of a > reason to not change it. > > Cheers, > > Wayne > > On 1/10/2019 1:42 AM, mdoes...@xs4all.nl wrote: >> I just had a look at the pending buglist and saw #1754130 Eagle import >> ignores net class and net class settings. >> >> I have a patch for that, but the reason I did not post it, is because >> it is pretty useless (for me at least). Kicad does not support setting >> netclass to netclass clearances, but eagle does. Also the netnames are >> changed at the first conversion from schematic to PCB. >> >> If there still interest in this patch, I can (clean it up and) post it. >> >> regards, >> >> Mark. >> >> ___ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp >> > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] Bug 1754130
I just had a look at the pending buglist and saw #1754130 Eagle import ignores net class and net class settings. I have a patch for that, but the reason I did not post it, is because it is pretty useless (for me at least). Kicad does not support setting netclass to netclass clearances, but eagle does. Also the netnames are changed at the first conversion from schematic to PCB. If there still interest in this patch, I can (clean it up and) post it. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] Plugin in C++
I've seen it is possible to write action plugins in python, I would rather do this kind of stuff in C++. In the sources I've found only some file loaders/savers and 3D stuff. Is the kind of plugin like "replicate layout" possible from C++? And if it is, is there some kind of example? regards, Mark ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Net ties and copper DRC
Hello Seth, I never even knew this feature existed. So basically copper which is not a pad is ignored during DRC? That's fine, you should not do that unless you're doing something weird. regards, Mark. Seth Hillbrand wrote: Hi Mark- This is the current 5.0 behavior, so nothing is changing in this respect. The issue is that users have designed boards with 5.0 and the 5.0 nettie libraries. We do not want 5.1 to change things in a way that causes existing boards to fail DRC. -S ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Net ties and copper DRC
Ignoring clearances in a footprint sound scary to me. Doing 1kV designs I want the clearances checked, so Ik know I've chosen the wrong footprint. How about creating special pin names xxx_nettie just like the special netnames for differential pairs? regards, Mark. Seth Hillbrand wrote: Hi Jeff- What about just avoiding DRC between footprint graphic items and the other items in the same footprint? That would avoid the file format change while keeping the purpose of the DRC (mostly). Best- Seth ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] GAL canvas strategy - testers needed!
Found another bug. When importing sheet pins, the pin can be placed and is visible during placement. Once placed it is no-longer visible. When I quit eeschema and start it with the same file, the sheet label is visible and right where I left it. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] GAL canvas strategy - testers needed!
I don't think I mailed the list, but also found another issue. I noticed the sheet text is the same color as "notes", and not "sheet label". The cursor cross-hair is always black. Otherwise it works fine for me on a quick test. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] GAL canvas strategy - testers needed!
I've given the GAL version a test-drive. Here are some issues I noted. I guess most of it is because the black background was not tested before. 1. Grid color always black. (Not visible on black background) 2. Hierarchical sheet color always white. 3. When using another background color (for example 1,1,1) the sheet color is correct after zooming. When moving the mouse the sheet color gradually changes to white. Sometimes a double picture is shown, see attachment. The background color was 1,1,1 for this schematic. kicad_gal.png Description: Binary data ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] [PATCH] Import attributes and variants from eagle.
Hello Seth, As requested an example eagle project using variants. regards Mark. eagle_variant.tgz Description: Binary data ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] [PATCH] Import attributes and variants from eagle.
Hello Seth, I don't know how to use eagle myself, but will ask a colleague to create a small sample project. He's on vacation right now but will be back next week. regards, Mark. ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
[Kicad-developers] [PATCH] Import attributes and variants from eagle.
From: Mark van Doesburg
Here is a patch that copies all attributes from an original eagle
schematic. This is necessary for me to keep the BOM the same.
Since kicad does not yet support variants, it creates additional fields
for values that differ for variants. It prefixes them with "VARIANT_"
---
common/eagle_parser.cpp | 31
eeschema/sch_eagle_plugin.cpp | 39 +++
include/eagle_parser.h| 2 ++
3 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/common/eagle_parser.cpp b/common/eagle_parser.cpp
index 60aa52612..6d8aa3fe5 100644
--- a/common/eagle_parser.cpp
+++ b/common/eagle_parser.cpp
@@ -884,8 +884,39 @@ EPART::EPART( wxXmlNode* aPart )
library = parseRequiredAttribute( aPart, "library" );
deviceset = parseRequiredAttribute( aPart, "deviceset" );
device = parseRequiredAttribute( aPart, "device" );
+
technology = parseOptionalAttribute( aPart, "technology" );
value = parseOptionalAttribute( aPart, "value" );
+
+for( auto child = aPart->GetChildren( ); child; child = child->GetNext(
) )
+{
+ if( child->GetName( ) == "attribute" )
+ {
+ std::string aname, avalue;
+ for( auto x = child->GetAttributes( ); x; x = x->GetNext( ) )
+ {
+ if( x->GetName( ) == "name" )
+ aname = x->GetValue( );
+ else if( x->GetName( ) == "value" )
+ avalue = x->GetValue( );
+ }
+ if( aname.size( ) && avalue.size( ) )
+ attribute[aname] = avalue;
+ }
+ else if( child->GetName( ) == "variant" )
+ {
+ std::string aname, avalue;
+ for( auto x = child->GetAttributes( ); x; x = x->GetNext( ) )
+ {
+ if( x->GetName( ) == "name" )
+ aname = x->GetValue( );
+ else if( x->GetName( ) == "value" )
+ avalue = x->GetValue( );
+ }
+ if( aname.size( ) && avalue.size( ) )
+ variant[aname] = avalue;
+ }
+}
}
diff --git a/eeschema/sch_eagle_plugin.cpp b/eeschema/sch_eagle_plugin.cpp
index 0b36e1f25..c7a999c5b 100644
--- a/eeschema/sch_eagle_plugin.cpp
+++ b/eeschema/sch_eagle_plugin.cpp
@@ -1142,6 +1142,22 @@ void SCH_EAGLE_PLUGIN::loadInstance( wxXmlNode*
aInstanceNode )
component->GetField( REFERENCE )->SetVisible( part->GetField( REFERENCE
)->IsVisible() );
component->GetField( VALUE )->SetVisible( part->GetField( VALUE
)->IsVisible() );
+for( auto a:epart->attribute )
+{
+ auto field = component->AddField( SCH_FIELD( *component->GetField(
VALUE ) ) );
+ field->SetName( a.first );
+ field->SetText( a.second );
+ field->SetVisible( false );
+}
+
+for( auto a:epart->variant )
+{
+ auto field = component->AddField( SCH_FIELD( *component->GetField(
VALUE ) ) );
+ field->SetName( "VARIANT_" + a.first );
+ field->SetText( a.second );
+ field->SetVisible( false );
+}
+
bool valueAttributeFound = false;
bool nameAttributeFound = false;
@@ -1157,18 +1173,20 @@ void SCH_EAGLE_PLUGIN::loadInstance( wxXmlNode*
aInstanceNode )
SCH_FIELD* field;
-if( attr.name.Lower() == "name" || attr.name.Lower() == "value" )
+if( attr.name.Lower() == "name" || attr.name.Lower() == "value" ||
(field = component->FindField( attr.name )))
{
if( attr.name.Lower() == "name" )
{
field = component->GetField( REFERENCE );
nameAttributeFound = true;
}
-else
+else if( attr.name.Lower() == "value" )
{
field = component->GetField( VALUE );
valueAttributeFound = true;
-}
+} else {
+field->SetVisible( false );
+ }
field->SetPosition( wxPoint( attr.x->ToSchUnits(),
-attr.y->ToSchUnits() ) );
int align = attr.align ? *attr.align : ETEXT::BOTTOM_LEFT;
@@ -1189,7 +1207,20 @@ void SCH_EAGLE_PLUGIN::loadInstance( wxXmlNode*
aInstanceNode )
eagleToKicadAlignment( (EDA_TEXT*) field, align, reldegrees,
mirror, spin,
absdegrees );
-}
+}
+}
+else if( attributeNode->GetName() == "variant" )
+{
+ wxString variant, value;
+
+ if( attributeNode->GetAttribute( "name", )
+ && attributeNode->GetAttribute( "value", ) )
+ {
+ auto field = component->AddField( SCH_FIELD(
*component->GetField( VALUE ) ) );
+ field->SetName( "VARIANT_" + variant );
+ field->SetText( value );
+ field->SetVisible( false );
+ }
}
