On 07/16/2015 01:23 AM, Thomas Huth wrote:
On 07/15/2015 09:58 PM, Nathan Fontenot wrote:
On 07/15/2015 09:35 AM, Thomas Huth wrote:
On 07/14/2015 11:22 PM, Benjamin Herrenschmidt wrote:
On Tue, 2015-07-14 at 20:43 +0200, Thomas Huth wrote:
Any suggestions how to fix this? Simply revert
On Wed, Jul 08, 2015 at 05:19:13PM +0100, Marc Zyngier wrote:
With the ARMv8.1 VHE, the architecture is able to (almost) transparently
run the kernel at EL2, despite being written for EL1.
This patch takes care of the almost part, mostly preventing the kernel
from dropping from EL2 to EL1,
On Wed, Jul 08, 2015 at 05:19:14PM +0100, Marc Zyngier wrote:
Having both VHE and non-VHE capable CPUs in the same system
is likely to be a recipe for disaster.
If the boot CPU has VHE, but a secondary is not, we won't be
able to downgrade and run the kernel at EL1. Add CPU hotplug
to the
From: James Hogan james.ho...@imgtec.com
In case we're running on a 64-bit host, be sure to sign extend the
general purpose registers and hi/lo/pc before writing them to KVM, so as
to take advantage of MIPS32/MIPS64 compatibility.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo
From: James Hogan james.ho...@imgtec.com
Fix access to 32-bit registers on big endian targets. The pointer passed
to the kernel must be for the actual 32-bit value, not a temporary
64-bit value, otherwise on big endian systems the kernel will only
interpret the upper half.
Signed-off-by: James
On Mon, Jul 06, 2015 at 10:17:32AM +0800, shannon.z...@linaro.org wrote:
From: Shannon Zhao shannon.z...@linaro.org
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for
On Mon, Jul 06, 2015 at 10:17:34AM +0800, shannon.z...@linaro.org wrote:
From: Shannon Zhao shannon.z...@linaro.org
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN. Add access handler which emulates
writing and reading PMCR_EL0 register.
On 07/15/2015 09:58 PM, Nathan Fontenot wrote:
On 07/15/2015 09:35 AM, Thomas Huth wrote:
On 07/14/2015 11:22 PM, Benjamin Herrenschmidt wrote:
On Tue, 2015-07-14 at 20:43 +0200, Thomas Huth wrote:
Any suggestions how to fix this? Simply revert 587f83e8dd50d? Use
mdelay() instead of msleep()
On Thu, 2 Jul 2015 15:08:11 +0200
Igor Mammedov imamm...@redhat.com wrote:
it became possible to use a bigger amount of memory
slots, which is used by memory hotplug for
registering hotplugged memory.
However QEMU crashes if it's used with more than ~60
pc-dimm devices and vhost-net enabled
Whenever a vcore state is VCORE_PREEMPT we need to be counting stolen
time for it. This currently isn't the case when we have a vcore that
no longer has any runnable threads in it but still has a runner task,
so we do an explicit call to kvmppc_core_start_stolen() in that case.
Signed-off-by:
When a vcore gets preempted, we put it on the preempted vcore list for
the current CPU. The runner task then calls schedule() and comes back
some time later and takes itself off the list. We need to be careful
to lock the list that it was put onto, which may not be the list for the
current CPU
When a vcore gets preempted, we put it on the preempted vcore list for
the current CPU. The runner task then calls schedule() and comes back
some time later and takes itself off the list. We need to be careful
to lock the list that it was put onto, which may not be the list for the
current CPU
This series contains two fixes for the new dynamic micro-threading
code that was added recently for HV-mode KVM on Power servers.
The patches are against Alex Graf's kvm-ppc-queue branch. Please
apply.
Paul.
arch/powerpc/kvm/book3s_hv.c | 12 +---
1 file changed, 9 insertions(+), 3
Whenever a vcore state is VCORE_PREEMPT we need to be counting stolen
time for it. This currently isn't the case when we have a vcore that
no longer has any runnable threads in it but still has a runner task,
so we do an explicit call to kvmppc_core_start_stolen() in that case.
Signed-off-by:
This series contains two fixes for the new dynamic micro-threading
code that was added recently for HV-mode KVM on Power servers.
The patches are against Alex Graf's kvm-ppc-queue branch. Please
apply.
Paul.
arch/powerpc/kvm/book3s_hv.c | 12 +---
1 file changed, 9 insertions(+), 3
On 15/07/2015 22:02, C. Bröcker wrote:
What OS is this? Is it RHEL/CentOS? If so, halt_poll_ns will be in 6.7
which will be out in a few days/weeks.
Paolo
OK. As said CentOS 6.6.
But where do I put this parameter?
You can add kvm.halt_poll_ns=50 to the kernel command line. If
you
On Tue, Jul 14, 2015 at 04:02:39PM +0300, Pavel Fedin wrote:
Hello!
You may want to check commit 8a14849, which makes this whole patch
irrelevant.
Thank you very much for pointing out, i will recheck.
My patches are based on linux-stable.git, should i base them on something
else?
On 15/07/2015 21:16, Andres Lagar-Cavilla wrote:
+static int kvm_mmu_notifier_clear_young(struct mmu_notifier *mn,
+ struct mm_struct *mm,
+ unsigned long start,
+ unsigned
On 16/07/2015 09:11, Paul Mackerras wrote:
This series contains two fixes for the new dynamic micro-threading
code that was added recently for HV-mode KVM on Power servers.
The patches are against Alex Graf's kvm-ppc-queue branch. Please
apply.
Paul.
arch/powerpc/kvm/book3s_hv.c | 12
On 16/07/2015 09:11, Paul Mackerras wrote:
This series contains two fixes for the new dynamic micro-threading
code that was added recently for HV-mode KVM on Power servers.
The patches are against Alex Graf's kvm-ppc-queue branch. Please
apply.
Paul.
arch/powerpc/kvm/book3s_hv.c | 12
On 27/05/2015 01:56, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed as such.
This patch corrects places where it is accessed as a 32 bit field by a
64 bit kernel. In
On 16-7-2015 13:27, Paolo Bonzini wrote:
On 15/07/2015 22:02, Hansa wrote:
What OS is this? Is it RHEL/CentOS? If so, halt_poll_ns will be in 6.7
which will be out in a few days/weeks.
Paolo
OK. As said CentOS 6.6.
But where do I put this parameter?
You can add kvm.halt_poll_ns=50 to
From: James Hogan james.ho...@imgtec.com
Fix access to 32-bit registers on big endian targets. The pointer passed
to the kernel must be for the actual 32-bit value, not a temporary
64-bit value, otherwise on big endian systems the kernel will only
interpret the upper half.
Signed-off-by: James
From: James Hogan james.ho...@imgtec.com
In case we're running on a 64-bit host, be sure to sign extend the
general purpose registers and hi/lo/pc before writing them to KVM, so as
to take advantage of MIPS32/MIPS64 compatibility.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo
On Fri, Jul 10, 2015 at 06:19:05PM -0700, Mario Smarduch wrote:
This is a followp to previous iteration but implemented on top of VHE
patches.
Only non-VHE path is addressied by this patch. In second patch 32-bit handler
is updated to keep exit handling consistent with 64-bit code, and
On Thu, Jul 16, 2015 at 11:23:08AM -0700, Mario Smarduch wrote:
On 07/16/2015 08:52 AM, Christoffer Dall wrote:
On Fri, Jul 10, 2015 at 06:19:05PM -0700, Mario Smarduch wrote:
This is a followp to previous iteration but implemented on top of VHE
patches.
Only non-VHE path is addressied
On 07/16/2015 12:05 PM, Christoffer Dall wrote:
On Thu, Jul 16, 2015 at 11:23:08AM -0700, Mario Smarduch wrote:
On 07/16/2015 08:52 AM, Christoffer Dall wrote:
On Fri, Jul 10, 2015 at 06:19:05PM -0700, Mario Smarduch wrote:
This is a followp to previous iteration but implemented on top of VHE
On 05/27/2015 01:56 AM, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is
accessed as such.
This patch corrects places where it is accessed as a 32 bit field by a
64 bit kernel. In
On Wed, Jul 08, 2015 at 05:19:06PM +0100, Marc Zyngier wrote:
Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the
CPU has the ARMv8,1 VHE capability.
This will be used to trigger kernel patching in KVM.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Will Deacon
On 07/16/2015 08:52 AM, Christoffer Dall wrote:
On Fri, Jul 10, 2015 at 06:19:05PM -0700, Mario Smarduch wrote:
This is a followp to previous iteration but implemented on top of VHE
patches.
Only non-VHE path is addressied by this patch. In second patch 32-bit
handler
is updated to keep
After enhancing arm64 FP/SIMD exit handling, ARMv7 VFP exit branch is moved
to guest trap handling. This allows us to keep exit handling flow between both
architectures consistent.
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/kvm/interrupts.S | 14 --
1 file
Currently we save/restore fp/simd on each exit. The first patch optimizes arm64
save/restore, we only do so on Guest access. hackbench and several lmbench
tests show anywhere from 30% to 50% of exits don't context switch the vfp/simd
registers.
For second patch 32-bit handler is updated to keep
This patch only saves and restores FP/SIMD registers on Guest access. To do
this cptr_el2 FP/SIMD trap is set on Guest entry and later checked on exit.
lmbench, hackbench show significant improvements, for 30-50% exits FP/SIMD
context is not saved/restored
Signed-off-by: Mario Smarduch
On Mon, Jul 06, 2015 at 10:17:33AM +0800, shannon.z...@linaro.org wrote:
From: Shannon Zhao shannon.z...@linaro.org
We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.
When a physical I/O device is assigned to a virtual machine through
facilities like VFIO and KVM, the interrupt for the device generally
bounces through the host system before being injected into the VM.
However, hardware technologies exist that often allow the host to be
bypassed for some of
On Wed, Jul 08, 2015 at 05:19:04PM +0100, Marc Zyngier wrote:
With ARMv8.1 VHE extension, it will be possible to run the kernel
at EL2 (aka HYP mode). In order for the kernel to easily find out
where it is running, add a new predicate that returns whether or
not the kernel is in HYP mode.
On 17/07/2015 02:35, Andy Lutomirski wrote:
Right now, NPT page attributes are not used, and the final page
attribute depends solely on gPAT (which however is not synced
correctly), the guest MTRRs and the guest page attributes.
However, we can do better by mimicking what is done for VMX.
On 07/07/2015 06:45 AM, Paolo Bonzini wrote:
Right now, NPT page attributes are not used, and the final page
attribute depends solely on gPAT (which however is not synced
correctly), the guest MTRRs and the guest page attributes.
However, we can do better by mimicking what is done for VMX.
In
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