FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it
to mmu.c to stop being compiled multiple times
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 8
arch/x86/kvm/paging_tmpl.h | 13 ++---
2 files changed, 10
CCed Pavel Shirshov ru.pc...@gmail.com
Sorry, git tool missed to CC mail to the person tagged with Reported-by
and Tested-by. :(
On 08/04/2015 06:59 PM, Xiao Guangrong wrote:
Current code validating mmio #PF is buggy, it was spotted by Pavel
Shirshov, the bug is that qemu complained with KVM:
We got the bug that qemu complained with KVM: unknown exit, hardware
reason 31 and KVM shown these info:
[84245.284948] EPT: Misconfiguration.
[84245.285056] EPT: GPA: 0xfeda848
[84245.285154] ept_misconfig_inspect_spte: spte 0x5eaef50107 level 4
[84245.285344] ept_misconfig_inspect_spte: spte
The #PF with PFEC.RSV = 1 is designed to speed MMIO emulation, however,
it is possible that the RSV #PF is caused by real BUG by mis-configure
shadow page table entries
This patch enables full check for the reserved bits on shadow page table
entries and dump the shadow page table hierarchy is the
We have the same data struct to check reserved bits on guest page tables
and shadow page tables, split is_rsvd_bits_set() so that the logic can be
shared between these two paths
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 28 +++-
The logic used to check ept misconfig is completely contained in common
reserved bits check for sptes, so it can be removed
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 22
arch/x86/kvm/mmu.h | 1 -
arch/x86/kvm/vmx.c | 74
Current code validating mmio #PF is buggy, it was spotted by Pavel
Shirshov, the bug is that qemu complained with KVM: unknown exit,
hardware reason 31 and KVM shown these info:
[84245.284948] EPT: Misconfiguration.
[84245.285056] EPT: GPA: 0xfeda848
[84245.285154] ept_misconfig_inspect_spte: spte
These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are
used to check if reserved bits set on guest ptes, move them to a data
struct so that the approach can be applied to check reserved bits on host
shadow page table entries
Signed-off-by: Xiao Guangrong
Since softmmu AMD nested shadow page tables and guest page tables have
the same format, split reset_rsvds_bits_mask so that the logic can be
reused by later patches which check reserved bits on sptes
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 26
Since shdow ept page tables and intel nested guest page tables have the
same format, split reset_rsvds_bits_mask_ept so that the logic can be
reused by later patches which check reserved bits on sptes
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 14
We have abstracted the data struct and functions which are used to check
reserved bit on guest page tables, now we extend the logic to check
reserved bits on shadow page tables
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/include/asm/kvm_host.h | 1 +
Hi Aliyun,
On Tue, Aug 04, 2015 at 03:05:50PM +0800, security wrote:
One of our whitehats has just reported an vulnerability to us. It is an
integer overflow problem of KVM WindowsGuestDrivers of VirtIO (Path:
kvm-guest-drivers-windows/NetKVM/DebugTools/VirtioConsoleSimulation/).
We
On Fri, Jul 24, 2015 at 04:55:08PM +0100, Marc Zyngier wrote:
In order to remove the crude hack where we sneak the masked bit
into the timer's control register, make use of the phys_irq_map
API control the active state of the interrupt.
This causes some limited changes to allow for potential
On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can be
inferred from the IOAPIC routes but the TMR cannot. The hardware
behavior on the other hand can be implemented purely within the LAPIC.
So updating the TMR within LAPIC is the
On Tue, Aug 04, 2015 at 01:53:24PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:27PM +0200, Andrew Jones wrote:
QEMU loads the unit test, but due to the way it translates the
unit test's linker VMA to the LMA, we can't just link such that
VMA == LMA. Thus, we link with VMA ==
On Tue, Aug 04, 2015 at 01:53:24PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:27PM +0200, Andrew Jones wrote:
QEMU loads the unit test, but due to the way it translates the
unit test's linker VMA to the LMA, we can't just link such that
VMA == LMA. Thus, we link with VMA ==
On Tue, Aug 04, 2015 at 02:09:52PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 07:08:17PM +0200, Paolo Bonzini wrote:
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones
Hi team,
One of our whitehats has just reported an vulnerability to us. It is an
integer overflow problem of KVM WindowsGuestDrivers of VirtIO (Path:
kvm-guest-drivers-windows/NetKVM/DebugTools/VirtioConsoleSimulation/).
We don't know where to report this vulnerability to, so could you tell
alvise rigo a.r...@virtualopensystems.com writes:
On Mon, Aug 3, 2015 at 6:06 PM, Alex Bennée alex.ben...@linaro.org wrote:
alvise rigo a.r...@virtualopensystems.com writes:
On Mon, Aug 3, 2015 at 12:30 PM, Alex Bennée alex.ben...@linaro.org
wrote:
alvise rigo
-Original Message-
From: Pranavkumar Sawargaonkar [mailto:pranavku...@linaro.org]
Sent: Tuesday, August 04, 2015 11:18 AM
To: Bhushan Bharat-R65777
Cc: kvm@vger.kernel.org; Alex Williamson; kvm...@lists.cs.columbia.edu;
linux-arm-ker...@lists.infradead.org;
On Mon, Aug 03, 2015 at 07:51:51PM +0200, Andrew Jones wrote:
Inspired by a patch by Alex Bennée. This version uses a new
unittests.cfg variable and includes support for DRYRUN.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Another difference with Alex's patch is we no longer output
On Tue, Aug 04, 2015 at 02:09:52PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 07:08:17PM +0200, Paolo Bonzini wrote:
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones
At least on the ARM side of things we're making sure unit tests can
be used for [MT]TCG, as well as for KVM. This series adds support to
unittests.cfg to allow us to specify kvm vs. tcg, as not all tests
will be able (should/need) to run on both. The first patch is a repost
of one of Alex's
With this $TEST_DIR/run can output test specific error messages.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
run_tests.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/run_tests.sh b/run_tests.sh
index ebb7e9fe6fdfc..80b87823c3358 100755
--- a/run_tests.sh
+++
Inspired by a patch by Alex Bennée. This version uses a new
unittests.cfg variable and includes support for mkstandalone.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
arm/run | 43 +--
arm/unittests.cfg | 4 +++-
run_tests.sh
From: Alex Bennée alex.ben...@linaro.org
This is useful information for the run scripts to know, especially if
they want to drop to using TCG.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Andrew Jones drjo...@redhat.com
---
configure | 2 ++
1 file changed, 2 insertions(+)
Hello!
I think this flag should be kept, as it really indicates what is valid
in the MSI structure. It also has other benefits such as making obvious
what userspace expects, which can then be checked against the kernel's
own expectations.
I'm OK with the flag despite it's indeed a small
Paolo Bonzini wrote on 2015-08-04:
On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can be
inferred from the IOAPIC routes but the TMR cannot. The hardware
behavior on the other hand can be implemented purely within the LAPIC.
So
On Tue, Aug 04, 2015 at 01:50:39PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:25PM +0200, Andrew Jones wrote:
Add the hvcall for putchar and use it in puts. That, along with a
couple more lines in start to prepare for C code, and a branch to
main(), gets us hello world. Run
On Tue, Aug 04, 2015 at 01:50:39PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:25PM +0200, Andrew Jones wrote:
Add the hvcall for putchar and use it in puts. That, along with a
couple more lines in start to prepare for C code, and a branch to
main(), gets us hello world. Run
On Tue, Aug 04, 2015 at 02:03:24PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/powerpc/asm/rtas.h | 27
On Tue, Aug 04, 2015 at 02:11:30PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/powerpc/asm/rtas.h | 27
Hi,
Thank you for reaching out.
Please send the report to me.
But to be clear on the indicated path -
kvm-guest-drivers-windows/NetKVM/DebugTools/VirtioConsoleSimulation/ - this is
not part of the actual production code or part of the code that runs in kernel.
It is a legacy simulator that
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev support
then we should target using pci to expose it. I'm ok with that,
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev support
then we should target using pci to expose it. I'm ok with that,
On 08/04/2015 09:23 PM, Paolo Bonzini wrote:
On 04/08/2015 15:10, Xiao Guangrong wrote:
This should be cpu_has_nx, I think.
cpu_has_nx() checks the feature on host CPU, however, this is the shadow
page table which completely follow guest's features.
E.g, if guest does not
On Fri, Jul 24, 2015 at 04:55:07PM +0100, Marc Zyngier wrote:
Virtual interrupts mapped to a HW interrupt should only be triggered
from inside the kernel. Otherwise, you could end up confusing the
kernel (and the GIC's) state machine.
Rearrange the injection path so that kvm_vgic_inject_irq
On Fri, Jul 24, 2015 at 04:55:09PM +0100, Marc Zyngier wrote:
So far, the only use of the HW interrupt facility is the timer,
implying that the active state is context-switched for each vcpu,
as the device is is shared across all vcpus.
This does not work for a device that has been assigned
On Fri, Jul 24, 2015 at 04:55:02PM +0100, Marc Zyngier wrote:
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list registers.
This patch provides implementations for both GICv2 and GICv3.
Signed-off-by: Marc Zyngier
On Fri, Jul 24, 2015 at 04:55:05PM +0100, Marc Zyngier wrote:
To allow a HW interrupt to be injected into a guest, we lookup the
guest virtual interrupt in the irq_phys_map list, and if we have
a match, encode both interrupts in the LR.
We also mark the interrupt as active at the host
Crap. Forgot -v2 on my format-patch command line...
Paolo, should I repost?
drew
On Tue, Aug 04, 2015 at 09:25:52AM +0200, Andrew Jones wrote:
At least on the ARM side of things we're making sure unit tests can
be used for [MT]TCG, as well as for KVM. This series adds support to
On Tue, Aug 04, 2015 at 02:11:30PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/powerpc/asm/rtas.h | 27
On Tue, Aug 04, 2015 at 02:03:24PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew Jones drjo...@redhat.com
---
lib/powerpc/asm/rtas.h | 27
On Fri, Jul 24, 2015 at 04:55:04PM +0100, Marc Zyngier wrote:
In order to be able to feed physical interrupts to a guest, we need
to be able to establish the virtual-physical mapping between the two
worlds.
The mappings are kept in a set of RCU lists, indexed by virtual interrupts.
On 08/04/2015 08:14 PM, Paolo Bonzini wrote:
On 04/08/2015 12:59, Xiao Guangrong wrote:
+/*
+ * the page table on host is the shadow page table for the page
+ * table in guest or amd nested guest, its mmu features completely
+ * follow the features in guest.
+ */
+void
On 04/08/2015 12:59, Xiao Guangrong wrote:
+/*
+ * the page table on host is the shadow page table for the page
+ * table in guest or amd nested guest, its mmu features completely
+ * follow the features in guest.
+ */
+void
+reset_shadow_rsvds_bits_mask(struct kvm_vcpu *vcpu, struct
On Tue, Jul 21, 2015 at 05:38:52PM +0100, Marc Zyngier wrote:
On 17/07/15 20:50, Christoffer Dall wrote:
On Wed, Jul 08, 2015 at 06:56:36PM +0100, Marc Zyngier wrote:
Now that struct vgic_lr supports the LR_HW bit and carries a hwirq
field, we can encode that information into the list
On Tue, Jul 21, 2015 at 07:01:13PM +0100, Marc Zyngier wrote:
On 17/07/15 23:15, Christoffer Dall wrote:
On Wed, Jul 08, 2015 at 06:56:42PM +0100, Marc Zyngier wrote:
So far, the only use of the HW interrupt facility is the timer,
implying that the active state is context-switched for each
On Tue, Aug 04, 2015 at 03:15:25PM +0200, Paolo Bonzini wrote:
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev
On Tue, Aug 04, 2015 at 03:15:25PM +0200, Paolo Bonzini wrote:
On 04/08/2015 09:47, Andrew Jones wrote:
In early development we did have a hypercall mediated virtio model,
but it was abandoned once we got PCI working.
So I think by yours and Alex's responses, if we want testdev
On 04/08/2015 15:10, Xiao Guangrong wrote:
This should be cpu_has_nx, I think.
cpu_has_nx() checks the feature on host CPU, however, this is the shadow
page table which completely follow guest's features.
E.g, if guest does not execution-protect the physical page, then
KVM does not do
On 04/08/15 14:04, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:04PM +0100, Marc Zyngier wrote:
In order to be able to feed physical interrupts to a guest, we need
to be able to establish the virtual-physical mapping between the two
worlds.
The mappings are kept in a set of RCU
https://bugzilla.kernel.org/show_bug.cgi?id=102301
Bug ID: 102301
Summary: Shutting down a Windowvs 10 virtual machine (with VGA
passthrough) causes a hard crash, every time
Product: Virtualization
Version: unspecified
Kernel
On 08/05/2015 12:58 AM, Alex Williamson wrote:
The patch was munged on commit to re-order these tests resulting in
excessive warnings when trying to do device assignment. Return to
original ordering: https://lkml.org/lkml/2015/7/15/769
Reviewed-by: Xiao Guangrong
Changelog in v2:
- rename reset_*_rsvds_bits_mask() to reset_*_zero_bits_mask() and
is_shadow_rsvd_bits_set() to is_shadow_zero_bits_set() to better
match what we are checking. Thanks for Paolo's suggestion.
Current code validating mmio #PF is buggy, it was spotted by Pavel
Shirshov, the bug
To detach tap device automatically from bridge when exiting,
just like what the reverse of script does.
Signed-off-by: Fan Du fan...@intel.com
---
include/kvm/virtio-net.h | 1 +
virtio/net.c | 49
2 files changed, 38 insertions(+),
The patch was munged on commit to re-order these tests resulting in
excessive warnings when trying to do device assignment. Return to
original ordering: https://lkml.org/lkml/2015/7/15/769
Fixes: 3e5d2fdceda1 (KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type)
Signed-off-by: Alex Williamson
On Tue, Aug 04, 2015 at 04:27:03PM +0100, Marc Zyngier wrote:
On 04/08/15 14:04, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:04PM +0100, Marc Zyngier wrote:
In order to be able to feed physical interrupts to a guest, we need
to be able to establish the virtual-physical mapping
On Tue, Aug 04, 2015 at 05:02:41PM +0100, Marc Zyngier wrote:
On 04/08/15 14:45, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:07PM +0100, Marc Zyngier wrote:
Virtual interrupts mapped to a HW interrupt should only be triggered
from inside the kernel. Otherwise, you could end up
On 04/08/15 18:36, Christoffer Dall wrote:
On Tue, Aug 04, 2015 at 04:27:03PM +0100, Marc Zyngier wrote:
On 04/08/15 14:04, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:04PM +0100, Marc Zyngier wrote:
In order to be able to feed physical interrupts to a guest, we need
to be able to
On 04/08/15 17:21, Eric Auger wrote:
Hi Marc,
On 07/24/2015 05:55 PM, Marc Zyngier wrote:
Virtual interrupts mapped to a HW interrupt should only be triggered
from inside the kernel. Otherwise, you could end up confusing the
kernel (and the GIC's) state machine.
Rearrange the injection path
On Tue, Aug 04, 2015 at 05:14:53PM +0100, Marc Zyngier wrote:
On 04/08/15 14:56, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:08PM +0100, Marc Zyngier wrote:
In order to remove the crude hack where we sneak the masked bit
into the timer's control register, make use of the
On Tue, Aug 04, 2015 at 06:08:53PM +0100, Marc Zyngier wrote:
On 04/08/15 15:32, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:09PM +0100, Marc Zyngier wrote:
So far, the only use of the HW interrupt facility is the timer,
implying that the active state is context-switched for each
On 04/08/15 14:56, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:08PM +0100, Marc Zyngier wrote:
In order to remove the crude hack where we sneak the masked bit
into the timer's control register, make use of the phys_irq_map
API control the active state of the interrupt.
This causes
Hi Marc,
On 07/24/2015 05:55 PM, Marc Zyngier wrote:
Virtual interrupts mapped to a HW interrupt should only be triggered
from inside the kernel. Otherwise, you could end up confusing the
kernel (and the GIC's) state machine.
Rearrange the injection path so that kvm_vgic_inject_irq is
used
On 04/08/15 15:32, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:09PM +0100, Marc Zyngier wrote:
So far, the only use of the HW interrupt facility is the timer,
implying that the active state is context-switched for each vcpu,
as the device is is shared across all vcpus.
This does
On 04/08/15 14:45, Christoffer Dall wrote:
On Fri, Jul 24, 2015 at 04:55:07PM +0100, Marc Zyngier wrote:
Virtual interrupts mapped to a HW interrupt should only be triggered
from inside the kernel. Otherwise, you could end up confusing the
kernel (and the GIC's) state machine.
Rearrange the
These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are
used to check if reserved bits set on guest ptes, move them to a data
struct so that the approach can be applied to check host shadow page
table entries as well
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
We got the bug that qemu complained with KVM: unknown exit, hardware
reason 31 and KVM shown these info:
[84245.284948] EPT: Misconfiguration.
[84245.285056] EPT: GPA: 0xfeda848
[84245.285154] ept_misconfig_inspect_spte: spte 0x5eaef50107 level 4
[84245.285344] ept_misconfig_inspect_spte: spte
FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it
to mmu.c to stop being compiled multiple times
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 8
arch/x86/kvm/paging_tmpl.h | 13 ++---
2 files changed, 10
Since shdow ept page tables and intel nested guest page tables have the
same format, split reset_rsvds_bits_mask_ept so that the logic can be
reused by later patches which check zero bits on sptes
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 14
On Tue, Aug 04, 2015 at 09:54:44AM +0200, Andrew Jones wrote:
On Tue, Aug 04, 2015 at 02:11:30PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew
On Tue, Aug 04, 2015 at 09:47:59AM +0200, Andrew Jones wrote:
On Tue, Aug 04, 2015 at 02:09:52PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 07:08:17PM +0200, Paolo Bonzini wrote:
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and
On Tue, Aug 04, 2015 at 09:47:59AM +0200, Andrew Jones wrote:
On Tue, Aug 04, 2015 at 02:09:52PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 07:08:17PM +0200, Paolo Bonzini wrote:
On 03/08/2015 16:41, Andrew Jones wrote:
Add enough RTAS support to support power-off, and
On Tue, Aug 04, 2015 at 09:54:44AM +0200, Andrew Jones wrote:
On Tue, Aug 04, 2015 at 02:11:30PM +1000, David Gibson wrote:
On Mon, Aug 03, 2015 at 04:41:28PM +0200, Andrew Jones wrote:
Add enough RTAS support to support power-off, and apply it to
exit().
Signed-off-by: Andrew
-Original Message-
From: Andre Przywara [mailto:andre.przyw...@arm.com]
Sent: Tuesday, July 21, 2015 5:45 PM
To: Du, Fan; Will Deacon
Cc: kvm@vger.kernel.org; Marc Zyngier
Subject: Re: [PATCHv3 2/2] kvmtool: Restrict virtio queue number to 1 when
vhost on
Hi,
On 21/07/15 07:18, Fan Du
We have the same data struct to check reserved bits on guest page tables
and shadow page tables, split is_rsvd_bits_set() so that the logic can be
shared between these two paths
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 28 +++-
The #PF with PFEC.RSV = 1 is designed to speed MMIO emulation, however,
it is possible that the RSV #PF is caused by real BUG by mis-configure
shadow page table entries
This patch enables full check for the zero bits on shadow page table
entries which include not only the reserved bit on hardware
Since softmmu AMD nested shadow page tables and guest page tables have
the same format, split reset_rsvds_bits_mask so that the logic can be
reused by later patches which check zero bits on sptes
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 26
The logic used to check ept misconfig is completely contained in common
reserved bits check for sptes, so it can be removed
Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com
---
arch/x86/kvm/mmu.c | 22
arch/x86/kvm/mmu.h | 1 -
arch/x86/kvm/vmx.c | 74
We have abstracted the data struct and functions which are used to check
reserved bit on guest page tables, now we extend the logic to check
zero bits on shadow page tables
The zero bits on sptes include not only reserved bits on hardware but also
the bits sptes nerve used
Signed-off-by: Xiao
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