Some data structures are always stored in big endian. Among those are the LPPACA
fields as well as the shadow slb. These structures might be shared with a
hypervisor.
So whenever we access those fields, make sure we do so in big endian byte order.
Signed-off-by: Alexander Graf
---
arch/powerpc
Now that we've fixed all the issues that HV KVM code had on little endian
hosts, we can enable it in the kernel configuration for users to play with.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/kvm/Kconfig b
>From assembly code we might not only have to explicitly BE access 64bit values,
but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
in their respective byte-reverse or native form.
Signed-off-by: Alexander Graf
CC: Benjamin Herrenschmidt
---
arch/powerpc/incl
There are a few shared data structures between the host and the guest. Most
of them get registered through the VPA interface.
These data structures are defined to always be in big endian byte order, so
let's make sure we always access them in big endian.
Signed-off-by: Alexander Graf
---
isable AIL whenever a vcpu
is scheduled in.
This patch fixes running PR KVM on POWER8 bare metal for me.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_pr.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
ind
On 06.06.14 18:31, Paolo Bonzini wrote:
Il 06/06/2014 14:46, Alexander Graf ha scritto:
KVM tells us the number of GSIs it can handle inside the kernel. That
value is
basically KVM_MAX_IRQ_ROUTES. However when we try to set the GSI
mapping table,
it checks for
r = -EINVAL;
if
On 06.06.14 15:23, Cornelia Huck wrote:
On Fri, 06 Jun 2014 15:15:54 +0200
Alexander Graf wrote:
On 06.06.14 15:12, Cornelia Huck wrote:
On Fri, 6 Jun 2014 14:46:05 +0200
Alexander Graf wrote:
KVM tells us the number of GSIs it can handle inside the kernel. That value is
basically
On 06.06.14 15:12, Cornelia Huck wrote:
On Fri, 6 Jun 2014 14:46:05 +0200
Alexander Graf wrote:
KVM tells us the number of GSIs it can handle inside the kernel. That value is
basically KVM_MAX_IRQ_ROUTES. However when we try to set the GSI mapping table,
it checks for
r = -EINVAL
g all of the GSIs. To make sure we never
hit that limit, let's reduce the number of GSIs we get from KVM by one.
Signed-off-by: Alexander Graf
---
kvm-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kvm-all.c b/kvm-all.c
index 4e19eff..56a251b 100644
--- a/kvm-al
On 06.06.14 04:37, Eduardo Habkost wrote:
On Fri, Jun 06, 2014 at 03:21:04AM +0200, Borislav Petkov wrote:
On Fri, Jun 06, 2014 at 12:24:26AM +0200, Alexander Graf wrote:
But can we drop the EMULATED name somehow? Can we rename [1] the ioctl
to say GET_UNSUPPORTED_CPUID or something along
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and entry. Writing to VTB is not
allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
For some reason BUG() doesn't always trigger the
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
This patchset adds support for emulating VTB, IC and Doorbell features in P8.
Doorbell support is dummy since we don't support SMT cores with PR-KVM.
Thanks, applied patches 1 and 4 to kvm-ppc-queue.
Alex
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To unsubscribe from this list: send the
On 06.06.14 00:32, Alexander Graf wrote:
On 05.06.14 19:33, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05.06.14 17:50, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
virtual time base register is a per VM, per cpu register that needs
On 05.06.14 19:33, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05.06.14 17:50, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and
On 05.06.14 21:57, Eduardo Habkost wrote:
The new option will allow slow emulated features (the ones returned by
GET_EMULATED_CPUID) to be enabled. We don't want to allow them to be
enabled by accident, so they will be enabled only if emulation is
explicitly allowed by the user.
Use "x-" prefix
On 05.06.14 19:48, Eduardo Habkost wrote:
On Thu, Jun 05, 2014 at 06:58:17PM +0200, Alexander Graf wrote:
On 05.06.14 18:52, Paolo Bonzini wrote:
Il 05/06/2014 18:45, Alexander Graf ha scritto:
Only if you were using "-cpu somethingThatHasAVX", though, no?
Yes. The same argumen
On 05.06.14 17:50, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and entry. Writing to VTB is not
allowed in the privileged mode.
Signed-off
On 05.06.14 18:52, Paolo Bonzini wrote:
Il 05/06/2014 18:45, Alexander Graf ha scritto:
Only if you were using "-cpu somethingThatHasAVX", though, no?
Yes. The same argument goes the other way around. I want to use AVX
emulation, do "allow-emulation" and suddenly
On 05.06.14 18:52, Paolo Bonzini wrote:
Il 05/06/2014 18:45, Alexander Graf ha scritto:
Only if you were using "-cpu somethingThatHasAVX", though, no?
Yes. The same argument goes the other way around. I want to use AVX
emulation, do "allow-emulation" and suddenly
On 05.06.14 18:44, Paolo Bonzini wrote:
Il 05/06/2014 18:40, Alexander Graf ha scritto:
kvm_set_cpuid(cpuid);
but enabling all experimental features inside KVM just because we want
one or two of them is very counter-intuitive. Imagine we'd introduce
emulation support for AVX. Sud
On 05.06.14 18:26, Paolo Bonzini wrote:
Il 05/06/2014 18:24, Alexander Graf ha scritto:
On 05.06.14 18:12, Eduardo Habkost wrote:
This implements GET_SUPPORTED_CPUID support using an explicit option
for it:
"allow-emulation". We don't want any emulated feature to be enabled
On 05.06.14 18:12, Eduardo Habkost wrote:
This implements GET_SUPPORTED_CPUID support using an explicit option for it:
"allow-emulation". We don't want any emulated feature to be enabled by accident,
so they will be enabled only if the user explicitly wants to allow them.
So is this an all-or-
On 05.06.14 14:30, Benjamin Herrenschmidt wrote:
On Thu, 2014-06-05 at 13:56 +0200, Alexander Graf wrote:
What if we ask user space to give us a pointer to user space allocated
memory along with the TCE registration? We would still ask user space to
only use the returned fd for TCE
On 05.06.14 14:21, Alexander Graf wrote:
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
We don't have SMT support yet, hence we should not find a doorbell
message generated
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++
1 file change
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
We don't have SMT support yet, hence we should not find a doorbell
message generated
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_emulate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/powerpc/kvm/book
On 05.06.14 14:08, Aneesh Kumar K.V wrote:
virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and entry. Writing to VTB is not
allowed in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
On 05.06.14 09:25, Alexey Kardashevskiy wrote:
This reserves 2 capability numbers.
This implements an extended version of KVM_CREATE_SPAPR_TCE_64 ioctl.
Please advise how to proceed with these patches as I suspect that
first two should go via Paolo's tree while the last one via Alex Graf's tre
On 05.06.14 12:27, Benjamin Herrenschmidt wrote:
On Thu, 2014-06-05 at 19:26 +1000, Alexey Kardashevskiy wrote:
No trees yet. For 64GB window we need (64<<30)/(16<<20)*8 = 32K TCE table.
Do we really need trees?
The above is assuming hugetlbfs backed guests. These are the least of my worry
ind
On 04.06.14 13:17, Aneesh Kumar K.V wrote:
We use time base for PURR and SPURR emulation with PR KVM since we
are emulating a single threaded core. When using time base
we need to make sure that we don't accumulate time spent in the host
in PURR and SPURR value.
Also we don't need to emulate mt
On 04.06.14 17:05, Gabriel L. Somlo wrote:
On Wed, Jun 04, 2014 at 04:44:13PM +0200, Alexander Graf wrote:
On 04.06.14 16:39, Gabriel L. Somlo wrote:
Paolo,
I noticed the monitor=mwait=nop patch is making its way upstream, so
thanks !
I'm still interested in following up with something
On 04.06.14 16:39, Gabriel L. Somlo wrote:
Paolo,
I noticed the monitor=mwait=nop patch is making its way upstream, so
thanks !
I'm still interested in following up with something that would enable
this behavior only conditionally (e.g. following an ioctl call from
userspace to enable it only
On 06/03/2014 04:21 PM, Gabriel L. Somlo wrote:
On Tue, Jun 03, 2014 at 11:17:48AM +0200, Paolo Bonzini wrote:
I think it's fine as it is now. :)
On Mon, Jun 02, 2014 at 09:55:18PM -0400, Gabriel L. Somlo wrote:
W.r.t. monitor/mwait, a guest can do one of the following:
1. Never check CPUID,
> Am 02.06.2014 um 22:41 schrieb "Michael S. Tsirkin" :
>
>> On Mon, Jun 02, 2014 at 10:35:56PM +0200, Alexander Graf wrote:
>>
>>
>>>> Am 02.06.2014 um 22:20 schrieb "Michael S. Tsirkin" :
>>>>
>>>> On Mo
> Am 02.06.2014 um 22:20 schrieb "Michael S. Tsirkin" :
>
>> On Mon, Jun 02, 2014 at 09:48:19PM +0200, Alexander Graf wrote:
>>
>>
>>>> Am 02.06.2014 um 21:25 schrieb "Gabriel L. Somlo" :
>>>>
>>>> On Wed, May 07
their presence
>> via cpuid, to prevent compliant guests from using them inadvertently.
>>
>> Signed-off-by: Gabriel L. Somlo
>> ---
>>
>> New in v2: remove invalid_op handler functions which were only used to
>> handle exits caused by monitor
On 31.05.14 09:21, Paul Mackerras wrote:
This patch series adds a way for userspace to control which PAPR
hypercalls get handled by kernel handlers vs. being sent up to
userspace, and then adds an implementation of a new hypercall,
H_SET_MODE.
This version makes the KVM_CAP_PPC_ENABLE_HCALL cap
On 31.05.14 09:21, Paul Mackerras wrote:
This provides a way for userspace controls which PAPR hcalls get
handled in the kernel. Each hcall can be individually enabled or
disabled for in-kernel handling, except for H_RTAS. The exception
for H_RTAS is because userspace can already control wheth
> Am 30.05.2014 um 22:57 schrieb Eduardo Habkost :
>
>> On Fri, May 30, 2014 at 10:46:56PM +0200, Paolo Bonzini wrote:
>> Il 30/05/2014 22:41, Eduardo Habkost ha scritto:
>>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>>> index 2d2e2be..44956d6 100644
>>> --- a/include/hw/boards.h
>>
On 30.05.14 18:11, Paolo Bonzini wrote:
Il 30/05/2014 18:08, Alexander Graf ha scritto:
What happens if it returns EINVAL? Also, reset should certainly
try to write all registers, what happens if one is missed.
If it returns EINVAL we just ignore the register.
I wonder if it's the
On 30.05.14 18:03, Paolo Bonzini wrote:
Il 30/05/2014 17:58, Alexander Graf ha scritto:
Would new userspace with old kernel be able to detect that POWER8
support isn't quite complete?
It couldn't, no. It would try to run a guest - if it happens to work
we're lucky ;).
On 30.05.14 17:55, Paolo Bonzini wrote:
Il 30/05/2014 17:53, Alexander Graf ha scritto:
This is an ABI break, this symbol was added in 3.14. I think I should
revert this. Can you convince me otherwise?
There's nothing bad happening with the change. Newer user space won't be
ab
On 30.05.14 17:50, Paolo Bonzini wrote:
Il 30/05/2014 14:42, Alexander Graf ha scritto:
From: Paul Mackerras
Commit b005255e12a3 ("KVM: PPC: Book3S HV: Context-switch new POWER8
SPRs") added a definition of KVM_REG_PPC_WORT with the same register
number as the existing KVM_REG_
> Am 30.05.2014 um 14:58 schrieb Paolo Bonzini :
>
> Il 30/05/2014 14:42, Alexander Graf ha scritto:
>> Hi Paolo / Marcelo,
>>
>> This is my current patch queue for ppc. Please pull.
>>
>> Alex
>>
>>
>> The following chan
The "shadow SLB" in the PACA is shared with the hypervisor, so it has to
be big endian. We access the shadow SLB during world switch, so let's make
sure we access it in big endian even when we're on a little endian host.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/
From: "Aneesh Kumar K.V"
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_host.h | 2 +-
arch/powerpc/kernel/asm
The HTAB is always big endian. We access the guest's HTAB using
copy_from/to_user, but don't yet take care of the fact that we might
be running on an LE host.
Wrap all accesses to the guest HTAB with big endian accessors.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_32_
fs_ioctl+0x4d4/0x790
[c000ec59fd90] [c0225148] .SyS_ioctl+0x58/0xb0
[c000ec59fe30] [c000a1e4] syscall_exit+0x0/0x98
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_pr.c | 8
1 file changed, 8 insertions(+)
diff --gi
.
Alexander Graf (27):
KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR
KVM: PPC: E500: Add dcbtls emulation
KVM: PPC: Book3S: PR: Fix C/R bit setting
KVM: PPC: Book3S_32: PR: Access HTAB in big endian
KVM: PPC
Commit 9308ab8e2d made C/R HTAB updates go byte-wise into the target HTAB.
However, it didn't update the guest's copy of the HTAB, but instead the
host local copy of it.
Write to the guest's HTAB instead.
Signed-off-by: Alexander Graf
CC: Paul Mackerras
Acked-by: Paul Macke
that we can set to keep NX
functionality available.
Signed-off-by: Alexander Graf
---
Documentation/virtual/kvm/ppc-pv.txt | 14 ++
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/uapi/asm/kvm_para.h | 6 ++
arch/powerpc/kvm/book3s_64_mmu.c
mory.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 23 ++-
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index fb25ebc..f3289
In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 1 +
1 file chang
The only guests that want to see dcbz act as 32byte are book3s_32 guests, so
we don't have to worry about little endian instruction ordering. So let's
just always search for big endian dcbz instructions, also when we're on a
little endian host.
Signed-off-by: Alexander Gr
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf
---
arch/p
When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
that we don't emulate. Just ignore accesses to them.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/powerp
: Alexander Graf
---
arch/powerpc/kernel/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6a01752..5e6f24f 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -417,7 +417,7 @@ static void
to decode the base page size and the actual page size correctly from the
HPTE entry.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_book3s_64.h | 146 ++-
arch/powerpc/kvm/book3s_hv.c | 7 ++
2 fil
ion stream,
bail out graciously and just declare every hcall as error.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index c99244
!PR guest
mode while hardware is in PR and we don't really emulate the PMU anyway.
So instead, let's just leave it at emulation of all its registers.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s.c | 18 ++
arch/powerpc/kvm/book3s_emulate.c | 22 ++
POWER8 implements a new register called TAR. This register has to be
enabled in FSCR and then from KVM's point of view is mere storage.
This patch enables the guest to use TAR.
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_host.h | 2 ++
arch/powerpc/kernel/asm-offs
hv we maintain
the struct in host native endian, since it never gets shared with the guest.
For book3s_64 pr we introduce a variable that tells us which endianness the
shared struct is in and route every access to it through helper inline
functions that evaluate this variable.
Signed-off-by: Alex
From: "Aneesh Kumar K.V"
Although it's optional, IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_emulate.c | 7 +++
1 file c
the guest.
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_asm.h| 18
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kernel/asm-offsets.c | 3 ++
arch/powerpc/kvm/book3s.c
The HTAB is always big endian. We access the guest's HTAB using
copy_from/to_user, but don't yet take care of the fact that we might
be running on an LE host.
Wrap all accesses to the guest HTAB with big endian accessors.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_
With the previous patches applied, we can now successfully use PR KVM on
little endian hosts which means we can now allow users to select it.
However, HV KVM still needs some work, so let's keep the kconfig conflict
on that one.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/Kconfi
ister as a simple write of the IDR register. That automatically
updates all the hidden state as well.
Reported-by: Paul Janzen
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/mpic.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerp
From: "Aneesh Kumar K.V"
Use make_dsisr instead of open coding it. This also have
the added benefit of handling alignment interrupt on additional
instructions.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/disassem
them in LE mode.
With this fixup in place, I can successfully run LE kernels with KVM
PV enabled on PR KVM.
Signed-off-by: Alexander Graf
---
arch/powerpc/kernel/epapr_paravirt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch
From: Paul Mackerras
Commit 3b7834743f9 ("KVM: PPC: Book3S HV: Reserve POWER8 space in
get/set_one_reg") added definitions for several KVM_REG_PPC_* symbols
but missed adding some to api.txt. This adds them.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
Doc
. In kvmppc_hv_get_dirty_log()
we then set that many bits in the dirty map.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
The HTAB on PPC is always in big endian. When we access it via hypercalls
on behalf of the guest and we're running on a little endian host, we need
to make sure we swap the bits accordingly.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_pr_papr.c | 14 +++---
1 file ch
gh it would trip over and break.
So add a new CAP that gives user space a hint that we have workarounds for the
bugs above in place. It can use those as hint to disable PV hypercalls when
the guest CPU is anything POWER7 or higher and the host does not have fixes
in place.
Signed-off-by: Alexander
ster sizes.)
For clarity, this moves KVM_REG_PPC_WORT to the next unused number,
and also adds it to api.txt.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
Documentation/virtual/kvm/api.txt | 1 +
arch/powerpc/include/uapi/asm/kvm.h | 2 +-
2 files changed, 2 insertions(+),
: Alexander Graf
---
arch/powerpc/kvm/powerpc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 3cf541a..a9bd0ff 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -1015,10 +1015,10
ned-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 11 ---
arch/powerpc/kvm/book3s_64_slb.S | 3 ++-
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c
b/arch/powerpc/kvm/book3s_64_mmu_host.c
index e2efb85..0ac9
CR2 before reading
MMCR0.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/reg.h | 12 ---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 59 +++--
2 files changed, 64 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/i
's also make it more readable (get
rid of rldicl), allow it to deal with a dynamic number of bolted
SLB entries and only do shadow SLB swizzling on LPAR systems.
Signed-off-by: Alexander Graf
---
arch/powerpc/kernel/paca.c | 3 ++
arch/powerpc/kvm/book3s_64_slb.S | 83 ++---
Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index f32896f..4e22ecb 100644
--- a/arch/powerpc/kvm
Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 60fe8ba..220aefb 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
the C bit.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 47 +
1 file changed, 37 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c
b/arch/powerpc/kvm/book3s_64_mmu_hv.c
ind
ack to big endian when we return to the guest.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_rtas.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_rtas.c b/arch/powerpc/kvm/book3s_rtas.c
index 7a05315..edb14ba 100644
--- a/arch/p
The default MSR when user space does not define anything should be identical
on little and big endian hosts, so remove MSR_LE from it.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_pr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_pr.c
it may miss out on doing a complete TLB flush, and therefore may end
up using stale TLB entries from a previous guest that used the same
LPID value.
This should make migration more reliable.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 3
The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/e500_emulate.c | 1 +
1
least don't give the guest a
program exception which it definitely does not expect.
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/reg_booke.h | 1 +
arch/powerpc/kvm/e500_emulate.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/arch/powerpc/include/asm/r
On 30.05.14 11:44, Michael Neuling wrote:
>>>
>>> Which header are these coming from, and why aren't we including
it? And is it
>>> going to still build with CONFIG_KVM=n?
>>
>> From include/asm/hvcall.h in the h_set_mode patch set I sent before.
>>
>> And yes it compiles with CONFIG_KVM=n
On 30.05.14 11:10, Michael Neuling wrote:
On Fri, 2014-05-30 at 18:56 +1000, Michael Ellerman wrote:
On Thu, 2014-05-29 at 17:45 +1000, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR
On 29.05.14 23:52, Benjamin Herrenschmidt wrote:
On Thu, 2014-05-29 at 23:27 +0200, Alexander Graf wrote:
On 29.05.14 09:45, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
On 29.05.14 09:45, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
+#define H_SET_MODE_RESOURCE_LE4
Much better, but
Signed-off-by: Kim Phillips
Looks largely identical to the PCI version of the same that has been
accepted for v3.16 and ack'd by GregKH.
Reviewed-by: Alex Williamson
Yup, would be great to have feature parity for device binding on
platform and PCI.
Reviewed-by: Alexander Graf
Alex
> Am 29.05.2014 um 08:22 schrieb Michael Neuling :
>
> This adds support for the H_SET_MODE hcall. This hcall is a
> multiplexer that has several functions, some of which are called
> rarely, and some which are potentially called very frequently.
> Here we add support for the functions that set
> Am 29.05.2014 um 07:27 schrieb Paul Mackerras :
>
>> On Wed, May 28, 2014 at 03:27:32PM +0200, Alexander Graf wrote:
>>
>>> On 26.05.14 14:17, Paul Mackerras wrote:
>>> +6.8 KVM_CAP_PPC_ENABLE_HCALL
>>> +
>>> +Architectures:
's also make it more readable (get
rid of rldicl), allow it to deal with a dynamic number of bolted
SLB entries and only do shadow SLB swizzling on LPAR systems.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- use andis.
- remove superfluous isync/sync
- add KVM warning comments in SLB bo
ned-off-by: Alexander Graf
---
v1 -> v2:
- flush ERAT by writing 0 to slb0
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 11 ---
arch/powerpc/kvm/book3s_64_slb.S | 3 ++-
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c
b/arc
On 17.05.14 07:36, Paul Mackerras wrote:
On Thu, May 15, 2014 at 02:43:53PM +0200, Alexander Graf wrote:
On LPAR guest systems Linux enables the shadow SLB to indicate to the
hypervisor a number of SLB entries that always have to be available.
Today we go through this shadow SLB and disable
On 26.05.14 14:17, Paul Mackerras wrote:
From: Michael Neuling
This adds support for the H_SET_MODE hcall. This hcall is a
multiplexer that has several functions, some of which are called
rarely, and some which are potentially called very frequently.
Here we add support for the functions that
On 26.05.14 14:17, Paul Mackerras wrote:
This adds code to check that when the KVM_CAP_PPC_ENABLE_HCALL
capability is used to enable or disable in-kernel handling of an
hcall, that the hcall is actually implemented by the kernel.
If not an EINVAL error is returned.
Signed-off-by: Paul Mackerras
On 26.05.14 14:17, Paul Mackerras wrote:
This provides a way for userspace controls which PAPR hcalls get
handled in the kernel. Each hcall can be individually enabled or
disabled for in-kernel handling, except for H_RTAS. The exception
for H_RTAS is because userspace can already control wheth
On 26.05.14 11:48, Paul Mackerras wrote:
This series of patches fixes a few bugs that have been found in
testing HV KVM recently. It also adds workarounds for a couple of
POWER8 PMU bugs, fixes the definition of KVM_REG_PPC_WORT, and adds
some things that were missing from Documentation/virtual
On 26.05.14 14:36, Andreas Färber wrote:
Am 26.05.2014 12:31, schrieb Alexander Graf:
On 26.05.14 12:20, Andreas Färber wrote:
Am 26.05.2014 11:57, schrieb Alexander Graf:
Any reason we're so incredibly inconsistent in what we do during realize
with reset? I would really prefer to e
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