On Wed, Dec 23, 2015 at 06:40:12AM +, Gonglei (Arei) wrote:
> > From: Kevin O'Connor [mailto:ke...@koconnor.net]
> > On Tue, Dec 22, 2015 at 02:14:12AM +, Gonglei (Arei) wrote:
> > > Sorry, it doesn't work. What's worse is we cannot stop SeaBIOS s
On Tue, Dec 22, 2015 at 03:15:26AM +, Xulei (Stone) wrote:
> Hi, Kevin,
> Can you tell how to reset/reboot this VM, if it goes to the handle_hwpic1()
> on its booting procedure? I mean, usually, SeaBIOS would not go to
> handle_hwpic routine. But in my test case, SeaBIOS calls handle_hwpic
On Tue, Dec 22, 2015 at 02:14:12AM +, Gonglei (Arei) wrote:
> > From: Kevin O'Connor [mailto:ke...@koconnor.net]
> > Sent: Tuesday, December 22, 2015 2:47 AM
> > To: Gonglei (Arei)
> > Cc: Xulei (Stone); Paolo Bonzini; qemu-devel; seab...@seabios.org;
> > Huangwe
On Mon, Dec 21, 2015 at 09:41:32AM +, Gonglei (Arei) wrote:
> When the gurb of OS is booting, then the softirq and C function send_disk_op()
> may use extra stack of SeaBIOS. If we inject a NMI, romlayout.S:
> irqentry_extrastack
> is invoked, and the extra stack will be used again. And the
On Sun, Dec 20, 2015 at 09:49:54AM +, Gonglei (Arei) wrote:
> > From: Kevin O'Connor [mailto:ke...@koconnor.net]
> > Sent: Saturday, December 19, 2015 11:12 PM
> > On Sat, Dec 19, 2015 at 12:03:15PM +, Gonglei (Arei) wrote:
> > > Maybe the root cause is not N
On Sat, Dec 19, 2015 at 12:03:15PM +, Gonglei (Arei) wrote:
> Maybe the root cause is not NMI but INTR, so yield() can open hardware
> interrupt,
> And then execute interrupt handler, but the interrupt handler make the SeaBIOS
> stack broken, so that the BSP can't execute the instruction and
On Fri, Dec 18, 2015 at 03:04:58AM +, Gonglei (Arei) wrote:
> Hi Kevin & Paolo,
>
> Luckily, I reproduced this problem last night. And I got the below log when
> SeaBIOS is stuck.
[...]
> [2015-12-18 10:38:10] gonglei: finish while
[...]
> <...>-31509 [035] 154753.180077: kvm_exit:
On Mon, May 25, 2015 at 02:52:51PM +0200, Paolo Bonzini wrote:
On 23/05/2015 01:23, Kevin O'Connor wrote:
I'm curious if you've tried profiling SeaBIOS to see where it is
spending unnecessary time?
No, I really wanted to get the absolute minimum time needed to get to
the kernel. I
On Mon, May 25, 2015 at 09:21:49AM +0300, Vasiliy Tolstov wrote:
2015-05-23 6:55 GMT+03:00 Kevin O'Connor ke...@koconnor.net:
Out of curiosity, I ran some additional timing tests. With SeaBIOS
fully stripped down (via Kconfig), it takes ~20ms to get to the boot
phase on my old AMD system
On Fri, May 22, 2015 at 07:23:27PM -0400, Kevin O'Connor wrote:
On Thu, May 21, 2015 at 03:51:43PM +0200, Paolo Bonzini wrote:
Some of you may have heard about the Clear Containers initiative from
Intel, which couple KVM with various kernel tricks to create extremely
lightweight virtual
On Thu, May 21, 2015 at 03:51:43PM +0200, Paolo Bonzini wrote:
Some of you may have heard about the Clear Containers initiative from
Intel, which couple KVM with various kernel tricks to create extremely
lightweight virtual machines. The experimental Clear Containers setup
requires only 18-20
On Thu, Mar 26, 2015 at 08:08:52PM +0300, Andrey Korolyov wrote:
On Thu, Mar 26, 2015 at 8:06 PM, Kevin O'Connor ke...@koconnor.net wrote:
On Thu, Mar 26, 2015 at 07:48:09PM +0300, Andrey Korolyov wrote:
On Thu, Mar 26, 2015 at 7:36 PM, Kevin O'Connor ke...@koconnor.net wrote:
I'm not sure
On Thu, Mar 26, 2015 at 04:58:07PM +0100, Radim Krčmář wrote:
2015-03-25 20:05-0400, Kevin O'Connor:
On Thu, Mar 26, 2015 at 02:35:58AM +0300, Andrey Korolyov wrote:
Thanks, strangely the reboot is always failing now and always reaching
seabios greeting. May be prints straightened up
On Thu, Mar 26, 2015 at 07:48:09PM +0300, Andrey Korolyov wrote:
On Thu, Mar 26, 2015 at 7:36 PM, Kevin O'Connor ke...@koconnor.net wrote:
I'm not sure if the crash always happens at the int $0x19 location
though. Andrey, does the crash always happen with EIP=d331 and/or
with Code=... cd
On Wed, Mar 25, 2015 at 11:43:31PM +0300, Andrey Korolyov wrote:
On Mon, Mar 16, 2015 at 10:17 PM, Andrey Korolyov and...@xdel.ru wrote:
For now, it looks like bug have a mixed Murphy-Heisenberg nature, as
it appearance is very rare (compared to the number of actual launches)
and most
On Thu, Mar 26, 2015 at 01:31:11AM +0300, Andrey Korolyov wrote:
On Wed, Mar 25, 2015 at 11:54 PM, Kevin O'Connor ke...@koconnor.net wrote:
Can you add something like:
-chardev file,path=seabioslog.`date +%s`,id=seabios -device
isa-debugcon,iobase=0x402,chardev=seabios
On Thu, Mar 26, 2015 at 02:35:58AM +0300, Andrey Korolyov wrote:
Thanks, strangely the reboot is always failing now and always reaching
seabios greeting. May be prints straightened up a race (e.g. it is not
int19 problem really).
object file part:
d331 irq_trampoline_0x19:
On Wed, Mar 11, 2015 at 03:53:07PM +, Dr. David Alan Gilbert wrote:
* Kevin O'Connor (ke...@koconnor.net) wrote:
On Wed, Mar 11, 2015 at 01:45:57PM +, Dr. David Alan Gilbert wrote:
* Bandan Das (b...@redhat.com) wrote:
Dr. David Alan Gilbert dgilb...@redhat.com writes:
while
true test.
(The emulation failure I mean, not the suberror 2 that Andrey is seeing)
The commit that seems to have introduced this is -
commit 0673b7870063a3affbad9046fb6d385a4e734c19
Author: Kevin O'Connor ke...@koconnor.net
Date: Sat May 24 10:49:50 2014 -0400
smp: Replace
On Wed, Mar 11, 2015 at 05:59:04PM +, Dr. David Alan Gilbert wrote:
* Kevin O'Connor (ke...@koconnor.net) wrote:
On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote:
* Kevin O'Connor (ke...@koconnor.net) wrote:
So, I couldn't get this to fail on my older AMD
On Wed, Mar 11, 2015 at 02:45:31PM -0400, Kevin O'Connor wrote:
On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
For what it's worth, I can't seem to trigger the problem if I move the
cmos read above the SIPI/LAPIC code (see patch below).
Ugh!
That's a seabios bug. Main
On Wed, Mar 11, 2015 at 04:52:03PM +, Dr. David Alan Gilbert wrote:
* Kevin O'Connor (ke...@koconnor.net) wrote:
So, I couldn't get this to fail on my older AMD machine at all with
the default SeaBIOS code. But, when I change the code with the patch
below, it failed right away
On Wed, Mar 11, 2015 at 01:09:42PM -0400, Bandan Das wrote:
Kevin O'Connor ke...@koconnor.net writes:
...
Something is very odd here. When I run the above command (on an older
AMD machine) I get:
Found 128 cpu(s) max supported 128 cpu(s)
That first value (1 vs 128) comes from QEMU
On Wed, Mar 11, 2015 at 02:40:39PM -0400, Kevin O'Connor wrote:
For what it's worth, I can't seem to trigger the problem if I move the
cmos read above the SIPI/LAPIC code (see patch below).
Ugh!
That's a seabios bug. Main processor modifies the rtc index
(rtc_read()) while APs try to clear
On Mon, Apr 28, 2014 at 03:49:31PM +0200, Gerd Hoffmann wrote:
On Sa, 2014-04-26 at 13:02 +0200, Paolo Bonzini wrote:
Il 26/04/2014 11:40, Paolo Bonzini ha scritto:
Il 25/04/2014 09:39, Gerd Hoffmann ha scritto:
Anyone has plans to add smm support to kvm?
No plans, but it should be
I only recently saw this email.
On Thu, Jun 06, 2013 at 06:10:12PM +0300, Gleb Natapov wrote:
On Thu, Jun 06, 2013 at 05:06:32PM +0200, Gerd Hoffmann wrote:
For seabios itself this isn't a big issue, see pci_{readl,writel} in
src/pci.c. When called in 16bit mode it goes into 32bit mode
On Fri, May 31, 2013 at 07:58:36AM -0500, Anthony Liguori wrote:
Kevin O'Connor ke...@koconnor.net writes:
Given the objections to implementing ACPI directly in QEMU, one
possible way forward would be to split the current SeaBIOS rom into
two roms: qvmloader and seabios. The qvmloader
On Fri, May 31, 2013 at 10:13:34AM +0200, Peter Stuge wrote:
Kevin O'Connor wrote:
one possible way forward would be to split the current SeaBIOS rom
into two roms: qvmloader and seabios. The qvmloader would do
the qemu specific platform init (pci init, smm init, mtrr init, bios
tables
On Tue, May 28, 2013 at 07:53:09PM -0400, Kevin O'Connor wrote:
There were discussions on potentially introducing a middle component
to generate the tables. Coreboot was raised as a possibility, and
David thought it would be okay to use coreboot for both OVMF and
SeaBIOS. The possibility
On Wed, May 29, 2013 at 11:18:03AM -0500, Anthony Liguori wrote:
Gerd Hoffmann kra...@redhat.com writes:
On 05/29/13 01:53, Kevin O'Connor wrote:
Raised
that QOM interface should be sufficient.
Agree on this one. Ideally the acpi table generation code should be
able to gather all
On Thu, May 23, 2013 at 03:41:32PM +0300, Michael S. Tsirkin wrote:
Juan is not available now, and Anthony asked for
agenda to be sent early.
So here comes:
Agenda for the meeting Tue, May 28:
- Generating acpi tables
I didn't see any meeting notes, but I thought it would be worthwhile
On Fri, Mar 15, 2013 at 09:45:14AM +0800, Asias He wrote:
Asias He (2):
virtio-scsi: Set _DRIVER_OK flag before scsi target scanning
virtio-scsi: Pack struct virtio_scsi_{req_cmd,resp_cmd}
Thanks. I pushed these patches.
-Kevin
--
To unsubscribe from this list: send the line unsubscribe
On Fri, Nov 02, 2012 at 01:42:08PM +0800, Xudong Hao wrote:
64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high
memory, top down from the end of guest physical address space.
Your patch seems to be against an old version of SeaBIOS. The latest
SeaBIOS already supports
On Tue, Sep 11, 2012 at 11:15:50AM -0500, Anthony Liguori wrote:
Jan Kiszka jan.kis...@siemens.com writes:
On 2012-09-11 05:02, Kevin O'Connor wrote:
The easiest way to fix this is to change QEMU to boot with the area
read-write. There's no real gain in booting with the memory read-only
On Mon, Sep 10, 2012 at 11:25:38AM +0200, Jan Kiszka wrote:
On 2012-09-09 17:45, Avi Kivity wrote:
On 09/07/2012 11:50 AM, Jan Kiszka wrote:
+} else {
+cpu_physical_memory_rw(run-mmio.phys_addr,
+ run-mmio.data,
+
On Wed, Sep 05, 2012 at 07:28:15AM +0200, Gerd Hoffmann wrote:
This patch makes seabios use the acpi pmtimer instead of tsc for
timekeeping. The pmtimer has a fixed frequency and doesn't need
calibration, thus it doesn't suffer from calibration errors due to a
loaded host machine.
[ v3:
On Tue, Aug 14, 2012 at 07:29:19AM +0200, Gerd Hoffmann wrote:
This patch makes seabios use the acpi pmtimer instead of tsc for
timekeeping. The pmtimer has a fixed frequency and doesn't need
calibration, thus it doesn't suffer from calibration errors due to a
loaded host machine.
The patch
On Sun, Aug 19, 2012 at 06:07:05PM +0300, Avi Kivity wrote:
ipxe contains the following snippet:
/* Copy ROM to image source PMM block */
pushw %es
xorw%ax, %ax
movw%ax, %es
movl%esi, %edi
xorl%esi, %esi
movzbl romheader_size,
On Sun, Aug 19, 2012 at 04:34:50PM +0100, Michael Brown wrote:
On Sunday 19 Aug 2012 16:07:05 Avi Kivity wrote:
(and that seabios needs changes to either work in
big real mode, or to put the processor back into big real mode after
returning from a PMM service.
If seabios switches into
On Mon, Aug 13, 2012 at 03:04:10PM +0200, Gerd Hoffmann wrote:
This patch makes seabios use the acpi pmtimer instead of tsc for
timekeeping. The pmtimer has a fixed frequency and doesn't need
calibration, thus it doesn't suffer from calibration errors due to a
loaded host machine.
It looks
On Thu, Apr 19, 2012 at 04:08:41PM +0200, Vasilis Liaskovitis wrote:
The memory device generation is guided by qemu paravirt info. Seabios
first uses the info to setup SRAT entries for the hotplug-able memory slots.
Afterwards, build_memssdt uses the created SRAT entries to generate
On Tue, Feb 14, 2012 at 04:13:42PM +0400, Cyrill Gorcunov wrote:
On Tue, Feb 14, 2012 at 01:10:59PM +0200, Pekka Enberg wrote:
On Tue, Feb 14, 2012 at 1:03 PM, Yang Bai hamo...@gmail.com wrote:
Since on X86, bios is always at the end of the address space, so I
have some thought about how
On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
To allow guests to load the native SHPC driver
for a bridge, we must declare an OSHP method
for the appropriate device which lets the OS
take control of the SHPC.
As we don't access SHPC at the moment, we
don't need to do
On Tue, Feb 14, 2012 at 02:43:45AM +0200, Michael S. Tsirkin wrote:
On Mon, Feb 13, 2012 at 07:34:55PM -0500, Kevin O'Connor wrote:
On Mon, Feb 13, 2012 at 11:33:08AM +0200, Michael S. Tsirkin wrote:
To allow guests to load the native SHPC driver
for a bridge, we must declare an OSHP
On Thu, Jan 19, 2012 at 03:02:30PM +0100, Vasilis Liaskovitis wrote:
On Fri, Jan 13, 2012 at 07:27:01PM -0500, Kevin O'Connor wrote:
[...]
Method (CPEJ, 2, NotSerialized) {
// _EJ0 method - eject callback
+Store(ShiftLeft(1, Arg0), PRE
On Fri, Jan 13, 2012 at 12:11:30PM +0100, Vasilis Liaskovitis wrote:
Signed-off-by: Vasilis Liaskovitis vasilis.liaskovi...@profitbricks.com
The SeaBIOS change is okay with me, but the qemu/kvm change needs to
be accepted first.
[...]
Method (CPEJ, 2, NotSerialized) {
On Tue, Dec 06, 2011 at 07:32:55PM -0500, Amos Kong wrote:
- Original Message -
On Tue, Dec 06, 2011 at 01:39:35PM +0800, Amos Kong wrote:
Only func 0 is registered to guest driver (we can
only found func 0 in slot-funcs list of driver),
the other functions could not be cleaned
On Mon, Nov 21, 2011 at 10:22:22PM +0200, Michael S. Tsirkin wrote:
On Sun, Nov 20, 2011 at 04:08:59PM -0500, Kevin O'Connor wrote:
On Sun, Nov 20, 2011 at 07:56:43PM +0200, Michael S. Tsirkin wrote:
Here's an updated revision of acpi runtime patching patchset.
Lightly tested
On Sun, Nov 20, 2011 at 07:56:43PM +0200, Michael S. Tsirkin wrote:
Here's an updated revision of acpi runtime patching patchset.
Lightly tested.
It looks good to me.
-Kevin
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to majord...@vger.kernel.org
On Wed, Nov 02, 2011 at 10:54:42AM +0200, Michael S. Tsirkin wrote:
On Tue, Nov 01, 2011 at 06:59:01PM -0400, Kevin O'Connor wrote:
Can we leave these parts in the DSDT and only move the bulk generated
stuff to the SSDT?
They can, but I thought one of the reasons we do the split
On Thu, Nov 03, 2011 at 09:04:57AM +0800, Wen Congyang wrote:
At 11/03/2011 08:30 AM, Kevin O'Connor Write:
I think it's reasonable to require that a user supplied DSDT still
fill certain requirements. Keep in mind that the reason for the user
supplied DSDT was for new platform (q35
On Tue, Nov 01, 2011 at 09:11:40PM +0200, Michael S. Tsirkin wrote:
So here's the plan: move all hotplug handling out
to ssdt, this way it'll keep working even with a
user-supplied dsdt. Next step we can patch
this ssdt at runtime.
There's little point in this change alone, so posting as
On Wed, Oct 26, 2011 at 11:28:02PM +0200, Michael S. Tsirkin wrote:
Add ACPI_EXTRACT_ALL_CODE directive, to support extracting
AML code from listing into a named array. Use that instead including C
file generated by iasl, this makes it possible to include multiple AML
tables without resorting
On Mon, Oct 10, 2011 at 02:06:29PM +0800, Lai Jiangshan wrote:
From: Kenji Kaneshige kaneshige.ke...@jp.fujitsu.com
In the current seabios MP table description, NMI is connected only to
BSP's LINT1. But usually NMI is connected to all the CPUs' LINT1 as
indicated in MP specification. This
On Wed, Oct 26, 2011 at 02:19:00PM +0200, Vasilis Liaskovitis wrote:
qemu-kvm passes numa/SRAT topology information for smp_cpus to SeaBIOS.
However
SeaBIOS always expects to setup max_cpus number of SRAT cpu entries
(MaxCountCPUs variable in build_srat function of Seabios). When qemu-kvm
On Wed, Oct 26, 2011 at 11:28:02PM +0200, Michael S. Tsirkin wrote:
Add ACPI_EXTRACT_ALL_CODE directive, to support extracting
AML code from listing into a named array. Use that instead including C
file generated by iasl, this makes it possible to include multiple AML
tables without resorting
On Tue, Oct 18, 2011 at 02:47:29AM +0900, Isaku Yamahata wrote:
On Wed, Oct 05, 2011 at 10:15:26PM -0400, Kevin O'Connor wrote:
- Some time back there were patches floating around to pass the DSDT
into SeaBIOS via fw_cfg interface. Those patches never made it in
(I forget why
On Tue, Oct 04, 2011 at 03:26:19PM +0200, Michael S. Tsirkin wrote:
Get rid of manually cut and pasted ssdt_proc,
use ssdt compiled by iasl and offsets extracted
by acpi_extract instead.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
FYI - I pushed the ACPI DSDT simplifications series
On Wed, Oct 05, 2011 at 08:35:26AM -0200, Michael S. Tsirkin wrote:
On Tue, Oct 04, 2011 at 10:52:33PM -0400, Kevin O'Connor wrote:
Something like:
ACPI_EXTRACT ssdt_proc_obj
Processor (CPAA, 0xAA, 0xb010, 0x06) {
I considered this, sure. We could parse AML to figure
On Tue, Oct 04, 2011 at 03:26:19PM +0200, Michael S. Tsirkin wrote:
Get rid of manually cut and pasted ssdt_proc,
use ssdt compiled by iasl and offsets extracted
by acpi_extract instead.
Thanks - I like the idea of auto-generating the offsets.
[...]
+#define AmlCode static ssdp_proc_aml
On Mon, Sep 26, 2011 at 10:04:13AM +0300, Michael S. Tsirkin wrote:
On Mon, Sep 26, 2011 at 12:40:18AM -0400, Kevin O'Connor wrote:
On Thu, Sep 22, 2011 at 09:09:49AM +0300, Michael S. Tsirkin wrote:
On Thu, Sep 22, 2011 at 12:35:13AM -0400, Kevin O'Connor wrote:
The code to generate
On Thu, Sep 22, 2011 at 09:09:49AM +0300, Michael S. Tsirkin wrote:
On Thu, Sep 22, 2011 at 12:35:13AM -0400, Kevin O'Connor wrote:
The code to generate basic SSDT code isn't that difficult (see
build_ssdt and src/ssdt-proc.dsl). Is there a compelling reason to
patch the DSDT versus just
On Thu, Sep 22, 2011 at 09:09:49AM +0300, Michael S. Tsirkin wrote:
On Thu, Sep 22, 2011 at 12:35:13AM -0400, Kevin O'Connor wrote:
On Wed, Sep 21, 2011 at 03:44:13PM +0300, Michael S. Tsirkin wrote:
The correct way to suppress hotplug is not to have _EJ0,
so this is what this patch does
On Wed, Sep 21, 2011 at 02:09:08PM +0300, Michael S. Tsirkin wrote:
On Wed, Sep 21, 2011 at 01:39:22AM -0400, Amos Kong wrote:
- Original Message -
How about moving code into functions so that it isn't duplicated for
each PCI device. See the patch below as an example (100%
On Wed, Sep 21, 2011 at 03:44:13PM +0300, Michael S. Tsirkin wrote:
The reason is that our acpi tables declare both _RMV with value 0,
and _EJ0 method for these slots. What happens in this case
is undocumented by ACPI spec, so linux ignores _RMV,
and windows seems to ignore _EJ0.
Could the
On Tue, Sep 20, 2011 at 04:00:57AM -0400, Amos Kong wrote:
From 4678a3cb0e0a3cd7a4bc3d284c5719fdba90bc61 Mon Sep 17 00:00:00 2001
From: Kevin O'Connor ke...@koconnor.net
Date: Tue, 20 Sep 2011 15:43:55 +0800
Subject: [PATCH V2] Fix regression of commit 87b533bf
From: Kevin O'Connor ke
On Tue, Sep 20, 2011 at 06:45:57AM -0400, Amos Kong wrote:
From 48ea1c9188334b89a60b4f9e853e86fc04fda4a5 Mon Sep 17 00:00:00 2001
From: Amos Kong ak...@redhat.com
Date: Tue, 20 Sep 2011 15:38:43 +0800
Subject: [SeaBIOS PATCH v2] hotplug: Add device per func in ACPI DSDT tables
Only func 0
On Wed, Sep 14, 2011 at 07:45:59AM -0400, Amos Kong wrote:
The size of bios.bin compiled from seabios
original: 128K
only apply patch1: 256K
only apply patch2: 128K
patch1: add 6 slot(only slot6 has 8 funcs) to the table
can hotplug/hot-remove a multifunc device to slot 6 successfully
On Sun, Aug 28, 2011 at 10:42:49PM +0200, Jan Kiszka wrote:
On 2011-08-28 20:54, Alexander Graf wrote:
On 28.08.2011, at 02:42, Avi Kivity wrote:
On 08/26/2011 08:32 AM, ya su wrote:
hi,Avi:
I met the same problem, tons of hpet vm_exits(vector 209, fault
address is in the
On Tue, Aug 09, 2011 at 02:32:02PM -0400, John Paul Walters wrote:
I've enabled debugging in seabios (#define DEBUG_BIOS) and get the
output below. Note that with the help of folks in the KVM irc
channel I'm able to start a 254 core instance using the KVM tool, so
the problem seems to be
On Wed, Jun 01, 2011 at 04:40:15PM +0200, Rudolf Marek wrote:
Having a brief look at the coreboot code it seems static stuff (compiled by
iasl) and dynamic bits are combined into the final dsdt table, is that
correct?
Yes the dsdt is static, it has just external references to ssdt
which is
On Wed, Jun 01, 2011 at 11:20:29PM +0900, Isaku Yamahata wrote:
On Wed, Jun 01, 2011 at 09:30:12AM +0200, Gerd Hoffmann wrote:
Hi,
0xE000 is hard-coded in the DSDT for both piix and q35 as below.
If the range is determined dynamically, the area also needs to be
updated somehow
On Tue, Dec 14, 2010 at 12:02:03PM +0200, Avi Kivity wrote:
That could certainly be optimized. If the BAR is all along in its
page, both on guest and host (if not, we can migrate it, at least on
the host), we can use the same offset within the page on the host as
it appears on the guest, and
On Thu, Dec 02, 2010 at 02:30:42PM +0200, Gleb Natapov wrote:
On Wed, Dec 01, 2010 at 09:25:40PM -0500, Kevin O'Connor wrote:
You're thinking in terms of which device to boot, which does make this
difficult. However, it's equally valid to think in terms of which
boot method to invoke
On Wed, Dec 01, 2010 at 02:27:40PM +0200, Gleb Natapov wrote:
On Tue, Nov 30, 2010 at 09:53:32PM -0500, Kevin O'Connor wrote:
BTW, what's the plan for handling SCSI adapters? Lets say a user has
a scsi card with three drives (lun 1, lun 3, lun 5) that show up as 3
bcvs (lun1, lun3, lun5
On Tue, Nov 30, 2010 at 04:01:00PM +0200, Gleb Natapov wrote:
On Mon, Nov 29, 2010 at 08:34:03PM -0500, Kevin O'Connor wrote:
On Sun, Nov 28, 2010 at 08:47:34PM +0200, Gleb Natapov wrote:
If you let go to the idea of exact matching of string built by qemu in
Seabios it will be easy to see
On Sun, Nov 28, 2010 at 08:47:34PM +0200, Gleb Natapov wrote:
On Sun, Nov 28, 2010 at 12:15:44PM -0500, Kevin O'Connor wrote:
It's unclear to me how SeaBIOS is supposed to do that.
Suppose we have /p...@i0cf8/s...@3/d...@0,0 with boot index 5 in
boot devices list and suppose pci device
On Mon, Nov 29, 2010 at 11:50:45AM +0100, Gerd Hoffmann wrote:
If scsi card has optionrom with only one bcv then Seabios can determine
its boot order from device path, so why not provide user with this
option today?
It's unclear to me how SeaBIOS is supposed to do that.
Try to keep track of
On Sun, Nov 28, 2010 at 09:45:34AM +0200, Gleb Natapov wrote:
On Sat, Nov 27, 2010 at 04:07:45PM -0500, Kevin O'Connor wrote:
On Sat, Nov 27, 2010 at 09:04:24PM +0200, Gleb Natapov wrote:
Suppose we add SCSI support to Seabios and suppose SCSI card Seabios can
natively boot from has
On Wed, Nov 24, 2010 at 12:03:11PM +0200, Gleb Natapov wrote:
On Tue, Nov 23, 2010 at 08:19:07PM -0500, Kevin O'Connor wrote:
On Tue, Nov 23, 2010 at 05:31:41PM +0200, Gleb Natapov wrote:
On Wed, Nov 17, 2010 at 06:43:47PM +0200, Gleb Natapov wrote:
I am using open firmware naming scheme
On Sat, Nov 27, 2010 at 06:22:16PM +0200, Gleb Natapov wrote:
On Sat, Nov 27, 2010 at 10:41:10AM -0500, Kevin O'Connor wrote:
On Wed, Nov 24, 2010 at 12:03:11PM +0200, Gleb Natapov wrote:
BEV should be easy. When you register BEV found on pci card you search
for device path to that pci
On Sat, Nov 27, 2010 at 07:06:19PM +0200, Gleb Natapov wrote:
On Sat, Nov 27, 2010 at 11:49:39AM -0500, Kevin O'Connor wrote:
On Sat, Nov 27, 2010 at 06:22:16PM +0200, Gleb Natapov wrote:
Yeah. I looked at the Seabios code. The simplest would be to change
device path to point to rom
On Sat, Nov 27, 2010 at 08:15:42PM +0200, Gleb Natapov wrote:
On Sat, Nov 27, 2010 at 12:47:26PM -0500, Kevin O'Connor wrote:
I don't think seabios should try to parse the path. Instead, I think
seabios should build a name for each device it finds using the same
algorithm that qemu uses
Trimming CC list, adding seabios list.
On Sat, Nov 27, 2010 at 09:04:24PM +0200, Gleb Natapov wrote:
On Sat, Nov 27, 2010 at 01:40:12PM -0500, Kevin O'Connor wrote:
On Sat, Nov 27, 2010 at 08:15:42PM +0200, Gleb Natapov wrote:
Qemu does not know that Seabios needs optionrom to boot from
Hi Gleb,
On Tue, Nov 23, 2010 at 05:31:41PM +0200, Gleb Natapov wrote:
Anthony, Blue
No comments on this patch series for almost a week. Can it be applied?
My apologies - I haven't had time to review.
On Wed, Nov 17, 2010 at 06:43:47PM +0200, Gleb Natapov wrote:
I am using open firmware
On Tue, Nov 16, 2010 at 09:22:45AM +0200, Gleb Natapov wrote:
On Mon, Nov 15, 2010 at 09:52:19PM -0500, Kevin O'Connor wrote:
I also have an ulterior motive here. If the boot order is exposed as
a newline separated list via an entry in QEMU_CFG_FILE_DIR, then this
becomes free for coreboot
On Mon, Nov 15, 2010 at 09:40:08AM +0200, Gleb Natapov wrote:
On Sun, Nov 14, 2010 at 10:40:33PM -0500, Kevin O'Connor wrote:
Why not just return a newline separated list that is null terminated?
Doing it like this will needlessly complicate firmware side. How do you
know how much memory
On Mon, Nov 15, 2010 at 06:09:45PM +0200, Avi Kivity wrote:
On 11/15/2010 05:49 PM, Avi Kivity wrote:
On 11/15/2010 05:41 PM, Avi Kivity wrote:
I think it's a miscompile.
out/code16.o:
1a4: 3e ds
1a5: 6c insb (%dx),%es:(%edi)
Note no
On Mon, Nov 15, 2010 at 03:36:25PM +0200, Gleb Natapov wrote:
On Mon, Nov 15, 2010 at 08:26:35AM -0500, Kevin O'Connor wrote:
On Mon, Nov 15, 2010 at 09:40:08AM +0200, Gleb Natapov wrote:
On Sun, Nov 14, 2010 at 10:40:33PM -0500, Kevin O'Connor wrote:
Why not just return a newline
On Sun, Nov 14, 2010 at 05:39:41PM +0200, Gleb Natapov wrote:
+/*
+ * This function returns device list as an array in a below format:
+ * +-+-+---+-+---+--
+ * | n | l1 | devpath1| l2 | devpath2 | ...
+ *
On Sun, Oct 31, 2010 at 01:40:01PM +0200, Gleb Natapov wrote:
This is current sate of the patch series for people to comment on.
I tried to use open firmware naming scheme to specify device path names.
The patch series produce names like these:
for pci machine:
On Wed, Oct 27, 2010 at 03:27:58PM +0200, Avi Kivity wrote:
On the last kvm conf call Anthony said that he'll be happy to
include an updated seabios with qemu 0.13.1, so a new release would
be appreciated.
I branched and tagged rel-0.6.1.1. It only has 6d5a2172
cherry-picked into it.
-Kevin
On Thu, Oct 21, 2010 at 12:07:17PM +0200, Avi Kivity wrote:
How do we manage the stable series wrt this issue?
qemu-kvm-0.12.5 has a regression within the stable series that this
patch fixes. qemu 0.12.5 does not, but only because it does not
emulate polarity in the I/O APIC correctly.
On Tue, Oct 12, 2010 at 08:49:58AM +0200, Avi Kivity wrote:
On 10/11/2010 07:53 PM, Ruben Kerkhof wrote:
5c99b6c984682ddb1d4543a7e27a1f4ca633e6a6 is the first bad commit
commit 5c99b6c984682ddb1d4543a7e27a1f4ca633e6a6
Author: Kevin O'Connorke...@koconnor.net
Gleb, Kevin, any ideas?
On Tue, Sep 21, 2010 at 04:06:01PM -0300, Marcelo Tosatti wrote:
On Tue, Sep 21, 2010 at 02:31:42PM +0200, Gleb Natapov wrote:
Without this BIOS fails to remap 0xf memory from ROM to RAM so writes
to F-segment modify ROM content instead of memory copy. Since QEMU does
not reloads ROMs
On Mon, Sep 20, 2010 at 08:50:17AM +0200, Gleb Natapov wrote:
On Sun, Sep 19, 2010 at 06:03:31PM -0400, Kevin O'Connor wrote:
I was wrong. The cpu_set x offline does send an event to the guest
OS. SeaBIOS even forwards the event along - as far as I can tell a
Notify(CPxx, 3) event
On Sun, Sep 19, 2010 at 08:38:12AM +0200, Gleb Natapov wrote:
On Sat, Sep 18, 2010 at 08:27:54PM +0200, Conrad Wood wrote:
hm... after upgrading to seabios 0.6.1 and qemu-kvm 0.13.50 (git today)
I get:
[...]
any ideas ?
Known problem in qemu. There was a patch for this, but qemu
On Sun, Sep 19, 2010 at 03:29:35PM +0200, Conrad Wood wrote:
On Sun, 2010-09-19 at 09:26 -0400, Kevin O'Connor wrote:
On Sun, Sep 19, 2010 at 08:38:12AM +0200, Gleb Natapov wrote:
Known problem in qemu. There was a patch for this, but qemu maintainers
think it is not good enough.
Old
On Sun, Sep 19, 2010 at 03:40:45PM +0200, Gleb Natapov wrote:
halted state is not the way to check for whether cpu is online or
offline. cpu may be online but executing hlt instruction so
its state will be halted, but cpu itself is online. Actually with kvm
today you are not able to check
On Sun, Sep 19, 2010 at 04:07:50PM +0200, Conrad Wood wrote:
1) Thanks for clarifying online vs halted - that makes sense and is
probably part of what confused me. I need to get the online/offline
status of cpus, not if they are halted or not. I understand this is
currently not possible with
1 - 100 of 158 matches
Mail list logo
