-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 31, 2014 8:18 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-...@vger.kernel.org; kvm@vger.kernel.org; Yoder Stuart-
B08248
Subject: Re: [PATCH 6/6] KVM: PPC: BOOKE: Emulate debug registers and
exception
On
We have
- wait (wait bit in PSW)
- disabled wait (wait bit and interrupt fencing in PSW)
- STOPPED (not related to PSW, state change usually handled via service
processor or hypervisor)
I think we have to differentiate between KVM/TCG. On KVM we always do in
kernel halt and qemu
From: David Hildenbrand d...@linux.vnet.ibm.com
A VCPU might never stop if it intercepts (for whatever reason) between
fake interrupt delivery and execution of the stop function.
Heart of the problem is that SIGP STOP is an interrupt that has to be
processed on every SIE entry until the VCPU
commit 7dfc63cf977447e09b1072911c22564f900fc578
(KVM: s390: allow only one SIGP STOP (AND STORE STATUS) at a time)
introduced a memory leak if a sigp stop is already pending. Free
the allocated inti structure.
Signed-off-by: Christian Borntraeger borntrae...@de.ibm.com
Reviewed-by: David
Hi Paolo,
On Wed, Jul 30, 2014 at 05:20:58PM +0200, Paolo Bonzini wrote:
Il 30/07/2014 14:04, Wanpeng Li ha scritto:
@@ -7962,14 +7965,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu,
struct vmcs12 *vmcs12)
if (!vmx-rdtscp_enabled)
exec_control =
Paolo,
The following changes since commit b55a8144d1807f9e74c51cb584f0dd198483d86c:
x86/kvm: Resolve shadow warning from min macro (2014-07-25 16:05:54 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
tags/kvm-s390-20140730
We handle FSCR feature bits (well, TAR only really today) lazily when the guest
starts using them. So when a guest activates the bit and later uses that feature
we enable it for real in hardware.
However, when the guest stops using that bit we don't stop setting it in
hardware. That means we can
Il 31/07/2014 10:03, Wanpeng Li ha scritto:
One thing:
+ if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
+ vmcs_write32(TPR_THRESHOLD, vmcs12-tpr_threshold);
I think you can just do this write unconditionally, since most
hypervisors will enable this. Also, you probably can
Fixes pvclock backwards jumps caused by TSC drifting despite
host believing that TSC is invariant/synchronized.
TSC drift maybe caused by erratum 778 described in
Revision Guide for AMD Family 15h Models 10h-1Fh Processors,
Publication # 48931, Issue Date: May 2013, Revision: 3.10
Igor
Signed-off-by: Igor Mammedov imamm...@redhat.com
---
arch/x86/kvm/cpuid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 38a0afe..f519823 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -478,8 +478,9 @@
Due to erratum #778 from
Revision Guide for AMD Family 15h Models 10h-1Fh Processors,
Publication # 48931, Issue Date: May 2013, Revision: 3.10
TSC on affected processor, a core may drift under certain conditions,
which makes initially synchronized TSCs to become unsynchronized.
As result TSC
For lots of exits the min time (and sometimes max) is 0 or 1. Lets
increase the accurancy similar to what the average field alread does.
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Jiri Olsa jo...@kernel.org
Cc: David Ahern dsah...@gmail.com
Cc: Arnaldo Carvalho de Melo a...@kernel.org
On my s390 kvm system most of the kvm exits are in the range
of 0 or 1 microseconds. Can we increase the accuracy by 2
additional digits?
Opinions?
Christian Borntraeger (1):
KVM: perf/stat: Properly show submicrosecond times
tools/perf/builtin-kvm.c | 8
1 file changed, 4
On Wed, Jul 30, 2014 at 03:58:43PM -0700, Zetan Drableg wrote:
[00183ms] /usr/libexec/qemu-kvm \
-global virtio-blk-pci.scsi=off \
-nodefconfig \
-nodefaults \
-nographic \
-machine accel=kvm:tcg \
-cpu host,+kvmclock \
-m 500 \
Resubmitting the patch in: http://marc.info/?l=kvmm=140594903520308w=2
after fixing the whitespaces issues.
Thank you,
Razya
From f293e470b36ff9eb4910540c620315c418e4a8fc Mon Sep 17 00:00:00 2001
From: Razya Ladelsky ra...@il.ibm.com
Date: Thu, 31 Jul 2014 09:47:20 +0300
Subject: [PATCH]
Il 30/07/2014 23:19, Mark D Rustad ha scritto:
Resolve shadow warnings that appear in W=2 builds. Instead of
using ret to hold the return pointer, save the length in a new
variable saved_len and compute the pointer on exit. This also
resolves a very technical error, in that ret was declared as
Il 30/07/2014 23:18, Mark D Rustad ha scritto:
Resolve some missing-initializers warnings that appear in W=2
builds. They are resolved by adding the name as a parameter to
the macros and having the macro generate all four fields of the
structure.
Signed-off-by: Mark Rustad
Il 24/07/2014 06:57, Andy Lutomirski ha scritto:
This adds a simple interface to allow a guest to request 64 bits of
host nonblocking entropy. This is independent of virtio-rng for a
couple of reasons:
- It's intended to be usable during early boot, when a trivial
synchronous interface
Il 24/07/2014 06:57, Andy Lutomirski ha scritto:
This is a straightforward implementation: for each bit of internal
RNG state, request one bit from KVM_GET_RNG_SEED. This is done even
if RDSEED/RDRAND worked, since KVM_GET_RNG_SEED is likely to provide
cryptographically secure output even if
Il 24/07/2014 06:57, Andy Lutomirski ha scritto:
It's considerably better than any of the alternatives on KVM.
Rather than reinventing all of the cpu feature query code, this fixes
native_cpuid to work in PIC objects.
I haven't combined it with boot/cpuflags.c's cpuid implementation:
On Tue, Jul 01, 2014 at 03:45:15PM +0100, Will Deacon wrote:
kvm_ioctl_create_device currently has knowledge of all the device types
and their associated ops. This is fairly inflexible when adding support
for new in-kernel device emulations, so move what we currently have out
into a table,
On Tue, Jul 01, 2014 at 03:45:16PM +0100, Will Deacon wrote:
Now that we have a dynamic means to register kvm_device_ops, use that
for the ARM VGIC, instead of relying on the static table.
Cc: Gleb Natapov g...@kernel.org
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Marc Zyngier
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the occurences used by KVM as the code wasn't
merged yet.
Just fix the accessors.
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas
On Thu, Jul 31, 2014 at 02:16:39PM +0100, Marc Zyngier wrote:
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the occurences used by KVM as the code wasn't
merged yet.
Just fix the
Hi Christoffer,
On Thu, Jul 31, 2014 at 01:10:15PM +0100, Christoffer Dall wrote:
On Tue, Jul 01, 2014 at 03:45:16PM +0100, Will Deacon wrote:
Now that we have a dynamic means to register kvm_device_ops, use that
for the ARM VGIC, instead of relying on the static table.
Cc: Gleb Natapov
On Thu, Jul 31, 2014 at 02:19:47PM +0100, Will Deacon wrote:
On Thu, Jul 31, 2014 at 02:16:39PM +0100, Marc Zyngier wrote:
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the
On 7/31/14, 5:13 AM, Christian Borntraeger wrote:
For lots of exits the min time (and sometimes max) is 0 or 1. Lets
increase the accurancy similar to what the average field alread does.
Seems reasonable to me.
Acked-by: David Ahern dsah...@gmail.com
Cc: Paolo Bonzini pbonz...@redhat.com
Il 31/07/2014 09:59, Christian Borntraeger ha scritto:
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
tags/kvm-s390-20140730
Thanks, applying.
Paolo
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More
On Wed, Jul 09, 2014 at 02:55:12PM +0100, Alex Bennée wrote:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused if
the CPU starts running after migration restore completes when it was
paused before it state
Il 31/07/2014 11:47, Igor Mammedov ha scritto:
Signed-off-by: Igor Mammedov imamm...@redhat.com
---
arch/x86/kvm/cpuid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 38a0afe..f519823 100644
---
Em Thu, Jul 31, 2014 at 08:24:03AM -0600, David Ahern escreveu:
On 7/31/14, 5:13 AM, Christian Borntraeger wrote:
For lots of exits the min time (and sometimes max) is 0 or 1. Lets
increase the accurancy similar to what the average field alread does.
Seems reasonable to me.
Acked-by:
Christoffer Dall writes:
On Wed, Jul 09, 2014 at 02:55:12PM +0100, Alex Bennée wrote:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused if
the CPU starts running after migration restore completes when it
On Thu, Jul 31, 2014 at 09:47:12AM +, Igor Mammedov wrote:
Due to erratum #778 from
Revision Guide for AMD Family 15h Models 10h-1Fh Processors,
Publication # 48931, Issue Date: May 2013, Revision: 3.10
TSC on affected processor, a core may drift under certain conditions,
which makes
On Thu, Jul 31, 2014 at 02:32:27PM +0100, Christoffer Dall wrote:
On Thu, Jul 31, 2014 at 02:19:47PM +0100, Will Deacon wrote:
On Thu, Jul 31, 2014 at 02:16:39PM +0100, Marc Zyngier wrote:
Commit 72c583951526 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we
On Thu, Jul 31, 2014 at 05:05:58PM +0100, Will Deacon wrote:
On Thu, Jul 31, 2014 at 02:32:27PM +0100, Christoffer Dall wrote:
On Thu, Jul 31, 2014 at 02:19:47PM +0100, Will Deacon wrote:
On Thu, Jul 31, 2014 at 02:16:39PM +0100, Marc Zyngier wrote:
Commit 72c583951526 (arm64: gicv3:
Il 31/07/2014 17:47, Borislav Petkov ha scritto:
On Thu, Jul 31, 2014 at 09:47:12AM +, Igor Mammedov wrote:
Due to erratum #778 from
Revision Guide for AMD Family 15h Models 10h-1Fh Processors,
Publication # 48931, Issue Date: May 2013, Revision: 3.10
TSC on affected processor, a core
On Jul 31, 2014, at 4:50 AM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 30/07/2014 23:18, Mark D Rustad ha scritto:
Resolve some missing-initializers warnings that appear in W=2
builds. They are resolved by adding the name as a parameter to
the macros and having the macro generate all four
On Thu, Jul 31, 2014 at 04:14:51PM +0100, Alex Bennée wrote:
Christoffer Dall writes:
On Wed, Jul 09, 2014 at 02:55:12PM +0100, Alex Bennée wrote:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused if
On 31 July 2014 17:38, Christoffer Dall christoffer.d...@linaro.org wrote:
If we are not complaining when setting the pause value to false if it
was true before, then we probably also need to wake up the thread in
case this is called from another thread, right?
or perhaps we should just
On Thu, Jul 31, 2014 at 05:45:28PM +0100, Peter Maydell wrote:
On 31 July 2014 17:38, Christoffer Dall christoffer.d...@linaro.org wrote:
If we are not complaining when setting the pause value to false if it
was true before, then we probably also need to wake up the thread in
case this
On 31 July 2014 17:50, Christoffer Dall christoffer.d...@linaro.org wrote:
On Thu, Jul 31, 2014 at 05:45:28PM +0100, Peter Maydell wrote:
Consider the case where the reset state of the system is
CPU 0 running, CPUs 1..N stopped, and we're doing an
incoming migration to a state where all CPUs
Il 31/07/2014 18:35, Rustad, Mark D ha scritto:
I agree it is ugly. .name = NULL would be enough to silence it. Would
that be better? At the moment I am thinking of this as a test case
for the other 1000 { } and {0} initializers in the kernel that are
throwing warnings. I know we both agree
Il 09/07/2014 15:55, Alex Bennée ha scritto:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused if
the CPU starts running after migration restore completes when it was
paused before it state was captured.
On 31 July 2014 17:57, Paolo Bonzini pbonz...@redhat.com wrote:
Il 09/07/2014 15:55, Alex Bennée ha scritto:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused if
the CPU starts running after migration
Resolve shadow warnings that appear in W=2 builds. Instead of
using ret to hold the return pointer, save the length in a new
variable saved_len and compute the pointer on exit. This also
resolves a very technical error, in that ret was declared as
a const char *, when it really was a char * const,
Il 31/07/2014 19:04, Peter Maydell ha scritto:
On 31 July 2014 17:57, Paolo Bonzini pbonz...@redhat.com wrote:
Il 09/07/2014 15:55, Alex Bennée ha scritto:
To cleanly restore an SMP VM we need to ensure that the current pause
state of each vcpu is correctly recorded. Things could get confused
On 31 July 2014 18:21, Paolo Bonzini pbonz...@redhat.com wrote:
What does ARM do if you have a WFI while interrupts are disabled? On
x86 after cli;hlt only an NMI will wake you up. With spurious
wakeups, it's pretty much guaranteed that you will break such cli;hlt
sequences.
The
On Thu, Jul 31, 2014 at 06:36:35PM +0100, Peter Maydell wrote:
On 31 July 2014 18:21, Paolo Bonzini pbonz...@redhat.com wrote:
What does ARM do if you have a WFI while interrupts are disabled? On
x86 after cli;hlt only an NMI will wake you up. With spurious
wakeups, it's pretty much
cc'ing the kvm mailing list that was mistakenly omitted.
On 7/30/14 9:57 AM, Nadav Amit wrote:
Task-switch emulation checks the privilage level prior to performing the
task-switch. This check is incorrect in the case of task-gates, in which the
tss.dpl is ignored, and can cause superfluous
cc'ing the kvm mailing list that was mistakenly omitted.
On 7/30/14 10:03 AM, Nadav Amit wrote:
Local-apic enables cluster mode broadcast. As Intel SDM 10.6.2.2 says:
Broadcast to all local APICs is achieved by setting all destination bits to
one. This patch enables cluster mode broadcast.
Jan Kiszka jan.kiszka at siemens.com writes:
On 2014-07-28 23:17, Nakajima, Jun wrote:
On Mon, Jul 28, 2014 at 1:27 PM, Paolo Bonzini pbonzini at
redhat.com wrote:
Il 28/07/2014 20:31, Jan Kiszka ha scritto:
The hypervisor has full control of and insight into the guest vCPU
state.
Hi Richard thanks for the info.
I took the strace approach and ran into this looping over and over again.
Is it failing to get time?
timer_gettime(0x8, {it_interval={0, 0}, it_value={0, 0}}) = 0
timer_settime(0x8, 0, {it_interval={0, 0}, it_value={0, 25}}, NULL) = 0
timer_gettime(0x8,
On Thu, Jul 31, 2014 at 12:12:26PM -0700, Zetan Drableg wrote:
Hi Richard thanks for the info.
I took the strace approach and ran into this looping over and over again.
Is it failing to get time?
timer_gettime(0x8, {it_interval={0, 0}, it_value={0, 0}}) = 0
timer_settime(0x8, 0,
I recently ran into a situation where I needed more than 16 stream ids
for an smmu on an AMD SOC, but we are currently limited to 16 by:
#define MAX_MASTER_STREAMIDSMAX_PHANDLE_ARGS
#define MAX_PHANDLE_ARGS 16
I expect others will run into this in the future as more advanced SOCs
start
On Thu, 2014-07-31 at 01:15 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 31, 2014 8:18 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-...@vger.kernel.org; kvm@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
Hello,
I am exploring ideas to implement a service inside a virtual machine on
untrusted hypervisors under current cloud infrastructures.
Particularly, I am interested how one can verify the integrity of the
service in an environment where hypervisor is not trusted. This is my setup.
1. I
On Thu, Jul 31, 2014 at 2:25 PM, Shiva V shivaramakrishnan...@gmail.com wrote:
Hello,
I am exploring ideas to implement a service inside a virtual machine on
untrusted hypervisors under current cloud infrastructures.
Particularly, I am interested how one can verify the integrity of the
Nakajima, Jun jun.nakajima at intel.com writes:
On Thu, Jul 31, 2014 at 2:25 PM, Shiva V shivaramakrishnan740 at
gmail.com wrote:
Hello,
I am exploring ideas to implement a service inside a virtual machine on
untrusted hypervisors under current cloud infrastructures.
Particularly, I am
Paolo Bonzini wrote on 2014-07-31:
Il 31/07/2014 10:03, Wanpeng Li ha scritto:
One thing:
+ if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
+ vmcs_write32(TPR_THRESHOLD, vmcs12-tpr_threshold);
I think you can just do this write unconditionally, since most
hypervisors will
Thanks,MST! :-)
I will change the order back and have a test again.
On 2014/7/31 22:37, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 04:31:00PM +0200, Michael S. Tsirkin wrote:
On Thu, Jul 31, 2014 at 07:47:24PM +0800, Zhangjie (HZ) wrote:
[The test scenario]:
Doing migration between
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 31, 2014 8:18 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re: [PATCH 6/6] KVM: PPC: BOOKE: Emulate debug registers and
exception
We handle FSCR feature bits (well, TAR only really today) lazily when the guest
starts using them. So when a guest activates the bit and later uses that feature
we enable it for real in hardware.
However, when the guest stops using that bit we don't stop setting it in
hardware. That means we can
On Thu, 2014-07-31 at 01:15 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, July 31, 2014 8:18 AM
To: Bhushan Bharat-R65777
Cc: ag...@suse.de; kvm-ppc@vger.kernel.org; k...@vger.kernel.org; Yoder
Stuart-
B08248
Subject: Re:
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software
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