Re: [PATCH] KVM: disable halt_poll_ns as default for s390x

Am 18.09.2015 um 13:29 schrieb Paolo Bonzini: > > > On 18/09/2015 12:54, Christian Borntraeger wrote: >>> -/* halt polling only reduces halt latency by 5-7 us, 500us is enough */ >>> -static unsigned int halt_poll_ns = 50; >>> +/* Architectures should define their poll value according to the

RE: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

Hello Andre and others! How are things going? I see the last message in thread something like 1 month old, then silence... Our project relies on this feature, any assistance needed? Kind regards, Pavel Fedin Expert Engineer Samsung Electronics Research center Russia -- To unsubscribe from

Re: [PATCH] KVM: x86: fix bogus warning about reserved bits

On Thu, Sep 24, 2015 at 11:23:08AM +0800, Xiao Guangrong wrote: > >+static inline bool > >+boot_cpu_is_amd(void) > >+{ > >+WARN_ON_ONCE(!tdp_enabled); > >+return shadow_x_mask != 0; > > shadow_x_mask != 0 is Intel's CPU. > > Borislav, could you please check shadow_x_mask == 0 instead and

RE: [PATCH 1/3] arm/arm64: KVM: vgic: Check for !irqchip_in_kernel() when mapping resources

Hello! > Until b26e5fdac43c ("arm/arm64: KVM: introduce per-VM ops"), > kvm_vgic_map_resources() used to include a check on irqchip_in_kernel(), > and vgic_v2_map_resources() still has it. I'm back from vacation and very glad to see myself being useful :) What's with the rest of that patch

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

On Thu, 2015-09-24 at 12:55 +0300, Michael S. Tsirkin wrote: > > I'm fine with this patch > > Acked-by: Michael S. Tsirkin Thanks. In fact Dave has already merged it. > but if you want to re-work it along the lines suggested > by Greg, that's also fine with me. If I'm going

[PATCH kvm-unit-tests] x86: Test watchpoints during emulation

From: Rami Burstein& Anrey Isakov This adds a test for data and port watchpoints during instruction emulation. Signed-off-by: Rami Burstein Signed-off-by: Andrey Isakov --- This unit tests are based on old kvm-unit-tests version

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

On Thu, Sep 24, 2015 at 09:25:45AM +0200, Greg Kurz wrote: > On Wed, 23 Sep 2015 19:45:08 +0100 > David Woodhouse wrote: > > > Commit 7d82410950aa ("virtio: add explicit big-endian support to memory > > accessors") accidentally changed the virtio_net header used by > >

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

On Wed, Sep 23, 2015 at 07:45:08PM +0100, David Woodhouse wrote: > Commit 7d82410950aa ("virtio: add explicit big-endian support to memory > accessors") accidentally changed the virtio_net header used by > AF_PACKET with PACKET_VNET_HDR from host-endian to big-endian. > > Since

Re: [PATCH 2/2] KVM: x86: Guest watchpoints during emulation.

Looking at the patch again, there two points you may want to change, see inline. If you want, I’ll send a v2. Nadav Nadav Amit wrote: > From: Nadav Amit > > This adds support for guest data and I/O breakpoints during instruction > emulation. >

Re: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

Hi Pavel, On 24/09/15 12:18, Pavel Fedin wrote: > Hello Andre and others! > > How are things going? I see the last message in thread something like 1 > month old, then silence... > Our project relies on this feature, any assistance needed? I am about to make it work on top of Christoffer's

[PATCH 2/2] KVM: x86: Guest watchpoints during emulation.

From: Nadav Amit This adds support for guest data and I/O breakpoints during instruction emulation. Watchpoints are examined during data and io interceptions: segmented_read, segmented_write, em_in, em_out, segmented_read_std and kvm_fast_pio_out. When such a breakpoint

[PATCH 1/2] KVM: x86: Add DR flag definition for IO watchpoints

From: Rami Burstein Add DR_RW_PROT for I/O watchponts. Signed-off-by: Andrey Isakov Signed-off-by: Rami Burstein Signed-off-by: Nadav Amit --- arch/x86/include/uapi/asm/debugreg.h | 1 + 1 file changed, 1

[PATCH 0/2] KVM: x86: Emulated I/O and data breakpoints support

This patch-set adds data and I/O breakpoints support on emulated instructions to KVM. The first patch just adds a missing definition and all the logic is in the second one. These patches were implemented as part of a university project, and then cleaned and rebased on the latest KVM by me. I have

[PATCH] KVM: nVMX: expose VPID capability to L1

Expose VPID capability to L1. Signed-off-by: Wanpeng Li --- arch/x86/kvm/vmx.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index f9219ad..866045c 100644 --- a/arch/x86/kvm/vmx.c +++

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

On Wed, 23 Sep 2015 19:45:08 +0100 David Woodhouse wrote: > Commit 7d82410950aa ("virtio: add explicit big-endian support to memory > accessors") accidentally changed the virtio_net header used by > AF_PACKET with PACKET_VNET_HDR from host-endian to big-endian. > Hi David,

Re: Migration fail randomly

On 2015-09-16 08:45, Sander Klein wrote: On 2015-09-15 15:38, Paolo Bonzini wrote: On 15/09/2015 15:36, Sander Klein wrote: On 2015-09-15 15:24, Paolo Bonzini wrote: What kernel runs in the host? The host is the standard Debian Jessie kernel, 3.16.7-ckt11-1+deb8u3. Please try a more

RE: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

Hello! > The only thing that is pure 64-bit is the MRS/MSR _instruction_ in > Aarch64, which always takes a x register. > So can you model the register size according to the spec and allow > 32-bit accesses from userland? I would like to complete the rework and respin v4, but this is, i guess,

[RFC PATCH v3] os-android: Add support to android platform

Hi, The v3 patch fix ident error and add error checking on ptsname_r() function. This patch is based on version: 007e620a7576e4ce2ea6955541e87d8ae8ed32ae. --- Building QEMU on android reqiures android NDK r10 cross-compilation

Re: [PATCH 1/1] target-i386: get/put MSR_TSC_AUX across reset and migration

On Wed, Sep 23, 2015 at 09:47:43AM +0200, Paolo Bonzini wrote: > > > On 23/09/2015 08:27, Amit Shah wrote: > > There's one report of migration breaking due to missing MSR_TSC_AUX > > save/restore. Fix this by adding a new subsection that saves the state > > of this MSR. > > > >

[PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

The function can return negative value. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107 Signed-off-by: Andrzej Hajda --- Hi, To avoid

Re: [PATCH 1/1] target-i386: get/put MSR_TSC_AUX across reset and migration

On Wed, Sep 23, 2015 at 11:57:33AM +0530, Amit Shah wrote: > There's one report of migration breaking due to missing MSR_TSC_AUX > save/restore. Fix this by adding a new subsection that saves the state > of this MSR. > > https://bugzilla.redhat.com/show_bug.cgi?id=1261797 > > Reported-by:

Re: [PATCH] KVM: nVMX: emulate the INVVPID instruction

Paolo Bonzini writes: ... >> @@ -7189,7 +7189,28 @@ static int handle_invept(struct kvm_vcpu *vcpu) >> >> static int handle_invvpid(struct kvm_vcpu *vcpu) >> { >> -kvm_queue_exception(vcpu, UD_VECTOR); >> +u32 vmx_instruction_info; >> +unsigned long type; >> +

Re: [PATCH 1/2] KVM: introduce __vmx_flush_tlb to handle specific vpid

Wanpeng Li writes: > Introduce __vmx_flush_tlb() to handle specific vpid. > > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/vmx.c | 21 + > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/arch/x86/kvm/vmx.c

[PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu

Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for each vcpu. According to ARMv8 spec, the PMU

[PATCH v3 00/20] KVM: ARM64: Add guest PMU support

This patchset adds guest PMU support for KVM on ARM64. It takes trap-and-emulate approach. When guest wants to monitor one event, it will be trapped by KVM and KVM will call perf_event API to create a perf event and call relevant perf_event APIs to get the count value of event. Use perf to test

[PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h

To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/pmu.h | 45

[PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in KVM, directly use raw event type to create a

[PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register

Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate reading to PMCCNTR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 17 +++-- 1 file changed, 15 insertions(+), 2

[PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 29 + 1 file changed, 25 insertions(+), 4

[PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register

The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shannon Zhao ---

[PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMOVSSET or PMOVSCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 33 ++--- 1 file

[PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR, call

[PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

Add reset handler which gets host value of PMCR_EL0 and make writable bits architecturally UNKNOWN. Add a common access handler for PMU registers which emulates writing and reading register and add emulation for PMCR. Signed-off-by: Shannon Zhao ---

[PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers

We are about to trap and emulate acccesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers and their AArch32 counterparts. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_asm.h | 59

[PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. As it doesn't need to deal with the acsessing action specially, it uses default case to emulate writing and reading PMSELR register. Add a helper for CP15 registers reset to UNKNOWN. Signed-off-by: Shannon

[PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao

[PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for the selected event

[PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++

[PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device

Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 15 + arch/arm64/include/uapi/asm/kvm.h | 3 + include/linux/kvm_host.h

[PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c

[PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24 insertions(+) diff --git a/arch/arm/kvm/arm.c

[PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

Add access handler which emulates writing and reading PMEVCNTRn and PMEVTYPERn. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 164 ++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c

[PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing

When calling perf_event_create_kernel_counter to create perf_event, assign a overflow handler. Then when perf event overflows, set irq_pending and call kvm_vcpu_kick() to sync the interrupt. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 4

[PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 18 ++ 3 files changed, 23 insertions(+) diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 91cf535..4da7f6c 100644

Re: [PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

On Thu, 2015-09-24 at 16:00 +0200, Andrzej Hajda wrote: > The function can return negative value. > > The problem has been detected using proposed semantic patch > scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. > > [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107 > >

RE: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including prerequisite series

Hi Paolo, Thanks for your review on this series! I'd like to confirm this series (plus the patch fixing the compilation error) is okay to you and I don't need to do extra things for it, right? Thanks, Feng > -Original Message- > From: Wu, Feng > Sent: Friday, September 18, 2015 10:30 PM

Re: [PATCH 1/2] KVM: introduce __vmx_flush_tlb to handle specific vpid

On 9/25/15 12:12 AM, Bandan Das wrote: Wanpeng Li writes: Introduce __vmx_flush_tlb() to handle specific vpid. Signed-off-by: Wanpeng Li --- arch/x86/kvm/vmx.c | 21 + 1 file changed, 13 insertions(+), 8 deletions(-)

[PATCH] KVM: PPC: e500: Emulate TMCFG0 TMRN register

Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. Signed-off-by: Mihai Caraman [laurentiu.tu...@freescale.com: rebased on latest kernel, use define instead of hardcoded value] Signed-off-by: Laurentiu Tudor --- Needs this

[PATCH] KVM: PPC: e6500: support powers of 2K TLB1 sizes

Book-E MMUv2 present in e6500 cores supports powers of 2K page sizes while older MMUv1 cores support only powers of 4K page sizes, or in other words the LSB of TSIZE on MMUv1 is always 0. Thus, on MMUv2 we must not strip the LSB. Signed-off-by: Mihai Caraman

[PATCH 2/2] KVM: PPC: e6500: TLB emulation for IND entries

Handle indirect entries (IND) in TLB emulation code. Translation size of IND entries differs from the size of referred Page Tables (Linux guests now use IND of 2MB for 4KB PTs) and this requires careful tweaking of the existing logic. TLB search emulation requires additional search in HW TLB0

[PATCH 0/2] KVM Book3E support for Hardware Page Tablewalk enabled guests

This is a revival of LRAT & HWPTW support that Mike submitted some time ago [1]. Patches are rebased and (most [2]) feedback addressed. Also, fixed some issues i noticed plus some cleanup. [1] https://patchwork.ozlabs.org/patch/366892/ https://patchwork.ozlabs.org/patch/366895/

[PATCH 1/2] KVM: PPC: e6500: Handle LRAT error exception

Handle LRAT error exception with support for lrat mapping and invalidation. Signed-off-by: Mihai Caraman [laurentiu.tu...@freescale.com: addressed review feedback, refactoring, cleanup & other fixes] Signed-off-by: Laurentiu Tudor ---

[PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

The function can return negative value. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107 Signed-off-by: Andrzej Hajda --- Hi, To avoid

Re: [PATCH] KVM: PPC: e6500: support powers of 2K TLB1 sizes

On Thu, 2015-09-24 at 15:57 +0300, Laurentiu Tudor wrote: > Book-E MMUv2 present in e6500 cores supports > powers of 2K page sizes while older MMUv1 cores > support only powers of 4K page sizes, or in other > words the LSB of TSIZE on MMUv1 is always 0. > Thus, on MMUv2 we must not strip the LSB.

Re: [PATCH] KVM: PPC: e500: Emulate TMCFG0 TMRN register

On Thu, 2015-09-24 at 09:56 +0300, Laurentiu Tudor wrote: > Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. > > Signed-off-by: Mihai Caraman > [laurentiu.tu...@freescale.com: rebased on latest kernel, > use define instead of hardcoded value] >

Re: [PATCH] powerpc/e6500: add TMCFG0 register definition

On Wed, 2015-09-23 at 18:06 +0300, Laurentiu Tudor wrote: > The register is not currently used in the base kernel > but will be in a forthcoming kvm patch. > > Signed-off-by: Laurentiu Tudor > --- > arch/powerpc/include/asm/reg_booke.h | 6 ++ > 1 file

Re: [PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

On Thu, 2015-09-24 at 16:00 +0200, Andrzej Hajda wrote: > The function can return negative value. > > The problem has been detected using proposed semantic patch > scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. > > [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107 > >

Re: [PATCH 1/2] KVM: PPC: e6500: Handle LRAT error exception

On Thu, 2015-09-24 at 16:11 +0300, Laurentiu Tudor wrote: > diff --git a/arch/powerpc/kvm/bookehv_interrupts.S > b/arch/powerpc/kvm/bookehv_interrupts.S > index 81bd8a07..1e9fa2a 100644 > --- a/arch/powerpc/kvm/bookehv_interrupts.S > +++ b/arch/powerpc/kvm/bookehv_interrupts.S > @@ -62,6 +62,7 @@