[PATCH] VSOCK: mark virtio_transport.ko experimental

Be explicit that the virtio_transport.ko code implements a draft virtio specification that is still subject to change. Signed-off-by: Stefan Hajnoczi --- If you'd rather wait until the device specification has been finalized, feel free to revert the virtio-vsock code for

Re: [PATCH v2 0/5] Add virtio transport for AF_VSOCK

On Wed, Dec 02, 2015 at 02:43:58PM +0800, Stefan Hajnoczi wrote: > v2: > * Rebased onto Linux v4.4-rc2 > * vhost: Refuse to assign reserved CIDs > * vhost: Refuse guest CID if already in use > * vhost: Only accept correctly addressed packets (no spoofing!) > * vhost: Support flexible rx/tx

Re: [RFC PATCH V2 00/10] Qemu: Add live migration support for SRIOV NIC

On 12/2/2015 10:31 PM, Michael S. Tsirkin wrote: >We hope >to find a better way to make SRIOV NIC work in these cases and this is >worth to do since SRIOV NIC provides better network performance compared >with PV NIC. If this is a performance optimization as the above implies, you need to

RE: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

Hello! > > > Cc: sta...@vger.kernel.org > > > Fixes: e6fab5442345 ("ARM/arm64: KVM: test properly for a PTE's > > > uncachedness") > > > > > > > That commit is not in a release yet, so no need for cc stable > [...] > > But it is cc'd to stable, so unless it is going to be nacked at review >

Re: [PATCH 1/3] KVM: arm64: Correctly handle zero register during MMIO

On 03/12/15 09:58, Pavel Fedin wrote: > On ARM64 register index of 31 corresponds to both zero register and SP. > However, all memory access instructions, use ZR as transfer register. SP > is used only as a base register in indirect memory addressing, or by > register-register arithmetics, which

Re: [PATCH 0/3] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On 03/12/15 10:53, Pavel Fedin wrote: > Hello! > >>> The problem has been discovered by performing an operation >>> >>> *((volatile int *)reg) = 0; >>> >>> which compiles as "str xzr, [xx]", and resulted in strange values being >>> written. >> >> Interesting find. Which compiler is that? > > $

RE: [PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

Hello! > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 87a64e8..a667228 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -102,7 +102,7 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, > > > > BUG_ON(!p->is_write); > > >

Re: [PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

On 03/12/15 11:08, Pavel Fedin wrote: > Hello! > >>> diff --git a/arch/arm64/kvm/sys_regs.c >>> b/arch/arm64/kvm/sys_regs.c index 87a64e8..a667228 100644 --- >>> a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ >>> -102,7 +102,7 @@ static bool access_vm_reg(struct kvm_vcpu >>>

RE: [PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

Hello! > > It's simply more convenient to use a pointer for exchange with > > userspace, see vgic_v3_cpu_regs_access() and callers. I wouldn't like > > to refactor the code again. What's your opinion on this? > > I still don't think this is a good idea. You can still store the value > as an

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

On 3 December 2015 at 08:14, Pavel Fedin wrote: > Hello! > >> > diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c >> > index 7dace90..51ad98f 100644 >> > --- a/arch/arm/kvm/mmu.c >> > +++ b/arch/arm/kvm/mmu.c >> > @@ -310,7 +310,8 @@ static void stage2_flush_ptes(struct

Re: [PATCH v2 10/21] arm64: KVM: Add patchable function selector

On Wed, 2 Dec 2015 16:34:56 -0600 Andrew Jones wrote: > On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote: > > KVM so far relies on code patching, and is likely to use it more > > in the future. The main issue is that our alternative system works > > at the

Re: [RFC PATCH V2 09/10] Qemu/VFIO: Add SRIOV VF migration support

On 12/3/2015 6:25 AM, Alex Williamson wrote: On Tue, 2015-11-24 at 21:35 +0800, Lan Tianyu wrote: This patch is to add SRIOV VF migration support. Create new device type "vfio-sriov" and add faked PCI migration capability to the type device. The purpose of the new capability 1) sync

Re: [RFC PATCH V2 06/10] Qemu/PCI: Add macros for faked PCI migration capability

On 12/3/2015 6:25 AM, Alex Williamson wrote: This will of course break if the PCI SIG defines that capability index. Couldn't this be done within a vendor defined capability? Thanks, Yes, it should work and thanks for suggestion. -- To unsubscribe from this list: send the line "unsubscribe

RE: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

Hello! > >> I think your analysis is correct, but does that not apply to both > >> instances? > > > > No no, another one is correct, since it operates on real PFN (at least > > looks like so). I > have verified my fix against the original problem (crash on Exynos5410 > without generic

[PATCH 0/3] KVM: arm64: BUG FIX: Correctly handle zero register transfers

ARM64 CPU has zero register which is read-only, with a value of 0. However, KVM currently incorrectly recognizes it being SP (because Rt == 31, and in struct user_pt_regs 'regs' array is followed by SP), resulting in invalid value being read, or even SP corruption on write. The problem has been

[PATCH 1/3] KVM: arm64: Correctly handle zero register during MMIO

On ARM64 register index of 31 corresponds to both zero register and SP. However, all memory access instructions, use ZR as transfer register. SP is used only as a base register in indirect memory addressing, or by register-register arithmetics, which cannot be trapped here. Correct emulation is

[PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

System register accesses also use zero register for Rt == 31, and therefore using it will also result in getting SP value instead. This patch makes them also using new accessors, introduced by the previous patch. Additionally, got rid of "massive hack" in kvm_handle_cp_64(). Signed-off-by: Pavel

[PATCH 3/3] KVM: arm64: Get rid of old vcpu_reg()

Using oldstyle vcpu_reg() accessor is proven to be inapproptiate and unsafe on ARM64. This patch fixes the rest of use cases and completely removes vcpu_reg() on ARM64. Signed-off-by: Pavel Fedin --- arch/arm/kvm/psci.c | 20 ++--

RE: [PATCH 0/3] KVM: arm64: BUG FIX: Correctly handle zero register transfers

Hello! > > The problem has been discovered by performing an operation > > > > *((volatile int *)reg) = 0; > > > > which compiles as "str xzr, [xx]", and resulted in strange values being > > written. > > Interesting find. Which compiler is that? $ aarch64-linux-gnu-gcc --version

Re: [RFC PATCH V2 02/10] Qemu/VFIO: Add new VFIO_GET_PCI_CAP_INFO ioctl cmd definition

On 12/3/2015 6:25 AM, Alex Williamson wrote: I didn't seen a matching kernel patch series for this, but why is the kernel more capable of doing this than userspace is already? The following link is the kernel patch. http://marc.info/?l=kvm=144837328920989=2 These seem like pointless ioctls,

Re: [PATCH 0/3] KVM: arm64: BUG FIX: Correctly handle zero register transfers

On 03/12/15 09:58, Pavel Fedin wrote: > ARM64 CPU has zero register which is read-only, with a value of 0. > However, KVM currently incorrectly recognizes it being SP (because > Rt == 31, and in struct user_pt_regs 'regs' array is followed by SP), > resulting in invalid value being read, or even

Re: [PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

Pavel, On 03/12/15 09:58, Pavel Fedin wrote: > System register accesses also use zero register for Rt == 31, and > therefore using it will also result in getting SP value instead. This > patch makes them also using new accessors, introduced by the previous > patch. > > Additionally, got rid of

RE: [PATCH v2 0/3] Introduce MSI hardware mapping for VFIO

Hello! > I like that you're making this transparent > for the user, but at the same time, directly calling function pointers > through the msi_domain_ops is quite ugly. Do you mean dereferencing info->ops->vfio_map() in .c code? I can introduce some wrappers in include/linux/msi.h like

Re: [RFC PATCH V2 00/10] Qemu: Add live migration support for SRIOV NIC

On 12/2/2015 10:31 PM, Michael S. Tsirkin wrote: >We hope >to find a better way to make SRIOV NIC work in these cases and this is >worth to do since SRIOV NIC provides better network performance compared >with PV NIC. If this is a performance optimization as the above implies, you need to

Re: [PATCH v2 0/3] Introduce MSI hardware mapping for VFIO

On Thu, 3 Dec 2015 16:16:54 +0300 Pavel Fedin wrote: Pavel, > Hello! > > > I like that you're making this transparent > > for the user, but at the same time, directly calling function pointers > > through the msi_domain_ops is quite ugly. > > Do you mean dereferencing

Re: [PATCH 2/3] KVM: arm64: Correctly handle zero register in system register accesses

On 03/12/15 11:55, Pavel Fedin wrote: > Hello! > >>> It's simply more convenient to use a pointer for exchange with >>> userspace, see vgic_v3_cpu_regs_access() and callers. I wouldn't like >>> to refactor the code again. What's your opinion on this? >> >> I still don't think this is a good

Re: [PATCH] KVM: VMX: fix the writing POSTED_INTR_NV

On 03/12/2015 06:29, roy.qing...@gmail.com wrote: > From: Li RongQing > > POSTED_INTR_NV is 16bit, should not use 64bit write function > > [ 5311.676074] vmwrite error: reg 3 value 0 (err 12) > [ 5311.680001] CPU: 49 PID: 4240 Comm: qemu-system-i38 Tainted: G I >

[PATCH 0/1] virtio/s390: one fix

Michael, here's one fix for the virtio-ccw driver. Patch is against master, as your git branches on mst/vhost.git seem to be quite old. Is there some branch I can base my own branch on, or do you prefer to take patches directly anyway? Cornelia Huck (1): virtio/s390: handle error values in

[PATCH 1/1] virtio/s390: handle error values in irb

The common I/O layer may pass an error value as the irb in the device's interrupt handler (for classic channel I/O). This won't happen in current virtio-ccw implementations, but it's better to be safe than sorry. Let's just return the error conveyed by the irb and clear any possible pending I/O

Re: [PATCH v2 0/3] Introduce MSI hardware mapping for VFIO

On Thu, 2015-12-03 at 16:16 +0300, Pavel Fedin wrote: > Hello! > > > I like that you're making this transparent > > for the user, but at the same time, directly calling function pointers > > through the msi_domain_ops is quite ugly. > > Do you mean dereferencing info->ops->vfio_map() in .c

[PATCH] KVM: VMX: fix read/write sizes of VMCS fields

In theory this should have broken EPT on 32-bit kernels (due to reading the high part of natural-width field GUEST_CR3). Not sure if no one noticed or the processor behaves differently from the documentation. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 8

[PATCH] KVM: VMX: fix read/write sizes of VMCS fields in dump_vmcs

This was not printing the high parts of several 64-bit fields on 32-bit kernels. Separate from the previous one to make the patches easier to review. Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 39 --- 1 file changed, 20

Re: [PATCH v4 1/3] KVM/arm/arm64: add hooks for armv7 fp/simd lazy switch support

On 14/11/15 22:12, Mario Smarduch wrote: > This patch adds vcpu fields to track lazy state, save host FPEXC, and > offsets to fields. > > Signed-off-by: Mario Smarduch > --- > arch/arm/include/asm/kvm_host.h | 6 ++ > arch/arm/kernel/asm-offsets.c | 2 ++ > 2 files

Re: [PATCH v4 2/3] KVM/arm/arm64: enable enhanced armv7 fp/simd lazy switch

On 14/11/15 22:12, Mario Smarduch wrote: > This patch tracks armv7 fp/simd hardware state with a vcpu lazy flag. > On vcpu_load saves host fpexc and enables FP access, and later enables fp/simd > trapping if lazy flag is not set. On first fp/simd access trap to handler > to save host and restore

Re: [RFC PATCH V2 02/10] Qemu/VFIO: Add new VFIO_GET_PCI_CAP_INFO ioctl cmd definition

On Thu, 2015-12-03 at 16:40 +0800, Lan, Tianyu wrote: > On 12/3/2015 6:25 AM, Alex Williamson wrote: > > I didn't seen a matching kernel patch series for this, but why is the > > kernel more capable of doing this than userspace is already? > The following link is the kernel patch. >

Re: [PATCH v4 3/3] KVM/arm/arm64: enable enhanced armv8 fp/simd lazy switch

On 14/11/15 22:12, Mario Smarduch wrote: > This patch tracks armv7 and armv8 fp/simd hardware state with a vcpu lazy > flag. > On vcpu_load for 32 bit guests enable FP access, and later enable fp/simd > trapping for 32 and 64 bit guests if lazy flag is not set. On first fp/simd > access trap to

[PATCH] KVM: vmx: detect mismatched size in VMCS read/write

Signed-off-by: Paolo Bonzini --- I am sending this as RFC because the error messages it produces are very ugly. Because of inlining, the original line is lost. The alternative is to change vmcs_read/write/checkXX into macros, but then you

Re: [PATCH v2 0/5] Add virtio transport for AF_VSOCK

From: Stefan Hajnoczi Date: Wed, 2 Dec 2015 14:43:58 +0800 > This patch series adds a virtio transport for AF_VSOCK (net/vmw_vsock/). Series applied, thanks. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to

Re: [PATCH v4 1/3] KVM/arm/arm64: add hooks for armv7 fp/simd lazy switch support

On 12/3/2015 7:46 AM, Marc Zyngier wrote: > On 14/11/15 22:12, Mario Smarduch wrote: >> This patch adds vcpu fields to track lazy state, save host FPEXC, and >> offsets to fields. >> >> Signed-off-by: Mario Smarduch >> --- >> arch/arm/include/asm/kvm_host.h | 6 ++

Re: [PATCH v4 1/3] KVM/arm/arm64: add hooks for armv7 fp/simd lazy switch support

On 03/12/15 19:21, Mario Smarduch wrote: > > > On 12/3/2015 7:46 AM, Marc Zyngier wrote: >> On 14/11/15 22:12, Mario Smarduch wrote: >>> This patch adds vcpu fields to track lazy state, save host FPEXC, and >>> offsets to fields. >>> >>> Signed-off-by: Mario Smarduch >>>

Re: [PATCH 0/5] Threaded MSI interrupt for VFIO PCI device

On Thu, Dec 03, 2015 at 11:55:53AM -0700, Alex Williamson wrote: > On Thu, 2015-12-03 at 10:22 -0800, Yunhong Jiang wrote: > > When assigning a VFIO device to a KVM guest with low latency requirement, > > it > > is better to handle the interrupt in the hard interrupt context, to reduce > > the

Re: [PATCH 0/5] Threaded MSI interrupt for VFIO PCI device

On Thu, 2015-12-03 at 10:22 -0800, Yunhong Jiang wrote: > When assigning a VFIO device to a KVM guest with low latency requirement, it > is better to handle the interrupt in the hard interrupt context, to reduce > the context switch to/from the IRQ thread. > > Based on discussion on

Re: [PATCH v4 1/3] KVM/arm/arm64: add hooks for armv7 fp/simd lazy switch support

On 12/3/2015 11:24 AM, Marc Zyngier wrote: > On 03/12/15 19:21, Mario Smarduch wrote: >> >> >> On 12/3/2015 7:46 AM, Marc Zyngier wrote: >>> On 14/11/15 22:12, Mario Smarduch wrote: This patch adds vcpu fields to track lazy state, save host FPEXC, and offsets to fields.

Re: [PATCH] KVM: VMX: fix the writing POSTED_INTR_NV

On Thu, Dec 3, 2015 at 9:58 PM, Paolo Bonzini wrote: > Indeed this is a problem for 32-bit hosts. I meet this error when I run a 32bit kernel on Intel Wildcat Pass platform -Roy -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to

Re: [PATCH 4/5] KVM: Add the irq handling consumer

[if your patch is applied to the wrong git tree, please drop us a note to help improving the system] Hi Yunhong, [auto build test ERROR on kvm/linux-next] [also build test ERROR on v4.4-rc3 next-20151202] url:

[PATCH 5/5] KVM: Expose x86 kvm_arch_set_irq_inatomic()

The x86 support setting irq in atomic, expose it to vfio driver. Signed-off-by: Yunhong Jiang --- arch/x86/kvm/Kconfig | 1 + include/linux/kvm_host.h | 19 --- virt/kvm/Kconfig | 3 +++ virt/kvm/eventfd.c | 9 - 4

[PATCH 2/5] VIRT: Support runtime irq_bypass consumer

Extend the irq_bypass manager to support runtime consumers. A runtime irq_bypass consumer can handle interrupt when an interrupt triggered. A runtime consumer has it's handle_irq() function set and passing a irq_context for the irq handling. A producer keep a link for the runtime consumers, so

[PATCH 1/5] KVM: Extract the irqfd_wakeup_pollin/irqfd_wakeup_pollup

Separate the irqfd_wakeup_pollin/irqfd_wakeup_pollup from the irqfd_wakeup, so that we can reuse the logic for MSI fastpath injection. Signed-off-by: Yunhong Jiang --- virt/kvm/eventfd.c | 86 -- 1 file changed,

[PATCH 3/5] VFIO: Support threaded interrupt handling on VFIO

For VFIO device with MSI interrupt type, it's possible to handle the interrupt on hard interrupt context without invoking the interrupt thread. Handling the interrupt on hard interrupt context reduce the interrupt latency. Signed-off-by: Yunhong Jiang ---

Re: [RFC PATCH V2 00/10] Qemu: Add live migration support for SRIOV NIC

On Wed, Dec 2, 2015 at 6:08 AM, Lan, Tianyu wrote: > On 12/1/2015 11:02 PM, Michael S. Tsirkin wrote: >>> >>> But >>> it requires guest OS to do specific configurations inside and rely on >>> bonding driver which blocks it work on Windows. >>> From performance side, >>>

[PATCH 0/5] Threaded MSI interrupt for VFIO PCI device

When assigning a VFIO device to a KVM guest with low latency requirement, it is better to handle the interrupt in the hard interrupt context, to reduce the context switch to/from the IRQ thread. Based on discussion on https://lkml.org/lkml/2015/10/26/764, the VFIO msi interrupt is changed to

[PATCH 4/5] KVM: Add the irq handling consumer

Add an irq_bypass consumer to the KVM eventfd, so that when a MSI interrupt happens and triggerred from VFIO, it can be handled fast. Signed-off-by: Yunhong Jiang --- include/linux/kvm_irqfd.h | 1 + virt/kvm/eventfd.c| 42

Re: [PATCH v4 3/3] KVM/arm/arm64: enable enhanced armv8 fp/simd lazy switch

On 12/3/2015 8:13 AM, Marc Zyngier wrote: > On 14/11/15 22:12, Mario Smarduch wrote: >> This patch tracks armv7 and armv8 fp/simd hardware state with a vcpu lazy >> flag. >> On vcpu_load for 32 bit guests enable FP access, and later enable fp/simd >> trapping for 32 and 64 bit guests if lazy

Re: [PATCH] KVM: VMX: fix the writing POSTED_INTR_NV

On 2015/12/3 13:29, roy.qing...@gmail.com wrote: From: Li RongQing POSTED_INTR_NV is 16bit, should not use 64bit write function [ 5311.676074] vmwrite error: reg 3 value 0 (err 12) [ 5311.680001] CPU: 49 PID: 4240 Comm: qemu-system-i38 Tainted: G I

Re: [PATCH v4 2/3] KVM/arm/arm64: enable enhanced armv7 fp/simd lazy switch

On 12/3/2015 7:58 AM, Marc Zyngier wrote: > On 14/11/15 22:12, Mario Smarduch wrote: >> This patch tracks armv7 fp/simd hardware state with a vcpu lazy flag. >> On vcpu_load saves host fpexc and enables FP access, and later enables >> fp/simd >> trapping if lazy flag is not set. On first

Re: [PATCH] KVM: arm/arm64: Revert to old way of checking for device mapping in stage2_flush_ptes().

On Wed, 2015-12-02 at 18:41 +0100, Ard Biesheuvel wrote: > Hi Pavel, > > Thanks for getting to the bottom of this. > > On 1 December 2015 at 14:03, Pavel Fedin wrote: > > This function takes stage-II physical addresses (A.K.A. IPA), on input, not > > real physical

Re: [PATCH] KVM: VMX: fix read/write sizes of VMCS fields

On 2015/12/3 23:11, Paolo Bonzini wrote: In theory this should have broken EPT on 32-bit kernels (due to reading the high part of natural-width field GUEST_CR3). Not sure if no one noticed or the processor behaves differently from the documentation. It seems we will check the success of

Re: [PATCH net-next 3/3] vhost_net: basic polling support

On 12/02/2015 08:36 PM, Michael S. Tsirkin wrote: > On Wed, Dec 02, 2015 at 01:04:03PM +0800, Jason Wang wrote: >> >> On 12/01/2015 10:43 PM, Michael S. Tsirkin wrote: >>> On Tue, Dec 01, 2015 at 01:17:49PM +0800, Jason Wang wrote: On 11/30/2015 06:44 PM, Michael S. Tsirkin wrote: > On