[PATCH] KVM: allow bit 10 to be cleared in MSR_IA32_MC4_CTL

to the quirk and ignore this single cleared bit. This fixes -cpu kvm64 on all machines and -cpu host on K8 machines with some guest Linux kernels. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff

Re: KVM warning about uncertified CPU for SMP for AMD model 2, stepping 3

advantages, but denies migration mostly). BTW.: I encourage people to test their KVM guests with -cpu host (on newer QEMUs) and send me any crash logs. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe

Re: KVM warning about uncertified CPU for SMP for AMD model 2, stepping 3

Jiri Kosina wrote: On Wed, 31 Mar 2010, Andre Przywara wrote: BTW.: I encourage people to test their KVM guests with -cpu host (on newer QEMUs) and send me any crash logs. I just quickly checked ... snip [0.147235] [c0528a80] init_amd+0x249/0x279 [0.148011] [c0527d74

Re: Setting nx bit in virtual CPU

, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 cpuid_mb Description: Binary data

Re: Setting nx bit in virtual CPU

Richard Simpson wrote: On 08/04/10 09:52, Andre Przywara wrote: Can you try to boot the attached multiboot kernel, which just outputs a brief CPUID dump? $ qemu-kvm -kernel cpuid_mb -vnc :0 (Unfortunately I have no serial console support in there yet, so you either have to write the values

[PATCH] [qemu-kvm/stable] fix CPUID vendor override

the meaning of vendor_override is actually the opposite of how it is currently used :-( This fix reverts the workaround 4dad7ff3 and replaces it with the correct version. Fix it to allow KVM to export the non-native CPUID vendor if explicitly requested by the user. Signed-off-by: Andre Przywara

[PATCH] [qemu-kvm] fix CPUID vendor override

the meaning of vendor_override is actually the opposite of how it is currently used :-( This fix reverts the workaround 4dad7ff3 and replaces it with the correct version. Fix it to allow KVM to export the non-native CPUID vendor if explicitly requested by the user. Signed-off-by: Andre Przywara

[PATCH] svm: implement NEXTRIPsave SVM feature

special, handcrafted code to trigger (no compiler will ever generate such code), I omit a fix for older CPUs. If someone is interested, I have both a patch for these CPUs as well as demo code triggering this issue: It segfaults under KVM, but runs perfectly on native Linux. Signed-off-by: Andre

Re: [PATCH] svm: implement NEXTRIPsave SVM feature

line anyway, so the concerns you rose did not apply to the original version of the patch. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: [PATCH] svm: implement NEXTRIPsave SVM feature

Alexander Graf wrote: On 11.04.2010, at 23:51, Andre Przywara wrote: Alexander Graf wrote: On 11.04.2010, at 23:40, Alexander Graf wrote: /* Either adds offset n to the instruction counter or takes the next instruction pointer from the vmcb if the CPU supports it */ static u64

Re: AW: Kvm migration problem

. -Ursprüngliche Nachricht- Von: Andre Przywara [mailto:andre.przyw...@amd.com] Gesendet: Mi 14.04.2010 11:17 An: Wagner, Kai Cc: kvm@vger.kernel.org Betreff: Re: Kvm migration problem Wagner, Kai wrote: Hey, im from germany and new in kvm. I'll tried the how-to's from your page

Re: Booting/installing WindowsNT

Michael, can you try -cpu kvm64? This should be somewhat in between -cpu host and -cpu qemu64. Also look in dmesg for uncatched rd/wrmsrs. In case you find something there, please try: # modprobe kvm ignore_msrs=1 (You have to unload the modules first) Regards, Andre. -- Andre Przywara AMD

Re: Booting/installing WindowsNT

Avi Kivity wrote: On 05/03/2010 11:24 AM, Andre Przywara wrote: can you try -cpu kvm64? This should be somewhat in between -cpu host and -cpu qemu64. Also look in dmesg for uncatched rd/wrmsrs. In case you find something there, please try: # modprobe kvm ignore_msrs=1 (You have to unload

Re: Booting/installing WindowsNT

the monitor, but also without going into) I could proceed with the installation. Michael, can you confirm this? I will now try to get behind the STOP 3E error. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from

Re: Booting/installing WindowsNT

Avi Kivity wrote: On 05/04/2010 06:27 PM, Andre Przywara wrote: 3. In all other cases so far it BSoDs with STOP 0x3E error right before displaying that kernel message. MSDN talks about a mulitprocessor configuration error: http://msdn.microsoft.com/en-us/library/ms819006.aspx I suspected

Re: Booting/installing WindowsNT

Avi Kivity wrote: On 05/05/2010 11:32 AM, Andre Przywara wrote: Avi Kivity wrote: On 05/04/2010 06:27 PM, Andre Przywara wrote: 3. In all other cases so far it BSoDs with STOP 0x3E error right before displaying that kernel message. MSDN talks about a mulitprocessor configuration error

Re: Booting/installing WindowsNT

Michael Tokarev wrote: 05.05.2010 12:32, Andre Przywara wrote: Avi Kivity wrote: On 05/04/2010 06:27 PM, Andre Przywara wrote: 3. In all other cases so far it BSoDs with STOP 0x3E error right before displaying that kernel message. MSDN talks about a mulitprocessor configuration error: http

Re: [PATCH 4/5] KVM: SVM: Allow EFER.LMSLE to be set with nested svm

not svm specific (it's useful for running non-hvm Xen in non-nested mode). Isn't there a cpuid bit for it? If so, it should be exposed to userspace, and the feature should depend on it. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line

Re: [Qemu-devel] [RFC] Bug Day - June 1st, 2010

Michael Tokarev wrote: 20.05.2010 02:30, Anthony Liguori wrote: On 05/19/2010 05:29 PM, Andre Przywara wrote: Michael Tokarev wrote: ... Also, thanks to Andre Przywara, whole winNT thing works but it requires -cpu qemu64,level=1 (or level=2 or =3), -- _not_ with default CPU. This [] It'd

Re: unhandled wrmsr

darkstar 2.6.35-rc1 #35 SMP Mon May 31 16:50:15 CST 2010 x86_64 Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz GenuineIntel GNU/Linux host distribution is slackware64-13.0 0.12.3 works well BTW the guest is a tiny core linux image -- Andre Przywara AMD-Operating System Research Center (OSRC

Re: unhandled wrmsr

Dave Young wrote: On Wed, Jun 2, 2010 at 8:45 PM, Andre Przywara andre.przyw...@amd.com wrote: Dave Young wrote: Hi, With today's git version (qemu-kvm), I got following message in kernel dmesg [168344.215605] kvm: 27289: cpu0 unhandled wrmsr: 0x198 data 0 Are you sure about that? Sure

Re: Opteron AMD-V support

of KVM. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org

Re: Live migration between Intel Q6600 and AMD Phenom II

based on this single feature is not very legitimate. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b

[PATCH] x86 CPUID extended family/model

qemu64,family=16,model=4,stepping=2 Attached patch introduces support for specifying those bits on the command line and passing them to the guest. (Patch applies against qemu-svn and kvm-userspace) Signed-off-by: Andre Przywara [EMAIL PROTECTED] Regards, Andre. P.S. I heard of a way to propagate

[PATCH 0/3] KVM-userspace: add NUMA support for guests

SRAT ACPI table Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109

[PATCH 1/3] KVM-userspace: introduce -nodes command line option

The attached patch parses a list of host nodes given on the command line and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy

[PATCH 2/3] KVM-userspace: allocate guest resources from different host nodes

actually faults in). Since libnuma is not that widespread (in default installations), I chose 'enable via configure' by now: --enable-numa will compile the parts in. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel

[PATCH 3/3] KVM-userspace: generate a SRAT table to describe the guests NUMA topology

-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany Register Court

Re: [PATCH 0/3] KVM-userspace: add NUMA support for guests

Avi Kivity wrote: Andre Przywara wrote: The user (or better: management application) specifies the host nodes the guest should use: -nodes 2,3 would create a two node guest mapped to node 2 and 3 on the host. These numbers are handed over to libnuma: VCPUs are pinned to the nodes

[PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

, a possible command line looks like: -numa 3,mem:1024M;512M;512M,cpu:0-1;2;3 Please note that you have to quote the semicolons on the shell. The monitor command is left out for now and will be send later. Please apply. Regards, Andre. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre

[PATCH 1/3] v2: KVM-userspace: introduce -numa command line option

The attached patch parses the command line options given at -numa and passes it on to lower levels (namely qemu-kvm.c) Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European

[PATCH 2/3] v2: KVM-userspace: allocate guest resources from different host nodes

actually faults in). The presence of libnuma will be auto-detected. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability

[PATCH 3/3] v2: KVM-userspace: generate a SRAT table to describe the guests NUMA topology

. Signed-off-by: Andre Przywara [EMAIL PROTECTED] -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany

Re: [PATCH 0/3] v2: KVM-userspace: add NUMA support for guests

of the first three if needed. Sounds like a plan. I will start with this and hope for some advice on the BOCHS BIOS issue. Thanks for your ideas! Regards, Andre. Andre Przywara wrote: Hi, this patch series introduces multiple NUMA nodes support within KVM guests. This is the second try

[PATCH] kvm-userspace: Fix a compiler warning

The following small patch fixes a compiler warning in KVM's vl.c Signed-off-by: Andre Przywara [EMAIL PROTECTED] --- diff --git a/qemu/vl.c b/qemu/vl.c index 7b58605..b489acd 100644 --- a/qemu/vl.c +++ b/qemu/vl.c @@ -4611,7 +4611,7 @@ static int gethugepagesize(void) { int ret, fd

Re: [PATCH] CPUID Masking MSRs

almost everything you probably need: http://xenbits.xensource.com/xen-unstable.hg?rev/be20b11656bb Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: Advanced Micro Devices GmbH

[PATCH] kvm/svm: fix DR interception handling on upcoming AMD CPUs

Somehow the code line advancing the RIP and checking for exceptions got dropped between the post on the ML and the commit. Add it again to let guests boot on upcoming AMD CPUs again. Reported-by: Joerg Roedel joerg.roe...@amd.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86

Re: [PATCH] kvm/svm: fix DR interception handling on upcoming AMD CPUs

Roedel, Joerg wrote: On Tue, Feb 08, 2011 at 07:22:29PM -0500, Andre Przywara wrote: Somehow the code line advancing the RIP and checking for exceptions got dropped between the post on the ML and the commit. Add it again to let guests boot on upcoming AMD CPUs again. Reported-by: Joerg Roedel

[PATCH 1/2] kvm/x86: fix XSAVE bit scanning

and simply skip zero ones to also cover later features. CC: sta...@kernel.org [2.6.38] Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index bfd7763

[PATCH 2/2] kvm/x86: remove unneeded substitute search for missing CPUID entries

-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c |6 -- 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6e86cec..625143f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4959,12 +4959,6 @@ struct

Re: [PATCH 2/2] kvm/x86: remove unneeded substitute search for missing CPUID entries

Avi Kivity wrote: On 03/30/2011 03:01 PM, Andre Przywara wrote: If KVM cannot find an exact match for a requested CPUID leaf, the code will try to find the closest match instead of simply confessing it's failure. The heuristic is on one hand wrong nowadays, since it does not take the KVM CPUID

[PATCH 2/2] kvm/x86: move and fix substitue search for missing CPUID entries

values were returned in response to a CPUID intercept. CC: sta...@kernel.org [2.6.38] Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c | 19 +-- 1 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index

Re: [PATCH 2/2] kvm/x86: move and fix substitue search for missing CPUID entries

Avi Kivity wrote: On 03/31/2011 03:13 PM, Andre Przywara wrote: If KVM cannot find an exact match for a requested CPUID leaf, the code will try to find the closest match instead of simply confessing it's failure. The implementation was meant to satisfy the CPUID specification, but did

[PATCH 2/2 v3] kvm/x86: move and fix substitue search for missing CPUID entries

values were returned in response to a CPUID intercept. CC: sta...@kernel.org [2.6.38] Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/x86.c | 31 +-- 1 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm

[PATCH 1/3] NUMA: add Linux libnuma detection

Add detection of libnuma (mostly contained in the numactl package) to the configure script. Currently this is Linux only, but can be extended later should the need for other interfaces come up. Can be enabled or disabled on the command line, default is use if available. Signed-off-by: Andre

[PATCH 0/3][RFC] NUMA: add host side pinning

this is currently for Linux hosts (any other KVM hosts alive?) and for PC guests only. I think both can be fixed easily if someone requests it (and gives me a pointer to further information). Please comment on the approach in general and the implementation. Thanks and Regards, Andre. -- Andre

[PATCH 2/3] NUMA: add parsing of host NUMA pin option

-by: Andre Przywara andre.przyw...@amd.com --- sysemu.h |1 + vl.c | 18 ++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/sysemu.h b/sysemu.h index 6018d97..1b3f77b 100644 --- a/sysemu.h +++ b/sysemu.h @@ -139,6 +139,7 @@ extern long hpagesize; extern int

[PATCH 3/3] NUMA: realize NUMA memory pinning

According to the user-provided assignment bind the respective part of the guest's memory to the given host node. This uses Linux' libnuma interface to realize the pinning right after the allocation. Failures are not fatal, but produce a warning. Signed-off-by: Andre Przywara andre.przyw

Re: [PATCH 0/3][RFC] NUMA: add host side pinning

Anthony Liguori wrote: On 06/23/2010 04:09 PM, Andre Przywara wrote: Hi, these three patches add basic NUMA pinning to KVM. According to a user provided assignment parts of the guest's memory will be bound to different host nodes. This should increase performance in large virtual machines

Re: [PATCH 0/3][RFC] NUMA: add host side pinning

Alexander Graf wrote: On 24.06.2010, at 00:21, Anthony Liguori wrote: On 06/23/2010 04:09 PM, Andre Przywara wrote: Hi, these three patches add basic NUMA pinning to KVM. According to a user provided assignment parts of the guest's memory will be bound to different host nodes. This should

Re: [PATCH 0/3][RFC] NUMA: add host side pinning

Avi Kivity wrote: On 06/24/2010 01:58 PM, Andre Przywara wrote: So who would create the /dev/shm/nodeXX files? Currently it is QEMU. It creates a somewhat unique filename, opens and unlinks it. The difference would be to name the file after the option and to not unlink it. I can imagine

Re: [PATCH 0/3][RFC] NUMA: add host side pinning

Jes Sorensen wrote: On 06/24/10 13:34, Andre Przywara wrote: Avi Kivity wrote: On 06/24/2010 01:58 PM, Andre Przywara wrote: Non-anonymous memory doesn't work well with ksm and transparent hugepages. Is it possible to use anonymous memory rather than file backed? I'd prefer non-file backed

2.6.35-rc1 regression with pvclock and smp guests

. Please note that this is the guest kernel, the host kernel does not matter. I have no idea (and don't feel like ;-) debugging this, so I hope someone will find and fix the bug. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448

Re: about using vmcall instruction

code or mask the registers to 16 bits in the host. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More

Using Linux's CPUSET for KVM VCPUs

| +--/ kvm_guest_02 ... What do you think about it? It is worth implementing this? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: 2.6.35-rc1 regression with pvclock and smp guests

Avi Kivity wrote: On 07/22/2010 03:53 PM, Andre Przywara wrote: Hi, I found a regression with pvclock and SMP KVM _guests_. PVCLOCK enabled guest kernels boot with qemu-kvm.git and with smp=1, but with smp=2 halt at: Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled (last line shown

Re: 2.6.35-rc1 regression with pvclock and smp guests

Avi Kivity wrote: On 07/26/2010 11:47 AM, Andre Przywara wrote: Does this go away with CONFIG_DEBUG_RODATA=n? If so, it's a known bug in the atomic_*() clobber lists. Unfortunately the bug persists even with CONFIG_DEBUG_RODATA disabled. The debug options I had enabled now

Re: 2.6.35-rc1 regression with pvclock and smp guests

Avi Kivity wrote: On 07/27/2010 02:49 PM, Andre Przywara wrote: What is the guest executing when it hangs? Both VCPUs are halted, the monitor and System.map tell me it's in native_safe_halt(). The code sequence confirms this, it is an intentional sti;hlt condition. Using -smp 16 also shows

Re: 2.6.35-rc1 regression with pvclock and smp guests

Avi Kivity wrote: On 07/27/2010 03:21 PM, Andre Przywara wrote: Avi Kivity wrote: On 07/27/2010 02:49 PM, Andre Przywara wrote: What is the guest executing when it hangs? Both VCPUs are halted, the monitor and System.map tell me it's in native_safe_halt(). The code sequence confirms

Re: 2.6.35-rc1 regression with pvclock and smp guests

Avi Kivity wrote: On 07/27/2010 04:48 PM, Andre Przywara wrote: Wierd. Maybe the clock goes crazy. Let's see if it jumps forward alot: } while (unlikely(last != ret)); + + { +static u64 last_report; +if (ret last_report + 1

Re: 2.6.35-rc1 regression with pvclock and smp guests

Andre Przywara wrote: Avi Kivity wrote: On 07/27/2010 04:48 PM, Andre Przywara wrote: Wierd. Maybe the clock goes crazy. Let's see if it jumps forward alot: } while (unlikely(last != ret)); + + { +static u64 last_report; +if (ret last_report + 1

Re: 2.6.35-rc1 regression with pvclock and smp guests

Zachary Amsden wrote: On 07/27/2010 11:51 AM, Andre Przywara wrote: Andre Przywara wrote: Avi Kivity wrote: On 07/27/2010 04:48 PM, Andre Przywara wrote: Wierd. Maybe the clock goes crazy. Let's see if it jumps forward alot: } while (unlikely(last != ret

Re: 2.6.35-rc1 regression with pvclock and smp guests

Andre Przywara wrote: Andre Przywara wrote: Avi Kivity wrote: On 07/27/2010 04:48 PM, Andre Przywara wrote: Wierd. Maybe the clock goes crazy. Let's see if it jumps forward alot: } while (unlikely(last != ret)); + + { +static u64 last_report

Re: 2.6.35-rc1 regression with pvclock and smp guests

Zachary Amsden wrote: On 07/28/2010 02:25 AM, Andre Przywara wrote: Andre Przywara wrote: Andre Przywara wrote: Avi Kivity wrote: On 07/27/2010 04:48 PM, Andre Przywara wrote: Wierd. Maybe the clock goes crazy. Let's see if it jumps forward alot: } while (unlikely(last != ret

Re: KVM Processor cache size

or is this just out of curiosity? -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org

Re: KVM Processor cache size

Ulrich Drepper wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/02/2010 05:51 AM, Andre Przywara wrote: Do you have a use case for the cache size or is this just out of curiosity? glibc uses the cache size information returned by cpuid to perform optimizations. For instance, copy

Re: KVM Processor cache size

the target to the source? This would allow to check for migrate-ability before we transfer any data. Or should we handle this in a management application? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from

Re: KVM Processor cache size

. And missing migration experience should not be a road blocker for -cpu host. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: KVM Processor cache size

will be fully available to the guest), but only the size _reported_ to the guest. If you are still in doubt, you could do benchmarks with the default CPU model and with -cpu host (maybe even with my patch) to determine whether there is a difference. Regards, Andre. -- Andre Przywara AMD-Operating

Re: KVM Processor cache size

Anthony Liguori wrote: On 08/02/2010 08:08 AM, Avi Kivity wrote: On 08/02/2010 03:51 PM, Andre Przywara wrote: I sent a patch to include the cache size when using -cpu host, but this has been n'acked because the benefit is not clear. Anthony, why was this NACKed? First, there are programs

[PATCH 2/4] NUMA: add Linux libnuma detection

Add detection of libnuma (mostly contained in the numactl package) to the configure script. Currently this is Linux only, but can be extended later should the need for other interfaces come up. Can be enabled or disabled on the command line, default is use if available. Signed-off-by: Andre

[PATCH 3/4] NUMA: parse new host dependent command line options

to the current CPUSET for the one guest node) $ qemu ... -numa node -numa node -numa host,nodeid=0,membind=3 \ -numa host,nodeid=1,preferred=!2-3 (binding the first guest node to host node 3 and the second guest node to any node expect 2 and 3) Signed-off-by: Andre Przywara andre.przyw...@amd.com

[PATCH 0/4]: NUMA: add host binding

of the VNC update by Corentin Chary on Aug 11th: http://lists.gnu.org/archive/html/qemu-devel/2010-08/msg00517.html So it requires this patch to build (but not to apply). Please comment! Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany -- To unsubscribe

[PATCH 4/4] NUMA: realize NUMA memory pinning

According to the user-provided assignment bind the respective part of the guest's memory to the given host node. This uses Linux' mbind syscall (which is wrapped only in libnuma) to realize the pinning right after the allocation. Failures are not fatal, but produce a warning. Signed-off-by: Andre

[PATCH 1/4] NUMA: change existing NUMA guest code to use new bitmap implementation

binding code. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- cpus.c|2 +- hw/pc.c |4 +- monitor.c |2 +- sysemu.h | 11 ++- vl.c | 94 +++-- 5 files changed, 73 insertions(+), 40 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] Add definitions for current cpu models..

/msg01228.html Resending this patch set is on my plan for next week. What is the state of this patch? Will it go in soon? Then I'd rebase my patch set on top of it. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm

Re: [PATCH] Add cpu model configuration support.. (resend)

. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Andrew Bowd; Thomas M. McCoy; Giuliano

Re: [PATCH] Add cpu model configuration support.. (resend)

builtin_x86_defs[] = { #ifdef TARGET_X86_64 { .name = qemu64, I would just drop all definitions here except qemu{32,64} and kvm{32,64}. The other models should be described in the config file. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden

Re: [PATCH v2 06/30] KVM: remove realmode_lmsw function.

); -} - static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) { struct kvm_cpuid_entry2 *e = vcpu-arch.cpuid_entries[i]; -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: [PATCH v2 05/30] KVM: Provide callback to get/set control registers in emulator ops.

); - break; - default: - vcpu_printf(vcpu, %s: unexpected cr %u\n, __func__, cr); - } -} - static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) { struct kvm_cpuid_entry2 *e = vcpu-arch.cpuid_entries[i]; -- Andre Przywara AMD-OSRC

Re: [PATCH v2 07/30] KVM: Provide x86_emulate_ctxt callback to get current cpl

= emulator_set_cr, + .cpl = emulator_get_cpl, }; static void cache_all_regs(struct kvm_vcpu *vcpu) -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More

Re: [PATCH v3 16/30] KVM: x86 emulator: If LOCK prefix is used dest arg should be memory.

(!(c-d Lock) || c-dst.type != OP_MEM)) { kvm_queue_exception(ctxt-vcpu, UD_VECTOR); goto done; } -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: [PATCH v3 00/30] emulator cleanup

it failed before. Patch 1..13, 17: Reviewed-by: Andre Przywara andre.przyw...@amd.com I am still investigating a corner case in patch 14 (calling syscall/sysenter from real mode), and there is the issue in patch 16. I have only shortly looked over the others. Regards, Andre. -- Andre Przywara

tainted Linux kernel in default SMP QEMU/KVM guests

patches for all solutions, but I'd like to get advice from people on which one to pursue. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body

Re: Tracking KVM development

on this. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 488-3567-12 -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo

[PATCH] kvm/x86: enlarge number of possible CPUID leaves

Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86

Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

Avi Kivity wrote: On 12/01/2010 01:17 PM, Andre Przywara wrote: Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors

[PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/include

[PATCH 3/5] kvm/svm: enhance mov DR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm

[PATCH 1/5] kvm/svm: add new SVM feature bit names

the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86

[PATCH 5/5] kvm/svm: copy instruction bytes from VMCB

In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by: Andre Przywara andre.przyw

[PATCH 4/5] kvm/svm: implement enhanced INVLPG intercept

When the DecodeAssist feature is available, the linear address is provided in the VMCB on INVLPG intercepts. Use it directly to avoid any decoding and emulation. This is only useful for shadow paging, though. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c |7

[PATCH 0/5] kvm/svm: implement new DecodeAssist features

Hi, upcoming AMD CPUs will have a SVM enhancement called DecodeAssist which will provide more information when intercepting certain events. These information allows to skip the instruction fetching and decoding and handle the intercept immediately. This patch set implements all the features which

Re: [PATCH 2/5] kvm/svm: enhance MOV CR intercept handler

Avi Kivity wrote: On 12/07/2010 12:59 PM, Andre Przywara wrote: Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed

Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/include/asm/kvm_host.h |2 +- 1 files

[PATCH] kvm: cleanup CR8 handling

The handling of CR8 writes in KVM is currently somewhat cumbersome. This patch makes it look like the other CR register handlers and fixes a possible issue in VMX, where the RIP would be incremented despite an injected #GP. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86

[PATCH 5/5] kvm/svm: copy instruction bytes from VMCB

In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by: Andre Przywara andre.przyw

[PATCH -v2 0/5] kvm/svm: implement new DecodeAssist features

Hi, version 2 of the DecodeAssist patches. Changes over version 1: - goes on top of the CR8 handling fix I sent out earlier this week (required for proper handling of CR8 exceptions) - handles exception cases properly (for mov cr and mov dr) - uses X86_FEATURE_ names instead of SVM_FEATURE

[PATCH 1/5] kvm/svm: add new SVM feature bit names

the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm/svm.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86

[PATCH 3/5] kvm/svm: enhance mov DR intercept handler

Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/kvm

  1   2   3   4   5   6   7   >