Re: [PATCH v3 01/22] arm64: Add macros to read/write system registers

r, u32 set) > val |= set; > asm volatile("msr sctlr_el1, %0" : : "r" (val)); > } > + > +#define read_sysreg(r) ({\ > + u64 __val; \ > + asm volatile("mrs %0, " __stringify(r) : &quo

Re: [PATCH 03/15] arm64: Introduce helpers for page table levels

On Thu, Oct 08, 2015 at 06:22:34PM +0100, Suzuki K. Poulose wrote: > On 08/10/15 15:45, Christoffer Dall wrote: > >On Wed, Oct 07, 2015 at 10:26:14AM +0100, Marc Zyngier wrote: > >>I just had a chat with Catalin, who did shed some light on this. > >>It all has to do with rounding up. What you

Re: [PATCH 09/15] arm64: Add page size to the kernel image header

On Tue, Sep 15, 2015 at 04:41:18PM +0100, Suzuki K. Poulose wrote: > From: Ard Biesheuvel > > This patch adds the page size to the arm64 kernel image header > so that one can infer the PAGESIZE used by the kernel. This will > be helpful to diagnose failures to boot the

Re: [PATCH 09/15] arm64: Add page size to the kernel image header

On Fri, Oct 02, 2015 at 04:49:01PM +0100, Catalin Marinas wrote: > On Tue, Sep 15, 2015 at 04:41:18PM +0100, Suzuki K. Poulose wrote: > > From: Ard Biesheuvel <ard.biesheu...@linaro.org> > > > > This patch adds the page size to the arm64 kernel image header > > s

Re: [PATCH 12/14] arm64: Check for selected granule support

On Wed, Sep 02, 2015 at 12:19:07PM +0200, Ard Biesheuvel wrote: > On 2 September 2015 at 11:48, Ard Biesheuvel > wrote: > > Couldn't we allocate some flag bits in the Image header to communicate > > the page size to the bootloader? > > Something like this perhaps? >

Re: [PATCH 12/14] arm64: Check for selected granule support

On Thu, Aug 13, 2015 at 03:45:07PM +0100, Suzuki K. Poulose wrote: On 13/08/15 13:28, Steve Capper wrote: On 13 August 2015 at 12:34, Suzuki K. Poulose suzuki.poul...@arm.com wrote: __enable_mmu: + mrs x1, ID_AA64MMFR0_EL1 + ubfxx2, x1, #ID_AA64MMFR0_TGran_SHIFT, 4 +

Re: [PATCH 2/6] irqchip: GIC: Convert to EOImode == 1

On Wed, Aug 12, 2015 at 02:31:47PM +0100, Marc Zyngier wrote: On 11/08/15 10:15, Eric Auger wrote: On 07/09/2015 03:19 PM, Marc Zyngier wrote: static int gic_irq_set_irqchip_state(struct irq_data *d, @@ -272,11 +278,15 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs

Re: [PATCH 00/13] arm64: Virtualization Host Extension support

On Wed, Jul 08, 2015 at 05:19:03PM +0100, Marc Zyngier wrote: Marc Zyngier (13): arm/arm64: Add new is_kernel_in_hyp_mode predicate arm64: Allow the arch timer to use the HYP timer arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature arm64: KVM: skip HYP setup when already running in HYP

Re: [PATCH 11/13] arm64: Panic when VHE and non VHE CPUs coexist

On Wed, Jul 08, 2015 at 05:19:14PM +0100, Marc Zyngier wrote: Having both VHE and non-VHE capable CPUs in the same system is likely to be a recipe for disaster. If the boot CPU has VHE, but a secondary is not, we won't be able to downgrade and run the kernel at EL1. Add CPU hotplug to the

Re: [PATCH 07/13] arm64: KVM: VHE: Patch out use of HVC

On Wed, Jul 08, 2015 at 05:19:10PM +0100, Marc Zyngier wrote: --- /dev/null +++ b/arch/arm64/kvm/vhe-macros.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 - ARM Ltd + * Author: Marc Zyngier marc.zyng...@arm.com + * + * This program is free software; you can redistribute it and/or modify +

Re: [PATCH 1/2] arm64: qcom: Add define for ARMv8 implementer (MIDR)

On Fri, Jun 19, 2015 at 05:28:53PM -0500, Timur Tabi wrote: On 06/15/2015 05:59 AM, Catalin Marinas wrote: I think this patch together with the second one could go through the kvm tree. For the core arm64 part: Acked-by: Catalin Marinascatalin.mari...@arm.com Suzuki Poulose posted a patch

Re: [PATCH 1/2] arm64: qcom: Add define for ARMv8 implementer (MIDR)

Signed-off-by: Timur Tabi ti...@codeaurora.org I think this patch together with the second one could go through the kvm tree. For the core arm64 part: Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Mar 05, 2015 at 08:52:49PM +0900, Peter Maydell wrote: On 5 March 2015 at 20:04, Catalin Marinas catalin.mari...@arm.com wrote: On Thu, Mar 05, 2015 at 11:12:22AM +0100, Paolo Bonzini wrote: On 04/03/2015 18:28, Catalin Marinas wrote: Can you add that property to the device tree

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Mar 05, 2015 at 11:12:22AM +0100, Paolo Bonzini wrote: On 04/03/2015 18:28, Catalin Marinas wrote: Can you add that property to the device tree for PCI devices too? Yes but not with mainline yet: http://thread.gmane.org/gmane.linux.kernel.iommu/8935 We can add

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Mar 05, 2015 at 01:26:39PM +0100, Paolo Bonzini wrote: On 05/03/2015 13:03, Catalin Marinas wrote: I'd hate to have to do that. PCI should be entirely probeable given that we tell the guest where the host bridge is, that's one of its advantages. I didn't say a DT node per

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Wed, Mar 04, 2015 at 06:03:11PM +0100, Paolo Bonzini wrote: On 04/03/2015 15:29, Catalin Marinas wrote: I disagree it is 100% a host-side issue. It is a host-side issue _if_ the host tells the guest that the (virtual) device is non-coherent (or, more precisely, it does not explicitly

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

(please try to avoid top-posting) On Mon, Mar 02, 2015 at 06:20:19PM -0800, Mario Smarduch wrote: On 03/02/2015 08:31 AM, Christoffer Dall wrote: However, my concern with these patches are on two points: 1. It's not a fix-all. We still have the case where the guest expects the behavior

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Wed, Mar 04, 2015 at 12:50:57PM +0100, Ard Biesheuvel wrote: On 4 March 2015 at 12:35, Catalin Marinas catalin.mari...@arm.com wrote: On Mon, Mar 02, 2015 at 06:20:19PM -0800, Mario Smarduch wrote: On 03/02/2015 08:31 AM, Christoffer Dall wrote: However, my concern with these patches

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Wed, Mar 04, 2015 at 03:12:12PM +0100, Andrew Jones wrote: On Wed, Mar 04, 2015 at 01:43:02PM +0100, Ard Biesheuvel wrote: On 4 March 2015 at 13:29, Catalin Marinas catalin.mari...@arm.com wrote: On Wed, Mar 04, 2015 at 12:50:57PM +0100, Ard Biesheuvel wrote: I think we have

Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings

On Thu, Feb 19, 2015 at 10:54:43AM +, Ard Biesheuvel wrote: This is a 0th order approximation of how we could potentially force the guest to avoid uncached mappings, at least from the moment the MMU is on. (Before that, all of memory is implicitly classified as Device-nGnRnE) That's just

Re: [PATCH v3 2/3] arm/arm64: KVM: Ensure memslots are within KVM_PHYS_SIZE

entries when inserting entries in the Stage-2 page tables. Signed-off-by: Christoffer Dall christoffer.d...@linaro.org Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo

Re: [PATCH v3 1/3] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

. Thanks to Catalin Marinas for his help in figuring out a good solution to this challenge. I have also fixed various bugs and missing error code handling from the original patch. - Christoffer ] Cc: Marc Zyngier marc.zyng...@arm.com Cc: Catalin Marinas catalin.mari...@arm.com Signed-off

Re: [PATCH v3 3/3] arm64: Allow 48-bits VA space without ARM_SMMU

On Fri, Oct 10, 2014 at 11:14:30AM +0100, Christoffer Dall wrote: Now when KVM has been reworked to support 48-bits host VA space, we can allow systems to be configured with this option. However, the ARM SMMU driver also needs to be tweaked for 48-bit support so only allow the config option

Re: [PATCH v2 1/3] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

On Thu, Oct 09, 2014 at 12:01:37PM +0100, Christoffer Dall wrote: On Wed, Oct 08, 2014 at 10:47:04AM +0100, Catalin Marinas wrote: On Tue, Oct 07, 2014 at 08:39:54PM +0100, Christoffer Dall wrote: +static inline int kvm_prealloc_hwpgd(struct kvm *kvm, pgd_t *pgd) +{ + pud_t *pud

Re: [PATCH v2 1/3] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

On Tue, Oct 07, 2014 at 08:39:54PM +0100, Christoffer Dall wrote: I came up with the following based on your feedback, but I personally don't find it a lot easier to read than what I had already. Suggestions are welcome: At least PTRS_PER_S2_PGD and KVM_PREALLOC_LEVEL are clearer to me as

Re: [PATCH v2 0/3] arm/arm64: KVM: Host 48-bit VA support and IPA limits

On Mon, Oct 06, 2014 at 09:30:24PM +0100, Christoffer Dall wrote: The following host configurations have been tested with KVM on APM Mustang: [...] 3) 64KB + 39 bits VA space That would be 42-bit VA space. -- Catalin -- To unsubscribe from this list: send the line unsubscribe kvm in the

Re: [PATCH v2 1/3] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

On Mon, Oct 06, 2014 at 09:30:25PM +0100, Christoffer Dall wrote: +/** + * kvm_prealloc_hwpgd - allocate inital table for VTTBR + * @kvm: The KVM struct pointer for the VM. + * @pgd: The kernel pseudo pgd + * + * When the kernel uses more levels of page tables than the guest, we

Re: [PATCH 1/2] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

On Mon, Oct 06, 2014 at 02:41:18PM +0100, Christoffer Dall wrote: On Tue, Sep 30, 2014 at 01:39:47PM +0100, Catalin Marinas wrote: On Thu, Sep 25, 2014 at 08:42:53PM +0100, Christoffer Dall wrote: @@ -572,19 +614,36 @@ void kvm_free_stage2_pgd(struct kvm *kvm) return

Re: [PATCH 2/2] arm/arm64: KVM: Ensure memslots are within KVM_PHYS_SIZE

On Mon, Oct 06, 2014 at 02:47:01PM +0100, Christoffer Dall wrote: On Tue, Sep 30, 2014 at 01:46:51PM +0100, Catalin Marinas wrote: On Thu, Sep 25, 2014 at 08:42:54PM +0100, Christoffer Dall wrote: When creating or moving a memslot, make sure the IPA space is within the addressable range

Re: [PATCH 1/2] arm64: KVM: Implement 48 VA support for KVM EL2 and Stage-2

Hi Christoffer, On Thu, Sep 25, 2014 at 08:42:53PM +0100, Christoffer Dall wrote: diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index 7796051..048f37f 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -409,7 +409,7 @@ static void update_vttbr(struct kvm *kvm)

Re: [PATCH 2/2] arm/arm64: KVM: Ensure memslots are within KVM_PHYS_SIZE

On Thu, Sep 25, 2014 at 08:42:54PM +0100, Christoffer Dall wrote: When creating or moving a memslot, make sure the IPA space is within the addressable range of the guest. Otherwise, user space can create too large a memslot and KVM would try to access potentially unallocated page table

Re: [PATCH] arm/arm64: KVM: Fix VTTBR_BADDR_MASK and pgd alloc

allocation to be based on the 40 bit IPA range instead of the maximum possible 48 bit PA range. - Christoffer ] Signed-off-by: Joel Schopp joel.sch...@amd.com Signed-off-by: Christoffer Dall christoffer.d...@linaro.org Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v6] arm64: fix VTTBR_BADDR_MASK

On Mon, Sep 22, 2014 at 04:56:58PM +0100, Joel Schopp wrote: The TCR_EL2.PS setting should be done based on the ID_A64MMFR0_EL1 but you can do this in __do_hyp_init (it looks like this function handles VTCR_EL2.PS already, not sure why it does do it for TCR_EL2 as well). So IMO you

Re: [PATCH v6] arm64: fix VTTBR_BADDR_MASK

On Tue, Sep 09, 2014 at 12:08:52AM +0100, Joel Schopp wrote: The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current systems. Rather than just add a bit it seems like a good time to also set things at run-time instead of compile time to accomodate more hardware. This

Re: [PATCH v6] arm64: fix VTTBR_BADDR_MASK

On Fri, Sep 19, 2014 at 04:28:54PM +0100, Catalin Marinas wrote: On Tue, Sep 09, 2014 at 12:08:52AM +0100, Joel Schopp wrote: The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current systems. Rather than just add a bit it seems like a good time to also set things at run

Re: [PATCH] MAINTAINERS: co-maintainance of KVM/{arm,arm64}

maintainers for both ports. Cc: Catalin Marinas catalin.mari...@arm.com Cc: Russell King li...@arm.linux.org.uk Cc: Paolo Bonzini pbonz...@redhat.com Cc: Gleb Natapov g...@redhat.com Signed-off-by: Marc Zyngier marc.zyng...@arm.com Signed-off-by: Christoffer Dall christoffer.d...@linaro.org

Re: [RFC] ARM VM System Sepcification

On 26 February 2014 20:05, Christoffer Dall christoffer.d...@linaro.org wrote: On Wed, Feb 26, 2014 at 08:55:58PM +0100, Arnd Bergmann wrote: On Wednesday 26 February 2014 10:34:54 Christoffer Dall wrote: For more information about UEFI and ACPI booting, see [4] and [5]. What's the point of

Re: [PATCH v4 00/12] arm/arm64: KVM: host cache maintenance when guest caches are off

On Wed, Feb 19, 2014 at 09:02:34AM +, Marc Zyngier wrote: On 2014-02-18 20:57, Eric Northup wrote: On Tue, Feb 18, 2014 at 7:27 AM, Marc Zyngier marc.zyng...@arm.com wrote: When we run a guest with cache disabled, we don't flush the cache to the Point of Coherency, hence possibly

Re: [PATCH v4 04/12] ARM: KVM: introduce kvm_p*d_addr_end

64bit clean versions of the same helpers, and use them in the stage-2 page table code. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord

Re: [PATCH v3 05/11] ARM: LPAE: provide an IPA capable pmd_addr_end

On Fri, Feb 07, 2014 at 04:04:56AM +, Christoffer Dall wrote: On Thu, Feb 06, 2014 at 10:43:28AM +, Catalin Marinas wrote: On Wed, Feb 05, 2014 at 07:55:45PM +, Marc Zyngier wrote: The default pmd_addr_end macro uses an unsigned long to represent the VA. When used with KVM

Re: [PATCH v3 05/11] ARM: LPAE: provide an IPA capable pmd_addr_end

On Wed, Feb 05, 2014 at 07:55:45PM +, Marc Zyngier wrote: The default pmd_addr_end macro uses an unsigned long to represent the VA. When used with KVM and stage-2 translation, the VA is actually an IPA, which is up to 40 bits. This also affect the SMMU driver, which also deals with stage-2

Re: [PATCH v3 06/11] ARM: KVM: force cache clean on page fault when caches are off

christoffer.d...@linaro.org Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 08/11] ARM: KVM: fix ordering of 64bit coprocessor accesses

-first, CRm... Move the 64bit test to be last in order to match the documentation. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Christoffer Dall christoffer.d...@linaro.org Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line

Re: [PATCH v3 07/11] ARM: KVM: fix handling of trapped 64bit coprocessor accesses

the expected string in case of failing match. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Christoffer Dall christoffer.d...@linaro.org Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message

Re: [PATCH v3 09/11] ARM: KVM: introduce per-vcpu HYP Configuration Register

to be changed on a per-vcpu basis. The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR field, initialized at setup time. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Christoffer Dall christoffer.d...@linaro.org Acked-by: Catalin Marinas catalin.mari

Re: [PATCH v3 11/11] ARM: KVM: trap VM system registers until MMU and caches are ON

, which is to leave these registers in complete control of the guest. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More

Re: [PATCH v3 10/11] ARM: KVM: add world-switch for AMAIR{0,1}

/handle. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Christoffer Dall christoffer.d...@linaro.org Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo

Re: [PATCH v2] ARM: mm: Fix stage-2 device memory attributes

On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote: On 24/01/14 23:37, Christoffer Dall wrote: On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote: --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -120,13 +120,19 @@ /*

Re: [PATCH v2] ARM: mm: Fix stage-2 device memory attributes

On Mon, Jan 27, 2014 at 05:02:25PM +, Marc Zyngier wrote: On 27/01/14 16:57, Catalin Marinas wrote: On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote: On 24/01/14 23:37, Christoffer Dall wrote: On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote: --- a/arch/arm

Re: [PATCH v3 1/2] KVM: ARM: Support hugetlbfs backed huge pages

) 6) /* HAP[2:1] */ +#define PMD_S2_RDWR(_AT(pmdval_t, 3) 6) /* HAP[2:1] */ + /* * Memory Attribute override for Stage-2 (MemAttr[3:0]) */ For the arm64 part: Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe

Re: [PATCH 3/4] arm64: KVM: let other tasks run when hitting WFE

On Mon, Jul 22, 2013 at 01:51:52PM +0100, Christoffer Dall wrote: On 22 July 2013 10:53, Raghavendra KT raghavendra.kt.li...@gmail.com wrote: On Fri, Jul 19, 2013 at 7:23 PM, Marc Zyngier marc.zyng...@arm.com wrote: So far, when a guest executes WFE (like when waiting for a spinlock to

Re: Planning the merge of KVM/arm64

On Wed, Jun 05, 2013 at 07:01:05AM +0100, Gleb Natapov wrote: On Tue, Jun 04, 2013 at 10:57:32PM -0700, Christoffer Dall wrote: On 4 June 2013 09:37, Gleb Natapov g...@redhat.com wrote: On Tue, Jun 04, 2013 at 05:51:41PM +0200, Paolo Bonzini wrote: Il 04/06/2013 17:43, Christoffer Dall ha

Re: Planning the merge of KVM/arm64

On Tue, Jun 04, 2013 at 02:13:52PM +0100, Anup Patel wrote: Hi Marc, On Tue, Jun 4, 2013 at 5:59 PM, Marc Zyngier marc.zyng...@arm.com wrote: Guys, The KVM/arm64 code is now, as it seems, in good enough shape to be merged. I've so far addressed all the comments, and it doesn't seem any

Re: [PATCH v4 22/32] arm64: KVM: define 32bit specific registers

in most cases. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More

Re: [PATCH v4 23/32] arm64: KVM: 32bit GP register access

On Tue, May 14, 2013 at 03:13:51PM +0100, Marc Zyngier wrote: Allow access to the 32bit register file through the usual API. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 24/32] arm64: KVM: 32bit conditional execution emulation

Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 25/32] arm64: KVM: 32bit handling of coprocessor traps

-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 26/32] arm64: KVM: CPU specific 32bit coprocessor access

On Tue, May 14, 2013 at 03:13:54PM +0100, Marc Zyngier wrote: Enable handling of CPU specific 32bit coprocessor access. Not much here either. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari

Re: [PATCH v4 27/32] arm64: KVM: 32bit specific register world switch

On Tue, May 14, 2013 at 03:13:55PM +0100, Marc Zyngier wrote: Allow registers specific to 32bit guests to be saved/restored during the world switch. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas

Re: [PATCH v4 28/32] arm64: KVM: 32bit guest fault injection

On Tue, May 14, 2013 at 03:13:56PM +0100, Marc Zyngier wrote: Add fault injection capability for 32bit guests. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from

Re: [PATCH v4 29/32] arm64: KVM: enable initialization of a 32bit vcpu

by the KVM_CAP_ARM_EL1_32BIT capability. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http

Re: [PATCH v4 32/32] arm64: KVM: document kernel object mappings in HYP

On Tue, May 14, 2013 at 03:14:00PM +0100, Marc Zyngier wrote: HYP mode has access to some of the kernel pages. Document the memory mapping and the offset between kernel VA and HYP VA. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 30/32] arm64: KVM: userspace API documentation

On Tue, May 14, 2013 at 03:13:58PM +0100, Marc Zyngier wrote: Unsurprisingly, the arm64 userspace API is extremely similar to the 32bit one, the only significant difference being the ONE_REG register mapping. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas

Re: [PATCH v4 21/32] arm64: KVM: Build system integration

On Tue, May 21, 2013 at 05:09:47PM +0100, Paolo Bonzini wrote: - Messaggio originale - Da: Catalin Marinas catalin.mari...@arm.com A: Marc Zyngier marc.zyng...@arm.com Cc: linux-arm-ker...@lists.infradead.org, kvm...@lists.cs.columbia.edu, kvm@vger.kernel.org, Will Deacon

Re: [PATCH v4 13/32] arm64: KVM: MMIO access backend

On Tue, May 14, 2013 at 03:13:41PM +0100, Marc Zyngier wrote: Define the necessary structures to perform an MMIO access. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 14/32] arm64: KVM: guest one-reg interface

On Tue, May 14, 2013 at 03:13:42PM +0100, Marc Zyngier wrote: Let userspace play with the guest registers. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- /dev/null +++ b/arch/arm64/kvm/guest.c ... +static int get_core_reg(struct

Re: [PATCH v4 15/32] arm64: KVM: hypervisor initialization code

On Tue, May 14, 2013 at 03:13:43PM +0100, Marc Zyngier wrote: --- /dev/null +++ b/arch/arm64/kvm/hyp-init.S ... + .text + .pushsection.hyp.idmap.text, ax + + .align 11 + +__kvm_hyp_init: + .global __kvm_hyp_init + +ENTRY(__kvm_hyp_init_vector) Why do you need both

Re: [PATCH v4 16/32] arm64: KVM: HYP mode world switch implementation

On Tue, May 14, 2013 at 03:13:44PM +0100, Marc Zyngier wrote: +// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); +ENTRY(__kvm_tlb_flush_vmid_ipa) + kern_hyp_va x0 + ldr x2, [x0, #KVM_VTTBR] + msr vttbr_el2, x2 + isb + + /* +

Re: [PATCH v4 17/32] arm64: KVM: Exit handling

On Tue, May 14, 2013 at 03:13:45PM +0100, Marc Zyngier wrote: Handle the exit of a VM, decoding the exit reason from HYP mode and calling the corresponding handler. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin

Re: [PATCH v4 18/32] arm64: KVM: Plug the VGIC

On Tue, May 14, 2013 at 03:13:46PM +0100, Marc Zyngier wrote: Add support for the in-kernel GIC emulation. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from

Re: [PATCH v4 19/32] arm64: KVM: Plug the arch timer

ISBs if you get an ERET anyway. Otherwise: Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 20/32] arm64: KVM: PSCI implementation

On Tue, May 14, 2013 at 03:13:48PM +0100, Marc Zyngier wrote: Wire the PSCI backend into the exit handling code. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from

Re: [PATCH v4 21/32] arm64: KVM: Build system integration

On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote: --- /dev/null +++ b/arch/arm64/kvm/Kconfig ... +config KVM_ARM_VGIC +bool + depends on KVM_ARM_HOST OF + select HAVE_KVM_IRQCHIP + ---help--- + Adds support for a hardware assisted, in-kernel GIC

Re: [PATCH v4 31/32] arm64: KVM: MAINTAINERS update

On Tue, May 14, 2013 at 03:13:59PM +0100, Marc Zyngier wrote: Elect myself as the KVM/arm64 maintainer. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message

Re: [PATCH v3 0/7] ARM: KVM: various mmu related fixes for 3.10

phys_addr_t instead of unsigned long long for HYP PGDs ARM: KVM: don't special case PC when doing an MMIO ARM: KVM: get rid of S2_PGD_SIZE ARM: KVM: drop use of PAGE_S2_DEVICE This series looks good to me: Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send

Re: [PATCH v4 01/32] arm64: KVM: define HYP and Stage-2 translation page flags

On Tue, May 14, 2013 at 03:13:29PM +0100, Marc Zyngier wrote: Add HYP and S2 page flags, for both normal and device memory. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 02/32] arm64: KVM: HYP mode idmap support

: Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 03/32] arm64: KVM: EL2 register definitions

On Tue, May 14, 2013 at 03:13:31PM +0100, Marc Zyngier wrote: Define all the useful bitfields for EL2 registers. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from

Re: [PATCH v4 04/32] arm64: KVM: system register definitions for 64bit guests

On Tue, May 14, 2013 at 03:13:32PM +0100, Marc Zyngier wrote: Define the saved/restored registers for 64bit guests. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe

Re: [PATCH v4 05/32] arm64: KVM: Basic ESR_EL2 helpers and vcpu register access

bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu) +{ + return !!(kvm_vcpu_get_hsr(vcpu) ESR_EL2_ISV); +} You kept these '!!' ;). BTW, would the compiler handle the conversion between the integer and bool here? Either way is fine by me: Reviewed-by: Catalin Marinas catalin.mari

Re: [PATCH v4 06/32] arm64: KVM: fault injection into a guest

On Tue, May 14, 2013 at 03:13:34PM +0100, Marc Zyngier wrote: Implement the injection of a fault (undefined, data abort or prefetch abort) into a 64bit guest. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas

Re: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend

On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote: +static inline bool kvm_is_write_fault(unsigned long esr) +{ + unsigned long esr_ec = esr ESR_EL2_EC_SHIFT; Not that it would make much difference but for consistency - we use esr as an 'unsigned int' in the arm64 code (only

Re: [PATCH v4 08/32] arm64: KVM: user space interface

On Tue, May 14, 2013 at 03:13:36PM +0100, Marc Zyngier wrote: Provide the kvm.h file that defines the user space visible interface. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 09/32] arm64: KVM: system register handling

On Tue, May 14, 2013 at 03:13:37PM +0100, Marc Zyngier wrote: Provide 64bit system register handling, modeled after the cp15 handling for ARM. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari

Re: [PATCH v4 07/32] arm64: KVM: architecture specific MMU backend

On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote: On 20/05/13 16:57, Catalin Marinas wrote: On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote: +static inline bool kvm_is_write_fault(unsigned long esr) +{ + unsigned long esr_ec = esr ESR_EL2_EC_SHIFT

Re: [PATCH v4 10/32] arm64: KVM: CPU specific system registers handling

On Tue, May 14, 2013 at 03:13:38PM +0100, Marc Zyngier wrote: Add the support code for CPU specific system registers. Not much here yet. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari

Re: [PATCH v4 11/32] arm64: KVM: virtual CPU reset

On Tue, May 14, 2013 at 03:13:39PM +0100, Marc Zyngier wrote: Provide the reset code for a virtual CPU booted in 64bit mode. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari...@arm.com

Re: [PATCH v4 12/32] arm64: KVM: kvm_arch and kvm_vcpu_arch definitions

On Tue, May 14, 2013 at 03:13:40PM +0100, Marc Zyngier wrote: Provide the architecture dependent structures for VM and vcpu abstractions. Reviewed-by: Christopher Covington c...@codeaurora.org Signed-off-by: Marc Zyngier marc.zyng...@arm.com Reviewed-by: Catalin Marinas catalin.mari

Re: [PATCH v2 02/10] arm64: uaccess s/might_sleep/might_fault/

(-) For arm64: Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe kvm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [RFC PATCH 0/2] ARM: KVM: Moving GIC/timer out of arch/arm

Hi Gleb, On Sun, May 12, 2013 at 10:03:59AM +0100, Gleb Natapov wrote: On Fri, May 03, 2013 at 04:55:01PM +0100, Marc Zyngier wrote: On 03/05/13 16:31, Anup Patel wrote: On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier marc.zyng...@arm.com wrote: As KVM/arm64 is looming on the horizon, it

Re: [PATCH v3 24/32] arm64: KVM: 32bit GP register access

On Sat, May 11, 2013 at 01:36:30AM +0100, Christoffer Dall wrote: On Tue, May 07, 2013 at 05:33:03PM +0100, Catalin Marinas wrote: On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote: On 02/05/13 17:09, Catalin Marinas wrote: BTW, on arch/arm it looks like this is used when you

Re: [PATCH v3 24/32] arm64: KVM: 32bit GP register access

On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote: On 02/05/13 17:09, Catalin Marinas wrote: BTW, on arch/arm it looks like this is used when you get a data abort with PC as the destination register and you inject a prefetch abort in this case. Why isn't this a normal data abort

Re: [PATCH v3 00/32] Port of KVM to arm64

On Mon, Apr 08, 2013 at 05:17:02PM +0100, Marc Zyngier wrote: This series contains the third version of KVM for arm64. It depends on the following branches/series: - git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git soc-armv8-model Catalin's platform support branch

Re: [PATCH v3 16/32] arm64: KVM: hypervisor initialization code

On Mon, Apr 08, 2013 at 05:17:18PM +0100, Marc Zyngier wrote: Provide EL2 with page tables and stack, and set the vectors to point to the full blown world-switch code. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm64/include/asm/kvm_host.h | 13 +

Re: [PATCH v3 19/32] arm64: KVM: Plug the VGIC

On Wed, Apr 24, 2013 at 12:43:21PM +0100, Marc Zyngier wrote: On 24/04/13 00:00, Christoffer Dall wrote: On Mon, Apr 08, 2013 at 05:17:21PM +0100, Marc Zyngier wrote: Add support for the in-kernel GIC emulation. The include file is a complete duplicate of the 32bit one - something to fix

Re: [PATCH v2 3/5] ARM: KVM: relax cache maintainance when building page tables

On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote: Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code) introduced code that flushes page tables to the point of coherency. This is overkill (point of unification is enough and already done), and actually not required if

Re: [PATCH v2 1/5] ARM: KVM: be more thorough when invalidating TLBs

On Thu, May 02, 2013 at 03:38:58PM +0100, Marc Zyngier wrote: diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index f7793df..9e2d906c 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S ... -static void clear_pte_entry(pte_t *pte) +static void

Re: [PATCH v3 20/32] arm64: KVM: Plug the arch timer

On Wed, Apr 24, 2013 at 12:43:51PM +0100, Marc Zyngier wrote: On 24/04/13 00:00, Christoffer Dall wrote: On Mon, Apr 08, 2013 at 05:17:22PM +0100, Marc Zyngier wrote: Add support for the in-kernel timer emulation. The include file is a complete duplicate of the 32bit one - something to fix

Re: [PATCH v3 24/32] arm64: KVM: 32bit GP register access

On Mon, Apr 08, 2013 at 05:17:26PM +0100, Marc Zyngier wrote: static inline bool kvm_vcpu_reg_is_pc(const struct kvm_vcpu *vcpu, int reg) { - return false; + return (vcpu_mode_is_32bit(vcpu)) reg == 15; } On AArch64, would ESR_EL2 have SRT == 15 when the source/destination

Re: [PATCH v3 07/32] arm64: KVM: fault injection into a guest

On Mon, Apr 08, 2013 at 05:17:09PM +0100, Marc Zyngier wrote: +static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr) +{ + unsigned long cpsr = *vcpu_cpsr(vcpu); + int is_aarch32; + u32 esr = 0; + + is_aarch32 = vcpu_mode_is_32bit(vcpu); Minor

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