On Sat, Dec 26, 2015 at 01:54:55PM -0800, Mario Smarduch wrote:
> Add helper functions to enable access to fp/smid on guest entry and save host
> fpexc on vcpu put, check if fp/simd registers are dirty and add new vcpu
> fields.
>
> Signed-off-by: Mario Smarduch
> ---
>
On Mon, Dec 21, 2015 at 11:34:25AM -0800, Mario Smarduch wrote:
>
>
> On 12/18/2015 11:45 PM, Christoffer Dall wrote:
> > On Fri, Dec 18, 2015 at 05:17:00PM -0800, Mario Smarduch wrote:
> >> On 12/18/2015 5:54 AM, Christoffer Dall wrote:
> >>> On Sun, Dec
On Tue, Dec 22, 2015 at 11:08:10AM +, Peter Maydell wrote:
> On 22 December 2015 at 09:55, Marc Zyngier wrote:
> > Assuming we trap a coprocessor access, and decide that the access
> > is illegal, we will inject an exception in the guest. In this
> > case, we shouldn't
On Thu, Dec 17, 2015 at 03:22:50PM +0800, Shannon Zhao wrote:
>
>
> On 2015/12/17 4:33, Christoffer Dall wrote:
> > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote:
> >> Hi,
> >>
> >> On 2015/12/16 15:31, Shannon Zhao wrote:
> >>
8 +1120,17 @@ static int init_hyp_mode(void)
>* Init HYP view of VGIC
>*/
> err = kvm_vgic_hyp_init();
> - if (err)
> + switch (err) {
> + case 0:
> + vgic_present = true;
> + break;
> + case -ENODEV:
> +
On Sun, Dec 06, 2015 at 05:07:12PM -0800, Mario Smarduch wrote:
> This patch adds vcpu fields to configure hcptr trap register which is also
> used
> to determine if fp/simd registers are dirty. Adds a field to save host FPEXC,
> and offsets associated offsets.
offsets offsets?
>
>
On Sun, Dec 06, 2015 at 05:07:14PM -0800, Mario Smarduch wrote:
> This patch tracks armv7 and armv8 fp/simd hardware state with cptr_el2
> register.
> On vcpu_load for 32 bit guests enable FP access, and enable fp/simd
> trapping for 32 and 64 bit guests. On first fp/simd access trap to handler
ore host. */
> + if (kvm_vcpu_vfp_isdirty(vcpu))
> + kvm_restore_host_vfp_state(vcpu);
> +
> + /* Restore host FPEXC trashed in vcpu_load */
> + kvm_restore_host_fpexc(vcpu);
> +
> /*
>* The arch-generic KVM code expects the cpu field of a v
On Fri, Dec 18, 2015 at 05:17:00PM -0800, Mario Smarduch wrote:
> On 12/18/2015 5:54 AM, Christoffer Dall wrote:
> > On Sun, Dec 06, 2015 at 05:07:14PM -0800, Mario Smarduch wrote:
> >> This patch tracks armv7 and armv8 fp/simd hardware state with cptr_el2
> >> registe
On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote:
> Hi,
>
> On 2015/12/16 15:31, Shannon Zhao wrote:
> >> > But in this case, you're returning an error if it is *not*
> >> > initialized.
> >> > I understand that in that case you cannot return an interrupt
> >> >
ier seems the right thing to do,
> having verified that the output code is similar.
To quote Rusty when he reviewd some of my first KVM patches:
"I consider inline the register keyword of the 90s"
You can take that as an:
Acked-by: Christoffer Dall <christoffer.d...@linaro.or
On Tue, Dec 15, 2015 at 03:46:03AM +, Bhushan Bharat wrote:
>
> Hi All,
>
> I am running "iperf" in KVM guest on ARM64 machine and observing below crash.
Which host/guest kernel version is this?
Which hardware?
-Christoffer
>
> =
> $iperf -c 3.3.3.3 -P 4 -t 0
On Tue, Dec 15, 2015 at 03:59:31PM +, Marc Zyngier wrote:
> On 15/12/15 15:50, Shannon Zhao wrote:
> >
> >
> > On 2015/12/15 23:33, Marc Zyngier wrote:
> >> On 15/12/15 08:49, Shannon Zhao wrote:
> From: Shannon Zhao
>
> Add a new kvm device type
On Mon, Dec 07, 2015 at 10:53:38AM +, Marc Zyngier wrote:
> As we've now switched to the new world switch implementation,
> remove the weak attributes, as nobody is supposed to override
> it anymore.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked
mov x0, x1
> + ret
> +ENDPROC(__guest_exit)
> +
> + /* Insert fault handling here */
> diff --git a/arch/arm64/kvm/hyp/hyp.h b/arch/arm64/kvm/hyp/hyp.h
> index 454e46f..0809653 100644
> --- a/arch/arm64/kvm/hyp/hyp.h
> +++ b/arch/arm64/kvm/hyp/hyp.h
> @@ -52,
-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
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On Mon, Dec 07, 2015 at 10:53:22AM +, Marc Zyngier wrote:
> Implement the timer save restore as a direct translation of
> the assembly code version.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
nction level.
>
> In order to cope with this, add the "hyp_alternate_select" macro that
> outputs a brief sequence of code that in turn can be patched, allowing
> an alternative function to be selected.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked-by:
vgic = >arch.vgic;
> + void __iomem *base = kern_hyp_va(vgic->vctrl_base);
> + int i, nr_lr;
> +
> + if (!base)
> + return;
> +
> + writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
> + writel_relaxed(cpu_if->vgic_vmcr, base + GICH
}
>
> - vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[LR_INDEX(lr)] = lr_val;
> + vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)] = lr_val;
>
> if (!(lr_desc.state & LR_STATE_MASK))
> vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U <
; + write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(3)], ICH_LR3_EL2);
> + case 2:
> + write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(2)], ICH_LR2_EL2);
> + case 1:
> + write_gicreg(cpu_if->vgic_lr[VGIC_V3_LR_INDEX(1)], ICH_LR1_EL2);
> + c
just return if *any* IRQ is active on the VCPU in question.
This is of course bogus, as we should check if the specific IRQ in
quesiton is active on the distributor instead.
Reported-by: Eric Auger <eric.au...@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
-
t;>>>>>> overflow
> >>>>>>>>>> caused by a given counter. If the status is now 0, the interrupt
> >>>>>>>>>> line
> >>>>>>>>>> drops. If the s
On Wed, Dec 02, 2015 at 01:19:22PM +, Marc Zyngier wrote:
> On 02/12/15 11:53, Christoffer Dall wrote:
> > On Wed, Dec 02, 2015 at 09:47:43AM +, Marc Zyngier wrote:
> >> On 02/12/15 09:27, Christoffer Dall wrote:
> >>> On Tue, Dec 01, 2015 at 06:51:
On Wed, Dec 02, 2015 at 03:21:49PM +, Marc Zyngier wrote:
> On 02/12/15 11:47, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote:
> >> As we've now switched to the new world switch implementation,
> >> remove the weak attrib
On Wed, Dec 02, 2015 at 03:29:50PM +, Marc Zyngier wrote:
> On 02/12/15 11:53, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:50:06PM +, Marc Zyngier wrote:
> >> Implement the fpsimd save restore, keeping the lazy part in
> >> assembler (as retur
On Thu, Nov 12, 2015 at 07:59:14PM +0800, Jisheng Zhang wrote:
> vgic_io_ops is only referenced within vgic.c, so it can be declared
> static.
>
> Signed-off-by: Jisheng Zhang
Applied to queue,
-Christoffer
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On Wed, Dec 02, 2015 at 08:04:42PM +0100, Ard Biesheuvel wrote:
> On 2 December 2015 at 19:50, Christoffer Dall
> <christoffer.d...@linaro.org> wrote:
> > On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote:
> >> This function takes stage-II physical addre
On Tue, Dec 01, 2015 at 04:03:52PM +0300, Pavel Fedin wrote:
> This function takes stage-II physical addresses (A.K.A. IPA), on input, not
> real physical addresses. This causes kvm_is_device_pfn() to return wrong
> values, depending on how much guest and host memory maps match. This
> results in
On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote:
> On 01/12/15 15:39, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote:
> >> KVM so far relies on code patching, and is likely to use it more
> >> in the future.
d don't remember why we did things this way.
Maybe I'm being over-cautious though...
Otherwise:
Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
> ---
> arch/arm64/kvm/hyp/debug-sr.c | 3 +++
> arch/arm6
store_host_state(vcpu);
>
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> index 3f81a4d..41b9d30 100644
> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> @@ -103,7 +103,7 @@ void __hyp_text __sysreg32_save_state(struct kvm_vcpu
> *vcpu)
>
+ write_sysreg(kvm->arch.vttbr, vttbr_el2);
> + isb();
> +
> + asm volatile("tlbi vmalls12e1is" : : );
> + dsb(ish);
> + isb();
> +
> + write_sysreg(0, vttbr_el2);
> +}
> +
> +void __hyp_text __tlb_flush_vm_context(void)
> +{
&g
__hyp_do_panic(str_va - HYP_PAGE_OFFSET + PAGE_OFFSET,
is the first parameter hyp_kern_va(str_va) ? If so, can you add that
define instead?
> +spsr, elr,
> + read_sysreg(esr_el2), read_sysreg(far_el2),
> +read_sysreg(hpfar_el2), par,
On Wed, Dec 02, 2015 at 09:47:43AM +, Marc Zyngier wrote:
> On 02/12/15 09:27, Christoffer Dall wrote:
> > On Tue, Dec 01, 2015 at 06:51:00PM +, Marc Zyngier wrote:
> >> On 01/12/15 15:39, Christoffer Dall wrote:
> >>> On Fri, Nov 27, 2015 at 06:50:
On Fri, Nov 27, 2015 at 06:50:08PM +, Marc Zyngier wrote:
> Add the entry points for HYP mode (both for hypercalls and
> exception handling).
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
--
To un
On Fri, Nov 27, 2015 at 06:50:15PM +, Marc Zyngier wrote:
> As we've now switched to the new world switch implementation,
> remove the weak attributes, as nobody is supposed to override
> it anymore.
Why not remove the aliases and change the callers?
-Christoffer
>
> Signed-off-by: Marc
On Fri, Nov 27, 2015 at 06:50:14PM +, Marc Zyngier wrote:
> As we've now rewritten most of our code-base in C, most of the
> KVM-specific code in asm-offset.c is useless. Delete-time again!
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked-by: Christoffer D
ore)
>
> mrs x1, hcr_el2
> tbnzx1, #HCR_RW_SHIFT, 1f
> - ldr x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
> + ldr x4, [x3, #VCPU_FPEXC32_EL2]
> msr fpexc32_el2, x4
> 1:
> pop x4, lr
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr
On Fri, Nov 27, 2015 at 06:50:12PM +, Marc Zyngier wrote:
> This is it. We remove all of the code that has now been rewritten.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
--
To unsubscribe from thi
On Fri, Nov 27, 2015 at 06:50:11PM +, Marc Zyngier wrote:
> In order to run C code in HYP, we must make sure that the kernel's
> RO section in mapped into HYP (otherwise things break badly).
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Acked-by: Christoffer D
On Tue, Dec 01, 2015 at 05:51:46PM +, Marc Zyngier wrote:
> On 01/12/15 12:00, Christoffer Dall wrote:
> > On Tue, Dec 01, 2015 at 09:58:23AM +, Marc Zyngier wrote:
> >> On 30/11/15 20:33, Christoffer Dall wrote:
> >>> On Fri, Nov 27, 2015 at 06:49:
On Fri, Nov 27, 2015 at 06:50:03PM +, Marc Zyngier wrote:
> Contrary to the previous patch, the guest entry is fairly different
> from its assembly counterpart, mostly because it is only concerned
> with saving/restoring the GP registers, and nothing else.
>
> Signed-off-by: Marc Zyngier
On Fri, Nov 27, 2015 at 06:50:04PM +, Marc Zyngier wrote:
> KVM so far relies on code patching, and is likely to use it more
> in the future. The main issue is that our alternative system works
> at the instruction level, while we'd like to have alternatives at
> the function level.
>
> In
On Tue, Dec 01, 2015 at 03:01:16PM +, Marc Zyngier wrote:
> On 01/12/15 14:47, Christoffer Dall wrote:
> > On Tue, Dec 01, 2015 at 01:06:31PM +, Marc Zyngier wrote:
> >> On 01/12/15 12:56, Christoffer Dall wrote:
> >>> On Fri, Nov 27, 2015 at 06:50:
write_sysreg(spsr[KVM_SPSR_FIQ], spsr_fiq);
> +
nit: white space
> + write_sysreg(sysreg[DACR32_EL2], dacr32_el2);
> + write_sysreg(sysreg[IFSR32_EL2], ifsr32_el2);
> +
> + if (vcpu->arch.debug_flags & KVM_ARM64
[TPIDRRO_EL0], tpidrro_el0);
> + write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1);
> + write_sysreg(ctxt->sys_regs[AMAIR_EL1], amair_el1);
> + write_sysreg(ctxt->sys_regs[CNTKCTL_EL1], cntkctl_el1);
> + write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1);
>
cpu->arch.debug_ptr),
> guest_ctxt);
> +
> + /* Jump in the fire! */
> + exit_code = __guest_enter(vcpu, host_ctxt);
> + /* And we're baaack! */
> +
> + __sysreg_save_state(guest_ctxt);
> + __sysreg32_save_state(vcpu);
> + __timer_save_state(vcpu);
&
On Tue, Dec 01, 2015 at 12:44:26PM +0100, Christoffer Dall wrote:
> On Tue, Dec 01, 2015 at 11:32:20AM +, Marc Zyngier wrote:
> > On 30/11/15 19:50, Christoffer Dall wrote:
> > > On Fri, Nov 27, 2015 at 06:49:58PM +, Marc Zyngier wrote:
> > >> Implement the vg
On Tue, Dec 01, 2015 at 11:32:20AM +, Marc Zyngier wrote:
> On 30/11/15 19:50, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:49:58PM +, Marc Zyngier wrote:
> >> Implement the vgic-v3 save restore as a direct translation of
> >> the assembly code ve
On Fri, Nov 27, 2015 at 06:50:02PM +, Marc Zyngier wrote:
> Implement the debug save restore as a direct translation of
> the assembly code version.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/hyp/Makefile | 1 +
> arch/arm64/kvm/hyp/debug-sr.c | 130
>
On Tue, Dec 01, 2015 at 09:58:23AM +, Marc Zyngier wrote:
> On 30/11/15 20:33, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:49:54PM +, Marc Zyngier wrote:
> >> Once upon a time, the KVM/arm64 world switch was a nice, clean, lean
> >> and mean piece of
On Tue, Dec 01, 2015 at 11:57:16AM +, Marc Zyngier wrote:
> On 01/12/15 11:50, Christoffer Dall wrote:
> > On Tue, Dec 01, 2015 at 12:44:26PM +0100, Christoffer Dall wrote:
> >> On Tue, Dec 01, 2015 at 11:32:20AM +, Marc Zyngier wrote:
> >>> On 30/11/15
On Tue, Dec 01, 2015 at 11:41:08AM +, Marc Zyngier wrote:
> On 30/11/15 20:00, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:49:56PM +, Marc Zyngier wrote:
> >> In order to expose the various EL2 services that are private to
> >> the hypervisor, add a n
On Tue, Dec 01, 2015 at 01:06:31PM +, Marc Zyngier wrote:
> On 01/12/15 12:56, Christoffer Dall wrote:
> > On Fri, Nov 27, 2015 at 06:50:02PM +, Marc Zyngier wrote:
> >> Implement the debug save restore as a direct translation of
> >> the assembly code ve
On Tue, Dec 01, 2015 at 03:47:37PM +0100, Christoffer Dall wrote:
> On Tue, Dec 01, 2015 at 01:06:31PM +, Marc Zyngier wrote:
> > On 01/12/15 12:56, Christoffer Dall wrote:
> > > On Fri, Nov 27, 2015 at 06:50:02PM +, Marc Zyngier wrote:
> > >> Implement the
On Fri, Nov 27, 2015 at 06:49:58PM +, Marc Zyngier wrote:
> Implement the vgic-v3 save restore as a direct translation of
> the assembly code version.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/hyp/Makefile | 1 +
> arch/arm64/kvm/hyp/hyp.h|
On Fri, Nov 27, 2015 at 06:49:55PM +, Marc Zyngier wrote:
> From: Mark Rutland
>
> Rather than crafting custom macros for reading/writing each system
> register provide generics accessors, read_sysreg and write_sysreg, for
> this purpose.
>
> Unlike read_cpuid, calls
On Fri, Nov 27, 2015 at 06:49:56PM +, Marc Zyngier wrote:
> In order to expose the various EL2 services that are private to
> the hypervisor, add a new hyp.h file.
>
> So far, it only contains mundane things such as section annotation
> and VA manipulation.
>
> Signed-off-by: Marc Zyngier
On Fri, Nov 27, 2015 at 06:49:57PM +, Marc Zyngier wrote:
> Implement the vgic-v2 save restore (mostly) as a direct translation
> of the assembly code version.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/Makefile | 1 +
> arch/arm64/kvm/hyp/Makefile
On Fri, Nov 27, 2015 at 06:49:59PM +, Marc Zyngier wrote:
> Implement the timer save restore as a direct translation of
> the assembly code version.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/kvm/hyp/Makefile | 1 +
> arch/arm64/kvm/hyp/hyp.h
On Fri, Nov 27, 2015 at 06:49:54PM +, Marc Zyngier wrote:
> Once upon a time, the KVM/arm64 world switch was a nice, clean, lean
> and mean piece of hand-crafted assembly code. Over time, features have
> crept in, the code has become harder to maintain, and the smallest
> change is a pain to
by: 84aab5e68c2a5e1e18d81ae8308c3ce25d501b29
(KVM: arm/arm64: arch_timer: Preserve physical dist. active
state on LR.active, 2015-11-24)
Therefore, get rid of the complexities and just look at the LR.
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@l
urphy <robin.mur...@arm.com>
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm64/include/asm/kvm_emulate.h | 8 +---
arch/arm64/kvm/inject_fault.c| 2 +-
2 files changed, 6 insertions(+), 4 deletions(-
was not active, which
shouldn't happen.
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
include/kvm/arm_vgic.h| 2 +-
virt/kvm/arm/arch_timer.c | 28 +---
virt/kvm/arm/vgic.
tually succeeds) by using code patching.
Cc: sta...@vger.kernel.org
Reviewed-by: Will Deacon <will.dea...@arm.com>
Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm64/Kconfig | 21 +
t;ard.biesheu...@linaro.org>
Tested-by: Pavel Fedin <p.fe...@samsung.com>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/kvm/mmu.c | 15 +++
1 file changed, 7 insertions(+), 8 d
_panic to stash the PAR_EL1 value prior to
restoring host register values, enabling us to report the original
values at the point of the panic.
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Christoffer Dall <christ
/arm64: KVM: test properly for a PTE's uncachedness
Christoffer Dall (3):
KVM: arm/arm64: Fix preemptible timer active state crazyness
KVM: arm/arm64: arch_timer: Preserve physical dist. active state on
LR.active
KVM: arm/arm64: vgic: Trust the LR state for HW IRQs
Marc Zyngier (2
tland <mark.rutl...@arm.com>
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm64/kvm/hyp.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
/sync timer functions, simply moving the timer flush into a
non-preemptible section.
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/kvm/arm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --gi
On Mon, Nov 16, 2015 at 10:28:16AM +, Marc Zyngier wrote:
> Here's a couple of fixes for KVM/arm64:
>
> - The first one addresses a misinterpretation of the architecture
> spec, leading to the mishandling of I/O accesses generated from an
> AArch32 guest using banked registers.
>
> - The
simplify the vgic code by just considering the LR state instead of
the GIC physical state on guest return.
Christoffer Dall (3):
KVM: arm/arm64: Fix preemptible timer active state crazyness
KVM: arm/arm64: arch_timer: Preserve physical dist. active state on
LR.active
KVM: arm/arm64: vgic: Trust
by: 84aab5e68c2a5e1e18d81ae8308c3ce25d501b29
(KVM: arm/arm64: arch_timer: Preserve physical dist. active
state on LR.active, 2015-11-24)
Therefore, get rid of the complexities and just look at the LR.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
virt/kvm/arm/vgic.c | 16 ++---
/sync timer functions, simply moving the timer flush into a
non-preemptible section.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/kvm/arm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index e
was not active, which
shouldn't happen.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
include/kvm/arm_vgic.h| 2 +-
virt/kvm/arm/arch_timer.c | 28 +---
virt/kvm/arm/vgic.c | 37 +
3 files changed, 43 inse
On Mon, Nov 09, 2015 at 03:13:15PM -0800, Mario Smarduch wrote:
>
>
> On 11/5/2015 7:02 AM, Christoffer Dall wrote:
> > On Fri, Oct 30, 2015 at 02:56:33PM -0700, Mario Smarduch wrote:
> >> This patch enables arm64 lazy fp/simd switch, similar to arm described in
> &
ed by the host kernel, and only perform the
> D-cache maintenance if this is the case.
>
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> Tested-by: Pavel Fedin <p.fe...@samsung.com>
> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
Tha
On Tue, Nov 10, 2015 at 02:15:45PM +0100, Ard Biesheuvel wrote:
> On 10 November 2015 at 13:22, Christoffer Dall
> <christoffer.d...@linaro.org> wrote:
> > On Tue, Nov 10, 2015 at 10:45:37AM +0100, Ard Biesheuvel wrote:
> >> Hi all,
> >>
> >> I wonder i
On Thu, Nov 05, 2015 at 04:23:41PM -0800, Mario Smarduch wrote:
>
>
> On 11/5/2015 6:48 AM, Christoffer Dall wrote:
> > On Fri, Oct 30, 2015 at 02:56:32PM -0700, Mario Smarduch wrote:
> >> This patch tracks vfp/simd hardware state with a vcpu lazy flag. vCPU lazy
&
On Thu, Nov 05, 2015 at 04:57:12PM -0800, Mario Smarduch wrote:
>
>
> On 11/5/2015 7:02 AM, Christoffer Dall wrote:
> > On Fri, Oct 30, 2015 at 02:56:33PM -0700, Mario Smarduch wrote:
> >> This patch enables arm64 lazy fp/simd switch, similar to arm described in
> &
On Fri, Nov 06, 2015 at 12:32:51PM +0300, Pavel Fedin wrote:
> Hello!
>
> > > diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
> > > index 7b42012..839dd970 100644
> > > --- a/arch/arm/kvm/mmu.c
> > > +++ b/arch/arm/kvm/mmu.c
> > > @@ -213,7 +213,10 @@ static void unmap_ptes(struct kvm *kvm,
mode device mappings
The unmap_ptes function is currently called to unmap both Stage-2 and
Hyp mode page table entries. Since calling clean and invalidate on
device memory may raise exceptions, we currently test against
PAGE_S2_DEVICE and do not flush for such mappings. However, we should
also be testing
On Fri, Oct 30, 2015 at 02:56:32PM -0700, Mario Smarduch wrote:
> This patch tracks vfp/simd hardware state with a vcpu lazy flag. vCPU lazy
> flag is set on guest access and traps to vfp/simd hardware switch handler. On
> vm-enter if lazy flag is set skip trap enable and save host fpexc. On
>
On Fri, Oct 30, 2015 at 02:56:33PM -0700, Mario Smarduch wrote:
> This patch enables arm64 lazy fp/simd switch, similar to arm described in
> second patch. Change from previous version - restore function is moved to
> host.
>
> Signed-off-by: Mario Smarduch
> ---
>
On Wed, Nov 04, 2015 at 07:51:58PM +0100, Ard Biesheuvel wrote:
> On 4 November 2015 at 19:49, Christopher Covington <c...@codeaurora.org>
> wrote:
> > On 11/04/2015 08:31 AM, Christoffer Dall wrote:
> >> On Tue, Nov 03, 2015 at 01:39:44PM -0600, Rob Herring wrote:
>
on the sync path are extremely close to those for
level-triggered interrupts, rename process_level_irq to
process_queued_irq, allowing it to cater for both cases.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
virt/kvm/arm/vgic.c | 40 ++--
, but this case was not supported
before this patch and we leave it for future work for now.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/include/asm/kvm_host.h | 3 --
arch/arm/kvm/arm.c| 10 +
arch/arm64/include/asm/kvm_host.h | 3 --
inclu
forwarding), some tracepoint
improvements, a tweak for the EL2 panic handlers, some more VGIC cleanups
getting rid of redundant state, and finally a stylistic change that gets rid of
some ctags warnings.
Christoffer Dall (10):
KVM: Add kvm_arch_vcpu_{un}blocking callbacks
arm/arm64: KVM
On Tue, Nov 03, 2015 at 12:44:54PM +0300, Pavel Fedin wrote:
> Hello!
>
> > By this time i'll make a very minimal version of patch 0001, for you to
> > test it. If we have
> > problems with current 0001, which we
> > cannot solve quickly, we could stick to that version then, which will
> >
as the reset value to the register.
This is a bit counter-intuitive, as the register is RO for these bits,
and we can just implement it that way, allowing us to control the value
of the bits purely in the reset code.
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffe
:
Also harmless, because now we check the level state in the
clear_soft_pend function and lower the pending bits if the level is
low.
Reviewed-by: Eric Auger <eric.au...@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.
t need any of the other "common" registers in
order to panic successfully.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: <kvm...@lists.cs.columbia.edu>
Signed
we do elsewhere for KVM generic-arch interactions.
Reviewed-by: Marc Zyngier <marc.zyng...@arm.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/include/asm/kvm_host.h | 3 +++
arch/arm64/include/asm/kvm_host.h | 3 +++
arch/mips/include/asm/kvm_h
some s/CPU index/vcpu_index/
in the descriptions. -Christoffer ]
Signed-off-by: Pavel Fedin <p.fe...@samsung.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 18 ++
1 file changed, 10 inserti
Auger <eric.au...@linaro.org>
Reported-by: Christoffer Dall <christoffer.d...@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
arch/arm/kvm/arm.c | 3 ++-
1 file changed, 2 insertions(+), 1
samsung.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
include/kvm/arm_vgic.h | 6 --
virt/kvm/arm/vgic-v2.c | 1 +
virt/kvm/arm/vgic-v3.c | 1 +
virt/kvm/arm/vgic.c| 53 ++
4 files changed, 17 insertions(+),
ng: include/kvm/arm_vgic.h:309: null expansion of name pattern "\1"
ctags: Warning: include/kvm/arm_vgic.h:317: null expansion of name pattern "\1"
Cc: kvm...@lists.cs.columbia.edu
Signed-off-by: Michal Marek <mma...@suse.com>
Signed-off-by: Christoffer Dall <chris
by Marc Zyngier and edited by me.
Omissions and errors are all mine.
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
Documentation/virtual/kvm/arm/vgic-mapped-irqs.txt | 187 +
1 file changed, 187 insertions(+)
create mode 100644 Documentation/virtual/k
an just clearing the LR, move
vgic_irq_clear_queued() inside of it.
Signed-off-by: Pavel Fedin <p.fe...@samsung.com>
Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
---
virt/kvm/arm/vgic.c | 37 ++---
1 file changed, 10 insertions(+), 27 del
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