[PATCH v8 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

From: Shannon Zhao When resetting vcpu, it needs to reset the PMU state to initial status. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/reset.c | 3 +++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 17 + 3 files

[PATCH v8 03/20] KVM: ARM64: Add offset defines for PMU registers

From: Shannon Zhao We are about to trap and emulate accesses to each PMU register individually. This adds the context offsets for the AArch64 PMU registers. Signed-off-by: Shannon Zhao --- arch/arm64/include/asm/kvm_host.h | 15 +++

[PATCH v8 13/20] KVM: ARM64: Add access handler for PMSWINC register

From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +-

[PATCH v8 14/20] KVM: ARM64: Add helper to handle PMCR register bits

From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to

[PATCH v8 02/20] KVM: ARM64: Define PMU data structure for each vcpu

From: Shannon Zhao Here we plan to support virtual PMU for guest by full software emulation, so define some basic structs and functions preparing for futher steps. Define struct kvm_pmc for performance monitor counter and struct kvm_pmu for performance monitor unit for

[PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device

From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 24 + arch/arm64/include/uapi/asm/kvm.h

[PATCH v8 05/20] KVM: ARM64: Add access handler for PMSELR register

From: Shannon Zhao Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for its reset handler. When reading PMSELR, return the PMSELR.SEL field to guest. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 16

[PATCH v8 09/20] KVM: ARM64: Add access handler for event counter register

From: Shannon Zhao These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which is mapped to PMEVCNTRn. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking care of big

[PATCH v8 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

From: Shannon Zhao When KVM frees VCPU, it needs to free the perf_event of PMU. Signed-off-by: Shannon Zhao --- arch/arm/kvm/arm.c| 1 + include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c| 21 + 3 files changed, 24

[PATCH v8 12/20] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register

From: Shannon Zhao Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMOVSSET or PMOVSCLR register. When writing non-zero value to PMOVSSET, the counter and its interrupt is enabled, kick

[RFC v4 5/5] VSOCK: Add Makefile and Kconfig

From: Asias He Enable virtio-vsock and vhost-vsock. Signed-off-by: Asias He Signed-off-by: Stefan Hajnoczi --- v4: * Make checkpatch.pl happy with longer option description * Clarify dependency on virtio rather than QEMU as suggested

[PATCH v8 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

From: Shannon Zhao When we use tools like perf on host, perf passes the event type and the id of this event type category to kernel, then kernel will map them to hardware event number and write this number to PMU PMEVTYPER_EL0 register. When getting the event number in

[PATCH v8 10/20] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register

From: Shannon Zhao Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event.

[PATCH v8 11/20] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

From: Shannon Zhao Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a handler to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao ---

[PATCH v8 06/20] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register

From: Shannon Zhao Add access handler which gets host value of PMCEID0 or PMCEID1 when guest access these registers. Writing action to PMCEID0 or PMCEID1 is UNDEFINED. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 27

[PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

From: Shannon Zhao These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER which is mapped to PMEVTYPERn or PMCCFILTR. The access handler translates all aarch32 register offsets to aarch64 ones and uses vcpu_sys_reg() to access their values to avoid taking

[RFC v4 2/5] VSOCK: Introduce virtio_vsock_common.ko

From: Asias He This module contains the common code and header files for the following virtio_transporto and vhost_vsock kernel modules. Signed-off-by: Asias He Signed-off-by: Stefan Hajnoczi --- v4: * Add MAINTAINERS file entry *

RE: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

Hello! > > 1. Is there any real need to distinguish between KVM_EXIT_MSR_WRITE and > KVM_EXIT_MSR_AFTER_WRITE ? IMHO from userland's point of view these are the > same. > > Indeed. Perhaps the kernel can set .handled to true to let userspace > know it already took care of it, instead of

Re: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

On Tue, Dec 22, 2015 at 10:24:13AM +0300, Pavel Fedin wrote: > > +On the return path into kvm, user space should set handled to > > +KVM_EXIT_MSR_HANDLED if it successfully handled the MSR access. Otherwise, > > +handled should be set to KVM_EXIT_MSR_UNHANDLED, which will cause a general > >

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Tue, Dec 22, 2015 at 02:14:12AM +, Gonglei (Arei) wrote: > > From: Kevin O'Connor [mailto:ke...@koconnor.net] > > Sent: Tuesday, December 22, 2015 2:47 AM > > To: Gonglei (Arei) > > Cc: Xulei (Stone); Paolo Bonzini; qemu-devel; seab...@seabios.org; > > Huangweidong (C); kvm@vger.kernel.org;

[RFC 0/2] VFIO SRIOV support

Today the QEMU hypervisor allows assigning a physical device to a VM, facilitating driver development. However, it does not support enabling SR-IOV by the VM kernel driver. Our goal is to implement such support, allowing developers working on SR-IOV physical function drivers to work inside VMs as

[RFC 2/2] VFIO: Add support for SRIOV extended capablity

Add support for PCIE SRIOV extended capablity with following features: 1. The ability to probe SRIOV BAR sizes. 2. The ability to enable and disable sriov. Signed-off-by: Ilya Lesokhin Signed-off-by: Noa Osherovich Signed-off-by: Haggai Eran

[RFC 1/2] PCI: Expose iov_set_numvfs and iov_resource_size for modules.

Expose iov_set_numvfs and iov_resource_size to make them available for VFIO-PCI sriov support. Signed-off-by: Ilya Lesokhin Signed-off-by: Noa Osherovich Signed-off-by: Haggai Eran --- drivers/pci/iov.c | 4 +++-

Re: [PATCH 1/2] arm: KVM: Do not update PC if the trap handler has updated it

On Tue, Dec 22, 2015 at 11:08:10AM +, Peter Maydell wrote: > On 22 December 2015 at 09:55, Marc Zyngier wrote: > > Assuming we trap a coprocessor access, and decide that the access > > is illegal, we will inject an exception in the guest. In this > > case, we shouldn't

[PATCH 0/2] kvmtool: replace documentations stubs with manpage

Hi, as I got annoyed with the availability and quality of the documentation and always wanted to write a manpage, I just took this first step by replacing the stub text files in the Documentation directory with a manpage. This is clearly only the beginning, there is more functionality which

[PATCH 2/2] Documentation: remove documentation stubs and common-cmds.h generation

Now that we have a manpage in place, we can get rid of the manpage style text files in the Documentation directory. This allows us also to get rid of the crude common-cmds.h generation, which relied on these files and on a command-list.txt file. Instead include the version of that header file

[PATCH 1/2] Add a rudimentary manpage

The kvmtool documentation is somewhat lacking, also it is not easily accessible when living in the source tree only. Add a good ol' manpage to document at least the basic commands and their options. This level of documentation matches the one that is already there in the Documentation directory

Re: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

On Tue, Dec 22, 2015 at 03:51:52PM +0300, Pavel Fedin wrote: > Hello! > > > > 1. Is there any real need to distinguish between KVM_EXIT_MSR_WRITE and > > KVM_EXIT_MSR_AFTER_WRITE ? IMHO from userland's point of view these are the > > same. > > > > Indeed. Perhaps the kernel can set .handled

[GIT PULL] KVM fixes for v4.4-rc7

Linus, The following changes since commit 6764e5ebd5c62236d082f9ae030674467d0b2779: Merge tag 'vfio-v4.4-rc5' of git://github.com/awilliam/linux-vfio (2015-12-09 16:52:12 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus for you

Re: [PATCH 1/2] arm: KVM: Do not update PC if the trap handler has updated it

On 22 December 2015 at 14:39, Christoffer Dall wrote: > On Tue, Dec 22, 2015 at 11:08:10AM +, Peter Maydell wrote: >> Won't this result in our incorrectly skipping the first insn >> in the fault handler if the original offending instruction >> was itself the first

[PATCH v3] vfio: Include No-IOMMU mode

There is really no way to safely give a user full access to a DMA capable device without an IOMMU to protect the host system. There is also no way to provide DMA translation, for use cases such as device assignment to virtual machines. However, there are still those users that want userspace

Re: [kvm-unit-tests PATCH 1/3] run_tests.sh: reduce return code ambiguity

2015-12-21 13:35-0600, Andrew Jones: > On Mon, Dec 21, 2015 at 05:31:24PM +0100, Radim Krčmář wrote: > > 2015-12-17 14:10-0600, Andrew Jones: >> > 128 = exited because of signal $? - 128 >> * = unit-test failed >> >> (Signal 0 is not used, so we could map 128 to mean "debug-exit probably >>

[PATCH v4] vfio: Include No-IOMMU mode

There is really no way to safely give a user full access to a DMA capable device without an IOMMU to protect the host system. There is also no way to provide DMA translation, for use cases such as device assignment to virtual machines. However, there are still those users that want userspace

RE: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

Hello! > It has: unlike the scenario that was the original motivation for Peter's > patches, where the the userspace wanted to handle register accesses > which the kernel *didn't*, in case of SynIC the userspace wants do > something about MSR accesses *only* if the kernel *also* handles them.

Re: [kvm-unit-tests PATCH 1/3] run_tests.sh: reduce return code ambiguity

On Mon, Dec 21, 2015 at 05:31:24PM +0100, Radim Krčmář wrote: > 2015-12-17 14:10-0600, Andrew Jones: > > qemu/unittest exit codes are convoluted, causing codes 0 and 1 > > to be ambiguous. Here are the possible meanings > > > > .-.

Re: [kvm-unit-tests PATCH 3/3] add timeout support

On Mon, Dec 21, 2015 at 06:04:20PM +0100, Radim Krčmář wrote: > 2015-12-17 14:10-0600, Andrew Jones: > > Signed-off-by: Andrew Jones > > --- > > diff --git a/arm/run b/arm/run > > @@ -75,10 +75,14 @@ chr_testdev+=' -device virtconsole,chardev=ctd -chardev > > testdev,id=ctd'

Re: [PATCH v5 3/3] KVM/arm/arm64: enable enhanced armv8 fp/simd lazy switch

On 12/18/2015 11:45 PM, Christoffer Dall wrote: > On Fri, Dec 18, 2015 at 05:17:00PM -0800, Mario Smarduch wrote: >> On 12/18/2015 5:54 AM, Christoffer Dall wrote: >>> On Sun, Dec 06, 2015 at 05:07:14PM -0800, Mario Smarduch wrote: This patch tracks armv7 and armv8 fp/simd hardware state

Re: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

On Fri, Dec 18, 2015 at 1:25 PM, Paolo Bonzini wrote: > > > On 18/08/2015 20:46, Peter Hornyack wrote: >> Define KVM_EXIT_MSR, a new exit reason for accesses to MSRs that kvm >> does not handle. Define KVM_CAP_UNHANDLED_MSR_EXITS, a vm-wide >> capability that guards the new

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Mon, Dec 21, 2015 at 09:41:32AM +, Gonglei (Arei) wrote: > When the gurb of OS is booting, then the softirq and C function send_disk_op() > may use extra stack of SeaBIOS. If we inject a NMI, romlayout.S: > irqentry_extrastack > is invoked, and the extra stack will be used again. And the

Re: [PATCH v3 9/9] KVM: PPC: Book3S HV: Add tunable to control H_IPI redirection

Redirecting the wakeup of a VCPU from the H_IPI hypercall to a core running in the host is usually a good idea, most workloads seemed to benefit. However, in one heavily interrupt-driven SMT1 workload, some regression was observed. This patch adds a kvm_hv module parameter called h_ipi_redirect to

Re: kvmclock doesn't work, help?

On Fri, Dec 18, 2015 at 1:49 PM, Marcelo Tosatti wrote: > On Fri, Dec 18, 2015 at 12:25:11PM -0800, Andy Lutomirski wrote: >> [cc: John Stultz -- maybe you have ideas on how this should best >> integrate with the core code] >> >> On Fri, Dec 18, 2015 at 11:45 AM, Marcelo

[PATCH v2 01/14] qapi: Rename (one) qjson.h to qobject-json.h

We have two different JSON visitors in the tree; and having both named 'qjson.h' can cause include confusion. Rename the qapi version. Why did I pick that one? A later patch plans on deleting the top-level qjson.c once we have a native JSON output visitor; we could have renamed that one for

Re: [PATCH v3 8/9] KVM: PPC: Book3S HV: Send IPI to host core to wake VCPU

This patch adds support to real-mode KVM to search for a core running in the host partition and send it an IPI message with VCPU to be woken. This avoids having to switch to the host partition to complete an H_IPI hypercall when the VCPU which is the target of the the H_IPI is not loaded (is not

RE: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

Dear Kevin, > -Original Message- > From: Kevin O'Connor [mailto:ke...@koconnor.net] > Sent: Sunday, December 20, 2015 10:33 PM > To: Gonglei (Arei) > Cc: Xulei (Stone); Paolo Bonzini; qemu-devel; seab...@seabios.org; > Huangweidong (C); kvm@vger.kernel.org; Radim Krcmar > Subject: Re:

RE: [PATCH v4 5/5] kvm/x86: Hyper-V kvm exit

Hello! > Yes, we can use KVM_EXIT_REG_IO/MSR_IO for Hyper-V SynIC MSRS's changes > and can even use only one MSR value . So union inside struct > kvm_hyperv_exit is excessive. > > But we still need Vcpu exit to handle VMBus hypercalls by QEMU to > emulate VMBus devices inside QEMU. > > And

Re: [PATCH v9 0/5] implement vNVDIMM

On 12/10/2015 11:11 AM, Xiao Guangrong wrote: New version, new week, and unfortunate new ping... :( Ping again to see what happened... -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at

Re: [PATCH v4 5/5] kvm/x86: Hyper-V kvm exit

On 12/21/2015 04:28 PM, Pavel Fedin wrote: Hello! Yes, we can use KVM_EXIT_REG_IO/MSR_IO for Hyper-V SynIC MSRS's changes and can even use only one MSR value . So union inside struct kvm_hyperv_exit is excessive. But we still need Vcpu exit to handle VMBus hypercalls by QEMU to emulate

Re: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

On 2015/12/22 12:37, Wu, Feng wrote: -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- ow...@vger.kernel.org] On Behalf Of Yang Zhang Sent: Monday, December 21, 2015 10:06 AM To: Wu, Feng ; pbonz...@redhat.com; rkrc...@redhat.com Cc:

Re: RE: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

Hi, Kevin, Can you tell how to reset/reboot this VM, if it goes to the handle_hwpic1() on its booting procedure? I mean, usually, SeaBIOS would not go to handle_hwpic routine. But in my test case, SeaBIOS calls handle_hwpic when KVM injects a #UD expcetion (not irq) and SeaBIOS will loop to

Re: [PATCH v2 2/2] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

On 2015/12/22 12:36, Wu, Feng wrote: -Original Message- From: Yang Zhang [mailto:yang.zhang...@gmail.com] Sent: Monday, December 21, 2015 10:01 AM To: Wu, Feng ; pbonz...@redhat.com; rkrc...@redhat.com Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org Subject:

RE: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

> -Original Message- > From: Kevin O'Connor [mailto:ke...@koconnor.net] > Sent: Tuesday, December 22, 2015 2:47 AM > To: Gonglei (Arei) > Cc: Xulei (Stone); Paolo Bonzini; qemu-devel; seab...@seabios.org; > Huangweidong (C); kvm@vger.kernel.org; Radim Krcmar > Subject: Re: [Qemu-devel]

RE: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Yang Zhang > Sent: Monday, December 21, 2015 10:06 AM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org;

RE: [PATCH v2 2/2] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

> -Original Message- > From: Yang Zhang [mailto:yang.zhang...@gmail.com] > Sent: Monday, December 21, 2015 10:01 AM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org > Subject: Re: [PATCH v2 2/2] KVM:

RE: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

Hi Radim/Paolo, > -Original Message- > From: Yang Zhang [mailto:yang.zhang...@gmail.com] > Sent: Tuesday, December 22, 2015 3:14 PM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org; Jiang Liu >

Re: [PATCH kernel 7/9] KVM: PPC: Move reusable bits of H_PUT_TCE handler to helpers

On 12/08/2015 04:27 PM, David Gibson wrote: On Tue, Sep 15, 2015 at 08:49:37PM +1000, Alexey Kardashevskiy wrote: Upcoming multi-tce support (H_PUT_TCE_INDIRECT/H_STUFF_TCE hypercalls) will validate TCE (not to have unexpected bits) and IO address (to be within the DMA window boundaries). This

Re: [PATCH kernel 7/9] KVM: PPC: Move reusable bits of H_PUT_TCE handler to helpers

On 12/08/2015 04:27 PM, David Gibson wrote: On Tue, Sep 15, 2015 at 08:49:37PM +1000, Alexey Kardashevskiy wrote: Upcoming multi-tce support (H_PUT_TCE_INDIRECT/H_STUFF_TCE hypercalls) will validate TCE (not to have unexpected bits) and IO address (to be within the DMA window boundaries). This

RE: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

> -Original Message- > From: Yang Zhang [mailto:yang.zhang...@gmail.com] > Sent: Tuesday, December 22, 2015 2:49 PM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org; Jiang Liu >

Re: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

On 2015/12/22 14:59, Wu, Feng wrote: -Original Message- From: Yang Zhang [mailto:yang.zhang...@gmail.com] Sent: Tuesday, December 22, 2015 2:49 PM To: Wu, Feng ; pbonz...@redhat.com; rkrc...@redhat.com Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org; Jiang Liu

Re: [PATCH kernel 9/9] KVM: PPC: Add support for multiple-TCE hcalls

On 12/08/2015 04:48 PM, David Gibson wrote: On Tue, Sep 15, 2015 at 08:49:39PM +1000, Alexey Kardashevskiy wrote: This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO devices or emulated PCI. These calls

Re: [PATCH kernel 9/9] KVM: PPC: Add support for multiple-TCE hcalls

On 12/08/2015 04:48 PM, David Gibson wrote: On Tue, Sep 15, 2015 at 08:49:39PM +1000, Alexey Kardashevskiy wrote: This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO devices or emulated PCI. These calls

RE: [RFC PATCH 2/5] KVM: add KVM_EXIT_MSR exit reason and capability.

Hello! > commit a684d520ed62cf0db4495e5197d5bf722e4f8109 > Author: Peter Hornyack > Date: Fri Dec 18 14:44:04 2015 -0800 > > KVM: add capabilities and exit reasons for MSRs. > > Define KVM_EXIT_MSR_READ, KVM_EXIT_MSR_WRITE, and >

Re: kvmclock doesn't work, help?

On Fri, Dec 18, 2015 at 12:25:11PM -0800, Andy Lutomirski wrote: > [cc: John Stultz -- maybe you have ideas on how this should best > integrate with the core code] > > On Fri, Dec 18, 2015 at 11:45 AM, Marcelo Tosatti wrote: > > On Fri, Dec 18, 2015 at 11:27:13AM -0800, Andy

Re: [PATCH v4 5/5] kvm/x86: Hyper-V kvm exit

On 12/18/2015 09:39 PM, Roman Kagan wrote: On Fri, Dec 18, 2015 at 10:10:11AM -0800, Peter Hornyack wrote: On Fri, Dec 18, 2015 at 8:01 AM, Paolo Bonzini wrote: On 18/12/2015 16:19, Pavel Fedin wrote: As far as i understand this code, KVM_EXIT_HYPERV is called when one

Re: [kvm-unit-tests PATCH 1/3] run_tests.sh: reduce return code ambiguity

2015-12-17 14:10-0600, Andrew Jones: > qemu/unittest exit codes are convoluted, causing codes 0 and 1 > to be ambiguous. Here are the possible meanings > > .-. > || 0 | 1 | >

Re: [kvm-unit-tests PATCH 3/3] add timeout support

2015-12-17 14:10-0600, Andrew Jones: > Signed-off-by: Andrew Jones > --- > diff --git a/arm/run b/arm/run > @@ -75,10 +75,14 @@ chr_testdev+=' -device virtconsole,chardev=ctd -chardev > testdev,id=ctd' > M+=",accel=$ACCEL" > command="$qemu $M -cpu $processor $chr_testdev" >

RE: [PATCH v4 5/5] kvm/x86: Hyper-V kvm exit

Hello! > > It depends. Can i read about these hypercalls somewhere? Is there any > > documentation? > I don't know about a documentation, but you can look at the code of > Hyper-V hypercall handling inside KVM: > > https://github.com/torvalds/linux/blob/master/arch/x86/kvm/hyperv.c#L346

RE: [PATCH v2 2/2] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

> -Original Message- > From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- > ow...@vger.kernel.org] On Behalf Of Yang Zhang > Sent: Monday, December 21, 2015 9:50 AM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org;

Re: [PATCH v2 2/2] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

On 2015/12/21 9:55, Wu, Feng wrote: -Original Message- From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel- ow...@vger.kernel.org] On Behalf Of Yang Zhang Sent: Monday, December 21, 2015 9:50 AM To: Wu, Feng ; pbonz...@redhat.com; rkrc...@redhat.com Cc:

Re: [PATCH kernel] vfio: Add explicit alignments in vfio_iommu_spapr_tce_create

On Fri, Dec 18, 2015 at 12:35:47PM +1100, Alexey Kardashevskiy wrote: > The vfio_iommu_spapr_tce_create struct has 4x32bit and 2x64bit fields > which should have resulted in sizeof(fio_iommu_spapr_tce_create) equal > to 32 bytes. However due to the gcc's default alignment, the actual > size of

Re: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

On 2015/12/16 9:37, Feng Wu wrote: Use vector-hashing to deliver lowest-priority interrupts, As an example, modern Intel CPUs in server platform use this method to handle lowest-priority interrupts. Signed-off-by: Feng Wu --- arch/x86/kvm/irq_comm.c | 27

Re: [PATCH v2 2/2] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

On 2015/12/16 9:37, Feng Wu wrote: Use vector-hashing to deliver lowest-priority interrupts for VT-d posted-interrupts. Signed-off-by: Feng Wu --- arch/x86/kvm/lapic.c | 67 arch/x86/kvm/lapic.h | 2 ++

Re: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

On 2015/12/21 9:50, Wu, Feng wrote: -Original Message- From: Yang Zhang [mailto:yang.zhang...@gmail.com] Sent: Monday, December 21, 2015 9:46 AM To: Wu, Feng ; pbonz...@redhat.com; rkrc...@redhat.com Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org Subject: Re:

RE: [PATCH v2 1/2] KVM: x86: Use vector-hashing to deliver lowest-priority interrupts

> -Original Message- > From: Yang Zhang [mailto:yang.zhang...@gmail.com] > Sent: Monday, December 21, 2015 9:46 AM > To: Wu, Feng ; pbonz...@redhat.com; > rkrc...@redhat.com > Cc: kvm@vger.kernel.org; linux-ker...@vger.kernel.org > Subject: Re: [PATCH v2 1/2] KVM: x86:

RE: [PATCH v4 5/5] kvm/x86: Hyper-V kvm exit

Hello! Replying to everything in one message. > > As far as i understand this code, KVM_EXIT_HYPERV is called when one > > of three MSRs are accessed. But, shouldn't we have implemented > > instead something more generic, like KVM_EXIT_REG_IO, which would > > work similar to KVM_EXIT_PIO or

[PATCH v2 3/4] x86/vdso: Remove pvclock fixmap machinery

Acked-by: Paolo Bonzini Signed-off-by: Andy Lutomirski --- arch/x86/entry/vdso/vclock_gettime.c | 1 - arch/x86/entry/vdso/vma.c| 1 + arch/x86/include/asm/fixmap.h| 5 - arch/x86/include/asm/pvclock.h | 5 -

[PATCH v2 2/4] x86/vdso: Get pvclock data from the vvar VMA instead of the fixmap

Acked-by: Paolo Bonzini Signed-off-by: Andy Lutomirski --- arch/x86/entry/vdso/vclock_gettime.c | 20 arch/x86/entry/vdso/vdso-layout.lds.S | 3 ++- arch/x86/entry/vdso/vdso2c.c | 3 +++ arch/x86/entry/vdso/vma.c

[PATCH v2 0/4] x86: KVM vdso and clock improvements

x86: KVM vdso and clock improvements NB: patch 1 doesn't really belong here, but it makes this a lot easier for me to test. Patch 1, if it's okay at all, should go though the kvm tree. The rest should probably go through tip:x86/vdso once they're reviewed. I'll do a followup to enable vdso

[PATCH v2 1/4] x86, vdso, pvclock: Simplify and speed up the vdso pvclock reader

From: Andy Lutomirski The pvclock vdso code was too abstracted to understand easily and excessively paranoid. Simplify it for a huge speedup. This opens the door for additional simplifications, as the vdso no longer accesses the pvti for any vcpu other than vcpu 0.

[PATCH v2 4/4] x86/vdso: Enable vdso pvclock access on all vdso variants

Now that pvclock doesn't require access to the fixmap, all vdso variants can use it. The kernel side isn't wired up for 32-bit kernels yet, but this covers 32-bit and x32 userspace on 64-bit kernels. Acked-by: Paolo Bonzini Signed-off-by: Andy Lutomirski

RE: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

> -Original Message- > From: Kevin O'Connor [mailto:ke...@koconnor.net] > Sent: Saturday, December 19, 2015 11:12 PM > On Sat, Dec 19, 2015 at 12:03:15PM +, Gonglei (Arei) wrote: > > Maybe the root cause is not NMI but INTR, so yield() can open hardware > interrupt, > > And then

[PULL] vhost: cleanups and fixes

The following changes since commit 9f9499ae8e6415cefc4fe0a96ad0e27864353c89: Linux 4.4-rc5 (2015-12-13 17:42:58 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git tags/for_linus for you to fetch changes up to

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Sun, Dec 20, 2015 at 09:49:54AM +, Gonglei (Arei) wrote: > > From: Kevin O'Connor [mailto:ke...@koconnor.net] > > Sent: Saturday, December 19, 2015 11:12 PM > > On Sat, Dec 19, 2015 at 12:03:15PM +, Gonglei (Arei) wrote: > > > Maybe the root cause is not NMI but INTR, so yield() can

RE: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

Hi Kevin, > -Original Message- > From: Kevin O'Connor [mailto:ke...@koconnor.net] > > On Fri, Dec 18, 2015 at 03:04:58AM +, Gonglei (Arei) wrote: > > Hi Kevin & Paolo, > > > > Luckily, I reproduced this problem last night. And I got the below log when > SeaBIOS is stuck. > [...] > >

Happy Christmas

B2B有效询盘越来越少，参展价格太高，坐等客户工作消极？ 您想试试主动出击开发属于您的单独优质客户询盘吗？ 您可以尝试将您的老客户在互联网上搜索发现都可以搜索到的。 外贸客户搜索与开发软件对特定行业，在搜索引擎上面搜索有一定历史的公司企业网站，拉取目标客户信息。联系真正高质量的终端客户，外贸客户开发系统帮助外贸企业，soho，外贸业务员降低客户开发门槛，不浪费时间在垃圾询盘身上。 详情咨询Q--Q:2036019519

Re: [Qemu-devel] [PATCH] SeaBios: Fix reset procedure reentrancy problem on qemu-kvm platform

On Sat, Dec 19, 2015 at 12:03:15PM +, Gonglei (Arei) wrote: > Maybe the root cause is not NMI but INTR, so yield() can open hardware > interrupt, > And then execute interrupt handler, but the interrupt handler make the SeaBIOS > stack broken, so that the BSP can't execute the instruction and

[PATCH] KVM: x86: MMU: Use clear_page() instead of init_shadow_page_table()

Not just in order to clean up the code, but to make it faster by using enhanced instructions: the initialization became 20-30% faster on our testing machine. Signed-off-by: Takuya Yoshikawa --- arch/x86/kvm/mmu.c | 10 +- 1 file changed, 1

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On Thu, Dec 17, 2015 at 03:22:50PM +0800, Shannon Zhao wrote: > > > On 2015/12/17 4:33, Christoffer Dall wrote: > > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: > >> Hi, > >> > >> On 2015/12/16 15:31, Shannon Zhao wrote: > > But in this case, you're returning an error if

RE: [RFC PATCH 3/3] vfio-pci: Allow to mmap MSI-X table if EEH is supported

From: Alex Williamson > Sent: 17 December 2015 21:07 ... > > Is this all related to the statements in the PCI(e) spec that the > > MSI-X table and Pending bit array should in their own BARs? > > (ISTR it even suggests a BAR each.) > > > > Since the MSI-X table exists in device memory/registers

Re: [RFC PATCH 2/3] vfio-pci: Allow to mmap sub-page MMIO BARs if all MMIO BARs are page aligned

On 2015/12/18 5:46, Alex Williamson wrote: On Thu, 2015-12-17 at 18:26 +0800, yongji xie wrote: On 2015/12/17 4:04, Alex Williamson wrote: On Fri, 2015-12-11 at 16:53 +0800, Yongji Xie wrote: Current vfio-pci implementation disallows to mmap sub-page(size < PAGE_SIZE) MMIO BARs because

Re: [PATCH kvm-unit-tests v2 01/12] run_tests: move run() to scripts/

2015-12-17 12:45-0600, Andrew Jones: > On Thu, Dec 17, 2015 at 06:53:32PM +0100, Radim Krčmář wrote: >> We'll be using it from scripts/mkstandalone later. >> >> Signed-off-by: Radim Krčmář >> --- >> v2: new >> >> run_tests.sh | 53

[PATCH v4 2/7] mips/kvm: Implement PRid CP0 register

Implement saving and restoring to KVM state of the Processor ID (PRid) CP0 register. This allows QEMU to control the PRid exposed to the guest instead of using the default set by KVM. Signed-off-by: James Hogan Reviewed-by: Leon Alrae Cc: Paolo

[PATCH v4 6/7] mips/kvm: Support FPU in MIPS KVM guests

Support the new KVM_CAP_MIPS_FPU capability, which allows the host's FPU to be exposed to the KVM guest. The capability is enabled if the guest core has an FPU according to its Config1 register. Various config bits are now writeable so that KVM is aware of the configuration (Config1.FP) and so

[PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests

Support the new KVM_CAP_MIPS_MSA capability, which allows MIPS SIMD Architecture (MSA) to be exposed to the KVM guest. The capability is enabled if the guest core has MSA according to its Config3 register. Various config bits are now writeable so that KVM is aware of the configuration

[PATCH v4 5/7] mips/kvm: Support signed 64-bit KVM registers

Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64() since they take an int64_t pointer, and add separate signed 64-bit accessors. These will be used for double precision floating point registers. Signed-off-by: James Hogan Cc: Paolo Bonzini

[PATCH v4 0/7] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests

Here's a v4 refresh of my FPU/MSA patchset for v2.6. Thanks to all who have taken the time to review it so far. This patchset primarily adds support for FPU and MIPS SIMD Architecture (MSA) in MIPS KVM guests to QEMU. It depends on Linux v4.1, specifically my KVM patchset to add the corresponding

[PATCH v4 4/7] mips/kvm: Support unsigned KVM registers

Add KVM register access functions for the uint32_t type. This is required for FP and MSA control registers, which are represented as unsigned 32-bit integers. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: Leon Alrae Cc:

[PATCH v4 1/7] mips/kvm: Remove a couple of noisy DPRINTFs

The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run() are particularly noisy during normal execution, and also not particularly helpful. Remove them so that more important debug messages can be more easily seen. Signed-off-by: James Hogan Reviewed-by:

[PATCH v4 3/7] mips/kvm: Implement Config CP0 registers

Implement saving and restoring to KVM state of the Config CP0 registers (namely Config, Config1, Config2, Config3, Config4, and Config5). These control the features available to a guest, and a few of the fields will soon be writeable by a guest so QEMU needs to know about them so as not to clobber

Re: [PATCH kvm-unit-tests v2 02/12] run_tests: prepare for changes in scripts/mkstandalone

2015-12-17 12:53-0600, Andrew Jones: > On Thu, Dec 17, 2015 at 06:53:33PM +0100, Radim Krčmář wrote: >> mkstandalone has a different mechanism for running tests as well as a >> different handling of output and return codes. >> - create two shell function to capture test execution and logging >>

Re: [PATCH kvm-unit-tests v2 03/12] scripts/mkstandalone: use common run function

2015-12-17 13:09-0600, Andrew Jones: > On Thu, Dec 17, 2015 at 06:53:34PM +0100, Radim Krčmář wrote: >> The biggest change is dependency on bash. An alternative would be to >> rewrite `run` in POSIX shell, but I think it's ok to presume that KVM >> unit tests will run on a system where installing

<    1   2   3   4   5   6   7   8   9   10   >