On Tue, Aug 09, 2011 at 10:20:27AM +0100, Avi Kivity wrote:
> On 08/06/2011 01:39 PM, Christoffer Dall wrote:
> > Adds support in the identity mapping feature that allows KVM to setup
> > identity mapping for the Hyp mode with the AP[1] bit set as required by
> > the specification and also supports
On 30 November 2011 11:39, Stefano Stabellini
wrote:
> A git branch is available here (not ready for submission):
>
> git://xenbits.xen.org/people/sstabellini/linux-pvhvm.git arm
>
> the branch above is based on git://linux-arm.org/linux-2.6.git arm-lpae,
> even though guests don't really need lpa
On Thu, Dec 01, 2011 at 10:26:37AM +, Ian Campbell wrote:
> On Wed, 2011-11-30 at 18:32 +, Stefano Stabellini wrote:
> > On Wed, 30 Nov 2011, Arnd Bergmann wrote:
> > > KVM and Xen at least both fall into the single-return-value category,
> > > so we should be able to agree on a calling con
On Thu, Dec 01, 2011 at 03:42:19PM +, Arnd Bergmann wrote:
> On Thursday 01 December 2011, Catalin Marinas wrote:
> > Given the way register banking is done on AArch64, issuing an HVC on a
> > 32-bit guest OS doesn't require translation on a 64-bit hypervisor. W
On Thu, Dec 01, 2011 at 04:44:40PM +, Arnd Bergmann wrote:
> On Thursday 01 December 2011, Catalin Marinas wrote:
> > On Thu, Dec 01, 2011 at 03:42:19PM +, Arnd Bergmann wrote:
> > > On Thursday 01 December 2011, Catalin Marinas wrote:
> > > How do you deal wi
On Fri, Jun 10, 2011 at 09:40:34AM +0100, Christoffer Dall wrote:
> OK, so I looked into compiling KVM/ARM as a module and there are a few
> obstacles:
>
> I need to export several symbols (identitiy_mapping_add,
> pgd_clear_bad, __irq_svc). __irq_svc is tricky because it's in the
> entry-armv.S a
On Fri, Jun 10, 2011 at 10:53:06AM +0100, Alexander Graf wrote:
> Am 10.06.2011 um 11:23 schrieb Catalin Marinas :
> > On Fri, Jun 10, 2011 at 09:40:34AM +0100, Christoffer Dall wrote:
> >> OK, so I looked into compiling KVM/ARM as a module and there are a few
> >> obst
On Tue, Mar 26, 2013 at 05:00:56PM +, Marc Zyngier wrote:
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -24,6 +24,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -239,18 +240,18 @@ ENDPROC(el1_error_invalid)
> el1_
On Tue, Mar 26, 2013 at 05:00:57PM +, Marc Zyngier wrote:
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -44,6 +44,7 @@ struct page *empty_zero_page;
> EXPORT_SYMBOL(empty_zero_page);
>
> pgprot_t pgprot_default;
> +pgprot_t pgprot_device;
> EXPORT_SYMBOL(pgprot_default);
>
On Mon, Apr 08, 2013 at 05:17:04PM +0100, Marc Zyngier wrote:
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
> b/arch/arm64/include/asm/pgtable-hwdef.h
> index 75fd13d..acb4ee5 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -68,6 +6
On Mon, Apr 08, 2013 at 05:17:09PM +0100, Marc Zyngier wrote:
> +static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long
> addr)
> +{
> + unsigned long cpsr = *vcpu_cpsr(vcpu);
> + int is_aarch32;
> + u32 esr = 0;
> +
> + is_aarch32 = vcpu_mode_is_32bit(vcpu);
On Mon, Apr 08, 2013 at 05:17:10PM +0100, Marc Zyngier wrote:
> diff --git a/arch/arm64/include/asm/kvm_mmu.h
> b/arch/arm64/include/asm/kvm_mmu.h
> new file mode 100644
> index 000..2eb2230
> --- /dev/null
> +++ b/arch/arm64/include/asm/kvm_mmu.h
...
> +/*
> + * Align KVM with the kernel's vi
On Mon, Apr 08, 2013 at 05:17:18PM +0100, Marc Zyngier wrote:
> Provide EL2 with page tables and stack, and set the vectors
> to point to the full blown world-switch code.
>
> Signed-off-by: Marc Zyngier
> ---
> arch/arm64/include/asm/kvm_host.h | 13 +
> arch/arm64/kvm/hyp-init.S |
On Wed, Apr 24, 2013 at 12:43:21PM +0100, Marc Zyngier wrote:
> On 24/04/13 00:00, Christoffer Dall wrote:
> > On Mon, Apr 08, 2013 at 05:17:21PM +0100, Marc Zyngier wrote:
> >> Add support for the in-kernel GIC emulation. The include file
> >> is a complete duplicate of the 32bit one - something t
On Thu, May 02, 2013 at 03:39:00PM +0100, Marc Zyngier wrote:
> Patch 5a677ce044f1 (ARM: KVM: switch to a dual-step HYP init code)
> introduced code that flushes page tables to the point of coherency.
> This is overkill (point of unification is enough and already done),
> and actually not required
On Thu, May 02, 2013 at 03:38:58PM +0100, Marc Zyngier wrote:
> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
> index f7793df..9e2d906c 100644
> --- a/arch/arm/kvm/interrupts.S
> +++ b/arch/arm/kvm/interrupts.S
...
> -static void clear_pte_entry(pte_t *pte)
> +static void clear
On Wed, Apr 24, 2013 at 12:43:51PM +0100, Marc Zyngier wrote:
> On 24/04/13 00:00, Christoffer Dall wrote:
> > On Mon, Apr 08, 2013 at 05:17:22PM +0100, Marc Zyngier wrote:
> >> Add support for the in-kernel timer emulation. The include file
> >> is a complete duplicate of the 32bit one - something
On Mon, Apr 08, 2013 at 05:17:26PM +0100, Marc Zyngier wrote:
> static inline bool kvm_vcpu_reg_is_pc(const struct kvm_vcpu *vcpu, int reg)
> {
> - return false;
> + return (vcpu_mode_is_32bit(vcpu)) && reg == 15;
> }
On AArch64, would ESR_EL2 have SRT == 15 when the source/destination
On Mon, Apr 08, 2013 at 05:17:02PM +0100, Marc Zyngier wrote:
> This series contains the third version of KVM for arm64.
>
> It depends on the following branches/series:
> - git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64.git
> soc-armv8-model
> Catalin's platform support b
On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> On 02/05/13 17:09, Catalin Marinas wrote:
> > BTW, on arch/arm it looks like this is used when you get a data abort
> > with PC as the destination register and you inject a prefetch abort in
> > this case. Why isn
On Sat, May 11, 2013 at 01:36:30AM +0100, Christoffer Dall wrote:
> On Tue, May 07, 2013 at 05:33:03PM +0100, Catalin Marinas wrote:
> > On Tue, May 07, 2013 at 05:28:00PM +0100, Marc Zyngier wrote:
> > > On 02/05/13 17:09, Catalin Marinas wrote:
> > > > BTW, on arch/
Hi Gleb,
On Sun, May 12, 2013 at 10:03:59AM +0100, Gleb Natapov wrote:
> On Fri, May 03, 2013 at 04:55:01PM +0100, Marc Zyngier wrote:
> > On 03/05/13 16:31, Anup Patel wrote:
> > > On Fri, May 3, 2013 at 7:32 PM, Marc Zyngier wrote:
> > >> As KVM/arm64 is looming on the horizon, it makes sense t
For arm64:
Acked-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:29PM +0100, Marc Zyngier wrote:
> Add HYP and S2 page flags, for both normal and device memory.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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think the latter and
you can use greater than (without equal).
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On Tue, May 14, 2013 at 03:13:31PM +0100, Marc Zyngier wrote:
> Define all the useful bitfields for EL2 registers.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:32PM +0100, Marc Zyngier wrote:
> Define the saved/restored registers for 64bit guests.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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dabt_isvalid(const struct kvm_vcpu *vcpu)
> +{
> + return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
> +}
You kept these '!!' ;). BTW, would the compiler handle the conversion
between the integer and bool here?
Either way is fine by me:
Reviewed-by: Catalin Marinas
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To
On Tue, May 14, 2013 at 03:13:34PM +0100, Marc Zyngier wrote:
> Implement the injection of a fault (undefined, data abort or
> prefetch abort) into a 64bit guest.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
> +static inline bool kvm_is_write_fault(unsigned long esr)
> +{
> + unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
Not that it would make much difference but for consistency - we use esr
as an 'unsigned int' in the arm64 code (onl
On Tue, May 14, 2013 at 03:13:36PM +0100, Marc Zyngier wrote:
> Provide the kvm.h file that defines the user space visible
> interface.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:37PM +0100, Marc Zyngier wrote:
> Provide 64bit system register handling, modeled after the cp15
> handling for ARM.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Mon, May 20, 2013 at 05:17:31PM +0100, Marc Zyngier wrote:
> On 20/05/13 16:57, Catalin Marinas wrote:
> > On Tue, May 14, 2013 at 03:13:35PM +0100, Marc Zyngier wrote:
> >> +static inline bool kvm_is_write_fault(unsigned long esr)
> >> +{
> >> + unsigned l
On Tue, May 14, 2013 at 03:13:38PM +0100, Marc Zyngier wrote:
> Add the support code for CPU specific system registers. Not much
> here yet.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:39PM +0100, Marc Zyngier wrote:
> Provide the reset code for a virtual CPU booted in 64bit mode.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:40PM +0100, Marc Zyngier wrote:
> Provide the architecture dependent structures for VM and
> vcpu abstractions.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:41PM +0100, Marc Zyngier wrote:
> Define the necessary structures to perform an MMIO access.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:42PM +0100, Marc Zyngier wrote:
> Let userspace play with the guest registers.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
> --- /dev/null
> +++ b/arch/arm64/kvm/guest.c
...
> +static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_
On Tue, May 14, 2013 at 03:13:43PM +0100, Marc Zyngier wrote:
> --- /dev/null
> +++ b/arch/arm64/kvm/hyp-init.S
...
> + .text
> + .pushsection.hyp.idmap.text, "ax"
> +
> + .align 11
> +
> +__kvm_hyp_init:
> + .global __kvm_hyp_init
> +
> +ENTRY(__kvm_hyp_init_vector)
Why do yo
On Tue, May 14, 2013 at 03:13:44PM +0100, Marc Zyngier wrote:
> +// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
> +ENTRY(__kvm_tlb_flush_vmid_ipa)
> + kern_hyp_va x0
> + ldr x2, [x0, #KVM_VTTBR]
> + msr vttbr_el2, x2
> + isb
> +
> + /*
On Tue, May 14, 2013 at 03:13:45PM +0100, Marc Zyngier wrote:
> Handle the exit of a VM, decoding the exit reason from HYP mode
> and calling the corresponding handler.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
--
To u
On Tue, May 14, 2013 at 03:13:46PM +0100, Marc Zyngier wrote:
> Add support for the in-kernel GIC emulation.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:48PM +0100, Marc Zyngier wrote:
> Wire the PSCI backend into the exit handling code.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:49PM +0100, Marc Zyngier wrote:
> --- /dev/null
> +++ b/arch/arm64/kvm/Kconfig
...
> +config KVM_ARM_VGIC
> +bool
> + depends on KVM_ARM_HOST && OF
> + select HAVE_KVM_IRQCHIP
> + ---help---
> + Adds support for a hardware assisted, in-kernel
On Tue, May 14, 2013 at 03:13:59PM +0100, Marc Zyngier wrote:
> Elect myself as the KVM/arm64 maintainer.
>
> Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
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_vmid
> ARM: KVM: relax cache maintainance when building page tables
> ARM: KVM: use phys_addr_t instead of unsigned long long for HYP PGDs
> ARM: KVM: don't special case PC when doing an MMIO
> ARM: KVM: get rid of S2_PGD_SIZE
> ARM: KVM: drop use of PAGE_S2_DEVICE
This s
On Tue, May 21, 2013 at 05:09:47PM +0100, Paolo Bonzini wrote:
>
>
> - Messaggio originale -
> > Da: "Catalin Marinas"
> > A: "Marc Zyngier"
> > Cc: linux-arm-ker...@lists.infradead.org, kvm...@lists.cs.columbia.edu,
> > kvm@vger.k
pped into their 64bit counterpart in most
> cases.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:51PM +0100, Marc Zyngier wrote:
> Allow access to the 32bit register file through the usual API.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:52PM +0100, Marc Zyngier wrote:
> As conditional instructions can trap on AArch32, add the thinest
> possible emulation layer to keep 32bit guests happy.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin
n
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:54PM +0100, Marc Zyngier wrote:
> Enable handling of CPU specific 32bit coprocessor access. Not much
> here either.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:55PM +0100, Marc Zyngier wrote:
> Allow registers specific to 32bit guests to be saved/restored
> during the world switch.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:56PM +0100, Marc Zyngier wrote:
> Add fault injection capability for 32bit guests.
>
> Reviewed-by: Christopher Covington
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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cal CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
> capability.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:14:00PM +0100, Marc Zyngier wrote:
> HYP mode has access to some of the kernel pages. Document the
> memory mapping and the offset between kernel VA and HYP VA.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
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On Tue, May 14, 2013 at 03:13:58PM +0100, Marc Zyngier wrote:
> Unsurprisingly, the arm64 userspace API is extremely similar to
> the 32bit one, the only significant difference being the ONE_REG
> register mapping.
>
> Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
--
On Tue, Jun 04, 2013 at 02:13:52PM +0100, Anup Patel wrote:
> Hi Marc,
>
> On Tue, Jun 4, 2013 at 5:59 PM, Marc Zyngier wrote:
> > Guys,
> >
> > The KVM/arm64 code is now, as it seems, in good enough shape to be
> > merged. I've so far addressed all the comments, and it doesn't seem any
> > worse
On Wed, Jun 05, 2013 at 07:01:05AM +0100, Gleb Natapov wrote:
> On Tue, Jun 04, 2013 at 10:57:32PM -0700, Christoffer Dall wrote:
> > On 4 June 2013 09:37, Gleb Natapov wrote:
> > > On Tue, Jun 04, 2013 at 05:51:41PM +0200, Paolo Bonzini wrote:
> > >> Il 04/06/2013 17:43, Christoffer Dall ha scrit
On Mon, Jul 22, 2013 at 01:51:52PM +0100, Christoffer Dall wrote:
> On 22 July 2013 10:53, Raghavendra KT wrote:
> > On Fri, Jul 19, 2013 at 7:23 PM, Marc Zyngier wrote:
> >> So far, when a guest executes WFE (like when waiting for a spinlock
> >> to become unlocked), we don't do a thing and let
On Tue, Sep 09, 2014 at 12:08:52AM +0100, Joel Schopp wrote:
> The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current
> systems. Rather than just add a bit it seems like a good time to also set
> things at run-time instead of compile time to accomodate more hardware.
>
> This
On Fri, Sep 19, 2014 at 04:28:54PM +0100, Catalin Marinas wrote:
> On Tue, Sep 09, 2014 at 12:08:52AM +0100, Joel Schopp wrote:
> > The current VTTBR_BADDR_MASK only masks 39 bits, which is broken on current
> > systems. Rather than just add a bit it seems like a good time to also
On Mon, Sep 22, 2014 at 04:56:58PM +0100, Joel Schopp wrote:
> > The TCR_EL2.PS setting should be done based on the ID_A64MMFR0_EL1
> > but you can do this in __do_hyp_init (it looks like this function
> > handles VTCR_EL2.PS already, not sure why it does do it for TCR_EL2 as
> > well).
> >
> > So
IPA range and changed the stage-2 pgd allocation to be based on
>the 40 bit IPA range instead of the maximum possible 48 bit PA range.
>- Christoffer ]
>
> Signed-off-by: Joel Schopp
> Signed-off-by: Christoffer Dall
Reviewed-by: Catalin Marinas
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Hi Christoffer,
On Thu, Sep 25, 2014 at 08:42:53PM +0100, Christoffer Dall wrote:
> diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
> index 7796051..048f37f 100644
> --- a/arch/arm/kvm/arm.c
> +++ b/arch/arm/kvm/arm.c
> @@ -409,7 +409,7 @@ static void update_vttbr(struct kvm *kvm)
> k
On Thu, Sep 25, 2014 at 08:42:54PM +0100, Christoffer Dall wrote:
> When creating or moving a memslot, make sure the IPA space is within the
> addressable range of the guest. Otherwise, user space can create too
> large a memslot and KVM would try to access potentially unallocated page
> table ent
On Mon, Oct 06, 2014 at 02:41:18PM +0100, Christoffer Dall wrote:
> On Tue, Sep 30, 2014 at 01:39:47PM +0100, Catalin Marinas wrote:
> > On Thu, Sep 25, 2014 at 08:42:53PM +0100, Christoffer Dall wrote:
> > > @@ -572,19 +614,36 @@ void kvm_free_stage2_p
On Mon, Oct 06, 2014 at 02:47:01PM +0100, Christoffer Dall wrote:
> On Tue, Sep 30, 2014 at 01:46:51PM +0100, Catalin Marinas wrote:
> > On Thu, Sep 25, 2014 at 08:42:54PM +0100, Christoffer Dall wrote:
> > > When creating or moving a memslot, make sure the IPA s
On Mon, Oct 06, 2014 at 09:30:24PM +0100, Christoffer Dall wrote:
> The following host configurations have been tested with KVM on APM
> Mustang:
[...]
> 3) 64KB + 39 bits VA space
That would be 42-bit VA space.
--
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th
On Mon, Oct 06, 2014 at 09:30:25PM +0100, Christoffer Dall wrote:
> +/**
> + * kvm_prealloc_hwpgd - allocate inital table for VTTBR
> + * @kvm: The KVM struct pointer for the VM.
> + * @pgd: The kernel pseudo pgd
> + *
> + * When the kernel uses more levels of page tables than the guest
On Tue, Oct 07, 2014 at 08:39:54PM +0100, Christoffer Dall wrote:
> I came up with the following based on your feedback, but I personally
> don't find it a lot easier to read than what I had already. Suggestions
> are welcome:
At least PTRS_PER_S2_PGD and KVM_PREALLOC_LEVEL are clearer to me as
f
On Thu, Oct 09, 2014 at 12:01:37PM +0100, Christoffer Dall wrote:
> On Wed, Oct 08, 2014 at 10:47:04AM +0100, Catalin Marinas wrote:
> > On Tue, Oct 07, 2014 at 08:39:54PM +0100, Christoffer Dall wrote:
> > > +static inline int kvm_prealloc_hwpgd(struct kv
e
> table entries when inserting entries in the Stage-2 page tables.
>
> Signed-off-by: Christoffer Dall
Acked-by: Catalin Marinas
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>There were too many changes from the original patch for me to
>preserve the authorship. Thanks to Catalin Marinas for his help in
>figuring out a good solution to this challenge. I have also fixed
>various bugs and missing error code handling from the original
>patch. - Chri
On Fri, Oct 10, 2014 at 11:14:30AM +0100, Christoffer Dall wrote:
> Now when KVM has been reworked to support 48-bits host VA space, we can
> allow systems to be configured with this option. However, the ARM SMMU
> driver also needs to be tweaked for 48-bit support so only allow the
> config optio
_RDWR(_AT(pteval_t, 3) << 6) /* HAP[2:1] */
>
> +#define PMD_S2_RDWR(_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
> +
> /*
> * Memory Attribute override for Stage-2 (MemAttr[3:0])
> */
For the arm64 part:
Acked-by: Catalin Marinas
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On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote:
> On 24/01/14 23:37, Christoffer Dall wrote:
> > On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
> >> --- a/arch/arm/include/asm/pgtable-3level.h
> >> +++ b/arch/arm/include/asm/pgtable-3level.h
> >> @@ -120,13 +120,19
On Mon, Jan 27, 2014 at 05:02:25PM +, Marc Zyngier wrote:
> On 27/01/14 16:57, Catalin Marinas wrote:
> > On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote:
> >> On 24/01/14 23:37, Christoffer Dall wrote:
> >>> On Sat, Jan 04, 2014 at 08:27:23AM
On Wed, Feb 05, 2014 at 07:55:45PM +, Marc Zyngier wrote:
> The default pmd_addr_end macro uses an unsigned long to represent
> the VA. When used with KVM and stage-2 translation, the VA is
> actually an IPA, which is up to 40 bits. This also affect the
> SMMU driver, which also deals with stag
viewed-by: Christoffer Dall
Reviewed-by: Catalin Marinas
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ementation is: CRn, 64bit-first, CRm...
>
> Move the 64bit test to be last in order to match the documentation.
>
> Signed-off-by: Marc Zyngier
> Reviewed-by: Christoffer Dall
Acked-by: Catalin Marinas
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the problem. Also update the debug feature to emit the
> expected string in case of failing match.
>
> Signed-off-by: Marc Zyngier
> Reviewed-by: Christoffer Dall
Acked-by: Catalin Marinas
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ry to allow the HCR to be changed on a per-vcpu basis.
>
> The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
> field, initialized at setup time.
>
> Signed-off-by: Marc Zyngier
> Reviewed-by: Christoffer Dall
Acked-by: Catalin Marinas
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a saner mode of operation, which is to leave these
> registers in complete control of the guest.
>
> Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
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registers we switch/handle.
>
> Signed-off-by: Marc Zyngier
> Reviewed-by: Christoffer Dall
Acked-by: Catalin Marinas
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On Fri, Feb 07, 2014 at 04:04:56AM +, Christoffer Dall wrote:
> On Thu, Feb 06, 2014 at 10:43:28AM +0000, Catalin Marinas wrote:
> > On Wed, Feb 05, 2014 at 07:55:45PM +, Marc Zyngier wrote:
> > > The default pmd_addr_end macro uses an unsigned long to represent
>
> The fix is to introduce 64bit clean versions of the same helpers,
> and use them in the stage-2 page table code.
>
> Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
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On Wed, Feb 19, 2014 at 09:02:34AM +, Marc Zyngier wrote:
> On 2014-02-18 20:57, Eric Northup wrote:
> > On Tue, Feb 18, 2014 at 7:27 AM, Marc Zyngier
> > wrote:
> >>
> >> When we run a guest with cache disabled, we don't flush the cache to
> >> the Point of Coherency, hence possibly missing
On 18 September 2012 13:47, Will Deacon wrote:
> On Sat, Sep 15, 2012 at 04:34:43PM +0100, Christoffer Dall wrote:
>> +#define L_PTE2_SHAREDL_PTE_SHARED
>> +#define L_PTE2_READ (_AT(pteval_t, 1) << 6) /* HAP[0] */
>> +#define L_PTE2_WRITE (_AT(pteval_t, 1) << 7) /*
On Tue, Sep 18, 2012 at 04:05:13PM +0100, Christoffer Dall wrote:
> On Tue, Sep 18, 2012 at 10:06 AM, Catalin Marinas
> wrote:
> > On 18 September 2012 13:47, Will Deacon wrote:
> >> On Sat, Sep 15, 2012 at 04:34:43PM +0100, Christoffer Dall wrote:
> &g
On 25 September 2012 13:38, Christoffer Dall
wrote:
>>> +
>>> + /*
>>> + * If this is a write fault (think COW) we need to make sure the
>>> + * existing page, which other CPUs might still read, doesn't go
>>> away
>>> + * from under us, by calling gfn_to_pfn_prot(write_fault=tr
On Thu, Sep 27, 2012 at 06:15:05PM +0100, Christoffer Dall wrote:
> On Thu, Sep 27, 2012 at 8:39 AM, Catalin Marinas
> wrote:
> > On 25 September 2012 13:38, Christoffer Dall
> > wrote:
> >>>> +
> >>>> + /*
> >>>> +
On 26 February 2014 20:05, Christoffer Dall wrote:
> On Wed, Feb 26, 2014 at 08:55:58PM +0100, Arnd Bergmann wrote:
>> On Wednesday 26 February 2014 10:34:54 Christoffer Dall wrote:
>> > For more information about UEFI and ACPI booting, see [4] and [5].
>>
>> What's the point of having ACPI in a v
rts.
>
> Cc: Catalin Marinas
> Cc: Russell King
> Cc: Paolo Bonzini
> Cc: Gleb Natapov
> Signed-off-by: Marc Zyngier
> Signed-off-by: Christoffer Dall
Acked-by: Catalin Marinas
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Hi Christoffer,
On Wed, Jan 16, 2013 at 05:57:26PM +, Christoffer Dall wrote:
> diff --git a/arch/arm/include/asm/pgtable-3level.h
> b/arch/arm/include/asm/pgtable-3level.h
> index a3f3792..6ef8afd 100644
> --- a/arch/arm/include/asm/pgtable-3level.h
> +++ b/arch/arm/include/asm/pgtable-3leve
On Wed, Jan 16, 2013 at 05:57:34PM +, Christoffer Dall wrote:
> --- a/arch/arm/mm/idmap.c
> +++ b/arch/arm/mm/idmap.c
> @@ -1,4 +1,6 @@
> +#include
Minor thing - do you need to include linux/module.h here?
> + identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
> +
On Wed, Jan 16, 2013 at 05:57:48PM +, Christoffer Dall wrote:
> --- a/arch/arm/include/asm/pgtable-3level-hwdef.h
> +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
> @@ -32,6 +32,9 @@
> #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
> #define PMD_BIT4 (_AT(pmdval_t, 0)
minor clean-up issues (which can be done
later as an additional patch) they look fine to me.
Reviewed-by: Catalin Marinas
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On Thu, Jan 24, 2013 at 04:05:33PM +, Christoffer Dall wrote:
> On Thu, Jan 24, 2013 at 6:39 AM, Catalin Marinas
> wrote:
> > On Wed, Jan 16, 2013 at 05:57:26PM +, Christoffer Dall wrote:
> >> diff --git a/arch/arm/include/asm/pgtable-3level.h
> >> b/arch/ar
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