Hi Thomas,
> -Original Message-
> From: Thomas Gleixner
> Sent: Friday, May 29, 2020 12:36 AM
> To: Jianyong Wu ; net...@vger.kernel.org;
> yangbo...@nxp.com; john.stu...@linaro.org; pbonz...@redhat.com;
> sean.j.christopher...@intel.com; m...@kernel.org;
> richardcoch...@gmail.com; Mark
Jianyong Wu writes:
> From: Thomas Gleixner
> diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
> index 7cb09c4cf21c..a8f65b3e4ec8 100644
> --- a/kernel/time/clocksource.c
> +++ b/kernel/time/clocksource.c
> @@ -928,6 +928,9 @@ int __clocksource_register_scale(struct clocksource
Having __load_guest_stage2 in kvm_hyp.h is quickly going to trigger
a circular include problem. In order to avoid this, let's move
it to kvm_mmu.h, where it will be a better fit anyway.
In the process, drop the __hyp_text annotation, which doesn't help
as the function is marked as
With ARMv8.5-GTG, the hardware (or more likely a hypervisor) can
advertise the supported Stage-2 page sizes.
Let's check this at boot time.
Reviewed-by: Suzuki K Poulose
Reviewed-by: Alexandru Elisei
Signed-off-by: Marc Zyngier
---
Hi Will,
Can you please take this patch via the arm64 tree,
Hi Marc,
On 28/05/2020 13:38, Marc Zyngier wrote:
> On 2020-05-28 13:36, Marc Zyngier wrote:
>> On 2020-05-26 17:18, James Morse wrote:
>>> KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
>>> This means ACTLR* accesses from the guest are always trapped, and
>>> always return
Hi James,
On 2020-05-26 17:18, James Morse wrote:
ACTLR_EL1 is a 64bit register while the 32bit ACTLR is obviously 32bit.
For 32bit software, the extra bits are accessible via ACTLR2... which
KVM doesn't emulate.
Signed-off-by: James Morse
---
I'm not convinced this is endian safe, but it
On 2020-05-28 13:36, Marc Zyngier wrote:
On 2020-05-26 17:18, James Morse wrote:
KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
TAC is a leftover from 32bit.
This means ACTLR* accesses from the guest are always trapped, and
always return the value in the sys_regs array.
On 2020-05-26 17:18, James Morse wrote:
KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
TAC is a leftover from 32bit.
This means ACTLR* accesses from the guest are always trapped, and
always return the value in the sys_regs array.
The guest can't change the value of
On 2020-05-28 12:59, James Morse wrote:
Hi Marc,
On 28/05/2020 09:57, Marc Zyngier wrote:
On 2020-05-26 17:18, James Morse wrote:
access_csselr() uses the 32bit r->reg value to access the 64bit
array,
so reads and write the wrong value. sys_regs[4], is ACTLR_EL1, which
is subsequently
Hi Marc,
On 28/05/2020 09:57, Marc Zyngier wrote:
> On 2020-05-26 17:18, James Morse wrote:
>> access_csselr() uses the 32bit r->reg value to access the 64bit array,
>> so reads and write the wrong value. sys_regs[4], is ACTLR_EL1, which
>> is subsequently save/restored when we enter the guest.
On 28/05/20 09:03, Marc Zyngier wrote:
> The current state of the architecture doesn't seem to leave much leeway in
> terms of SW creativity here. You just can't allocate your own ISS encoding
> without risking a clash with future revisions of the architecture.
> It isn't even clear whether the
On 28/05/20 08:14, Gavin Shan wrote:
>> - for x86 we're also thinking of initiating the page fault from the
>> exception handler, rather than doing so from the hypervisor before
>> injecting the exception. If ARM leads the way here, we would do our
>> best to share code when x86 does the same.
>
Hi James,
On 2020-05-26 17:18, James Morse wrote:
aarch32 has pairs of registers to access the high and low parts of
64bit
registers. KVM has a union of 64bit sys_regs[] and 32bit copro[]. The
32bit accessors read the high or low part of the 64bit sys_reg[] value
through the union.
Both
Hi Marc,
On 5/27/20 5:37 PM, Marc Zyngier wrote:
On 2020-05-27 05:05, Gavin Shan wrote:
[...]
+struct kvm_vcpu_pv_apf_data {
+ __u32 reason;
+ __u8 pad[60];
+ __u32 enabled;
+};
What's all the padding for?
The padding is ensure the @reason and @enabled in different
Hi Paolo,
On 5/27/20 4:48 PM, Paolo Bonzini wrote:
I definitely appreciate the work, but this is repeating most of the
mistakes done in the x86 implementation. In particular:
- the page ready signal can be done as an interrupt, rather than an
exception. This is because "page ready" can be
On 5/27/20 5:20 PM, Marc Zyngier wrote:
On 2020-05-27 03:43, Gavin Shan wrote:
Hi Mark,
On 5/26/20 8:42 PM, Mark Rutland wrote:
On Fri, May 08, 2020 at 01:29:13PM +1000, Gavin Shan wrote:
Since kvm/arm32 was removed, this renames kvm_vcpu_get_hsr() to
kvm_vcpu_get_esr() to it a bit more
On 2020-05-28 07:14, Gavin Shan wrote:
Hi Paolo,
On 5/27/20 4:48 PM, Paolo Bonzini wrote:
I definitely appreciate the work, but this is repeating most of the
mistakes done in the x86 implementation. In particular:
- the page ready signal can be done as an interrupt, rather than an
exception.
17 matches
Mail list logo
