Re: [PATCH 0/2] Add the missing resetting LRs at boot time for new-vgic

On 2016/12/6 19:47, Marc Zyngier wrote: > On 06/12/16 06:41, Shannon Zhao wrote: >> From: Shannon Zhao >> >> Commit 50926d8(KVM: arm/arm64: The GIC is dead, long live the GIC) >> removes the old vgic and commit 9097773(KVM: arm/arm64: vgic-new: >> vgic_init: implement

Re: [PATCH] arm/arm64: KVM: Check for properly initialized timer on init

On Tue, Dec 06, 2016 at 11:25:42AM +, Marc Zyngier wrote: > On 05/12/16 09:32, Christoffer Dall wrote: > > When the arch timer code fails to initialize (for example because the > > memory mapped timer doesn't work, which is currently seen with the AEM > > model), then KVM just continues

[kvm-unit-tests PATCH v14 4/5] arm: pmu: Check cycle count increases

From: Christopher Covington Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, even for the smallest delta of two subsequent reads. Signed-off-by: Christopher Covington Signed-off-by: Wei Huang --- arm/pmu.c | 66

[kvm-unit-tests PATCH v14 2/5] arm: Add support for read_sysreg() and write_sysreg()

This patch adds two new macros to support read/write operations of ARMv7 and ARMv8 system registers. As part of the change, xstr() is revised to support variable arguments. With it, ARMv7 system register can be defined with __ACCESS_CP15() or __ACCESS_CP15_64() depending if it is 32-bit or 64-bit.

[kvm-unit-tests PATCH v14 1/5] arm: rename cp15.h to sysreg.h

To prepare for future support of ARMv8 system register, rename cp15.h file to sysreg.h, with _ASMARM_CP15_H_ renamed to _ASMARM_SYSREG_H_ in header file. Signed-off-by: Wei Huang --- arm/cstart.S | 2 +- lib/arm/asm/{cp15.h => sysreg.h} | 6 +++--- 2 files

[kvm-unit-tests PATCH v14 5/5] arm: pmu: Add CPI checking

From: Christopher Covington Calculate the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. The code includes a strict checking facility intended for the -icount option in TCG mode in the configuration file. Signed-off-by: Christopher

[kvm-unit-tests PATCH v14 3/5] arm: Add PMU test

From: Christopher Covington Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington Signed-off-by: Wei Huang ---

[kvm-unit-tests PATCH v14 0/5] ARM PMU tests

Changes from v13: * Rename cp15.h to sysreg.h for ARMv7 and add a new file sysreg.h for ARMv8 * Add macros for read_sysreg() and write_sysreg(). CP15 registers can be defined with __ACCESS_CP15() or __ACCESS_CP15_64(). sysreg.h (ARMv8) was from Drew's GIC testing code, which can be leveraged

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On 06/12/16 16:29, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: >> The ARMv8 architecture allows the cycle counter to be configured >> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, >> hence accessing PMCCFILTR_EL0. But it disallows

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On 05/12/16 08:09, Maninder Singh wrote: > This patch corrects format specifier for printing 64 bit addresses. > > Signed-off-by: Maninder Singh > Signed-off-by: Vaneet Narang > --- > arch/arm64/kernel/signal.c | 2 +- > arch/arm64/kvm/sys_regs.c

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On Tue, Dec 06, 2016 at 05:29:18PM +0100, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: > > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > > index 83037cd..3b7cfbd 100644 > > --- a/arch/arm64/kvm/hyp/switch.c > > +++

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On 06/12/16 16:11, Christoffer Dall wrote: > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: >> This patch corrects format specifier for printing 64 bit addresses. >> >> Signed-off-by: Maninder Singh >> Signed-off-by: Vaneet Narang

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: > The ARMv8 architecture allows the cycle counter to be configured > by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, > hence accessing PMCCFILTR_EL0. But it disallows the use of > PMSELR_EL0.SEL==0x1f to access the

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: > This patch corrects format specifier for printing 64 bit addresses. > > Signed-off-by: Maninder Singh > Signed-off-by: Vaneet Narang > --- > arch/arm64/kernel/signal.c | 2 +- >

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On 06/12/16 15:27, Will Deacon wrote: > On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: >> The ARMv8 architecture allows the cycle counter to be configured >> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, >> hence accessing PMCCFILTR_EL0. But it disallows the use

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On Tue, Dec 06, 2016 at 03:26:37PM +, Catalin Marinas wrote: > On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote: > > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: > > > This patch corrects format specifier for printing 64 bit addresses. > > > > > > Signed-off-by:

Re: [PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

On Tue, Dec 06, 2016 at 02:56:50PM +, Marc Zyngier wrote: > The ARMv8 architecture allows the cycle counter to be configured > by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, > hence accessing PMCCFILTR_EL0. But it disallows the use of > PMSELR_EL0.SEL==0x1f to access the

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On Mon, Dec 05, 2016 at 11:24:21AM +, Will Deacon wrote: > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: > > This patch corrects format specifier for printing 64 bit addresses. > > > > Signed-off-by: Maninder Singh > > Signed-off-by: Vaneet Narang

[PATCH v2] arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

The ARMv8 architecture allows the cycle counter to be configured by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, hence accessing PMCCFILTR_EL0. But it disallows the use of PMSELR_EL0.SEL==0x1f to access the cycle counter itself through PMXEVCNTR_EL0. Linux itself doesn't

Re: [PATCH v9 01/11] arm/arm64: vgic: Implement support for userspace access

On Tue, Dec 06, 2016 at 12:42:09PM +0100, Auger Eric wrote: > Hi, > > On 28/11/2016 14:05, Christoffer Dall wrote: > > On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kil...@gmail.com wrote: > >> From: Vijaya Kumar K > >> > >> Read and write of some registers like

Re: [PATCH 1/2] arm64: PMU: Do not use PMSELR_EL0 to access PMCCFILTR_EL0

On 06/12/16 13:50, Will Deacon wrote: > On Fri, Dec 02, 2016 at 03:50:58PM +, Marc Zyngier wrote: >> The ARMv8 architecture allows the cycle counter to be configured >> by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, >> hence accessing PMCCFILTR_EL0. But it disallows the use

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Dec 06, 2016 at 01:09:26PM +, Marc Zyngier wrote: > On 06/12/16 12:16, Christoffer Dall wrote: > > On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote: > >> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: > >>> On 01/12/16 19:32, Jintack Lim wrote: >

Re: [PATCH v9 04/11] irqchip/gic-v3: Add missing system register definitions

Hi, On 23/11/2016 14:01, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and > ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers. > > Signed-off-by: Vijaya Kumar K > --- >

Re: [PATCH 1/2] arm64: PMU: Do not use PMSELR_EL0 to access PMCCFILTR_EL0

On Fri, Dec 02, 2016 at 03:50:58PM +, Marc Zyngier wrote: > The ARMv8 architecture allows the cycle counter to be configured > by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, > hence accessing PMCCFILTR_EL0. But it disallows the use of > PMSELR_EL0.SEL==0x1f to access the

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

Hi Christoffer, Thanks for the review. On Tue, Dec 6, 2016 at 7:12 AM, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: >> On 01/12/16 19:32, Jintack Lim wrote: >> > Current KVM world switch code is unintentionally setting wrong

Re: [PATCH v9 03/11] arm/arm64: vgic: Introduce find_reg_by_id()

Hi Vijay, On 23/11/2016 14:01, vijay.kil...@gmail.com wrote: > From: Vijaya Kumar K > > In order to implement vGICv3 CPU interface access, we will need to perform > table lookup of system registers. We would need both index_to_params() and > find_reg() exported for that

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Dec 6, 2016 at 6:17 AM, Marc Zyngier wrote: > On 01/12/16 19:32, Jintack Lim wrote: >> Current KVM world switch code is unintentionally setting wrong bits to >> CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical >> timer. Bit positions of

Re: [PATCH v9 02/11] arm/arm64: vgic: Add distributor and redistributor access

Hi, On 28/11/2016 14:08, Christoffer Dall wrote: > On Wed, Nov 23, 2016 at 06:31:49PM +0530, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> VGICv3 Distributor and Redistributor registers are accessed using >> KVM_DEV_ARM_VGIC_GRP_DIST_REGS and

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On 06/12/16 12:16, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote: >> On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: >>> On 01/12/16 19:32, Jintack Lim wrote: Current KVM world switch code is unintentionally setting wrong bits to

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Thu, Dec 01, 2016 at 02:32:05PM -0500, Jintack Lim wrote: > Current KVM world switch code is unintentionally setting wrong bits to > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical > timer. Bit positions of CNTHCTL_EL2 are changing depending on > HCR_EL2.E2H bit.

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Dec 06, 2016 at 01:12:21PM +0100, Christoffer Dall wrote: > On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: > > On 01/12/16 19:32, Jintack Lim wrote: > > > Current KVM world switch code is unintentionally setting wrong bits to > > > CNTHCTL_EL2 when E2H == 1, which may allow

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On Tue, Dec 06, 2016 at 11:17:40AM +, Marc Zyngier wrote: > On 01/12/16 19:32, Jintack Lim wrote: > > Current KVM world switch code is unintentionally setting wrong bits to > > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical > > timer. Bit positions of CNTHCTL_EL2 are

Re: [PATCH v9 01/11] arm/arm64: vgic: Implement support for userspace access

Hi, On 28/11/2016 14:05, Christoffer Dall wrote: > On Wed, Nov 23, 2016 at 06:31:48PM +0530, vijay.kil...@gmail.com wrote: >> From: Vijaya Kumar K >> >> Read and write of some registers like ISPENDR and ICPENDR >> from userspace requires special handling when compared to

Re: [PATCH 2/2] KVM: arm/arm64: vgic-v2: Add the missing resetting LRs at boot time

On 06/12/16 06:41, Shannon Zhao wrote: > From: Shannon Zhao > > This is the corresponding part of commit d6400d7(KVM: arm/arm64: > vgic-v2: Reset LRs at boot time) which is missed for new-vgic. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH 1/2] arm64: KVM: vgic-v3: Add the missing resetting LRs at boot time

Hi Shannon, On 06/12/16 06:41, Shannon Zhao wrote: > From: Shannon Zhao > > This is the corresponding part of commit 0d98d00(arm64: KVM: > vgic-v3: Reset LRs at boot time) which is missed for new-vgic. > > Signed-off-by: Shannon Zhao > --- >

Re: [Qemu-devel] [kvm-unit-tests RFC 00/15] arm/arm64: add ITS framework

On Tue, Dec 06, 2016 at 11:14:41AM +, Andre Przywara wrote: > Hi, > > On 06/12/16 09:48, Andrew Jones wrote: > > On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote: > >> This series proposes a framework to test the virtual ITS. > >> This is based on Drew's v7 series [1]. The last

Re: [PATCH v2] arm/arm64: KVM: VGIC: limit ITARGETSR bits to number of VCPUs

On 16/11/16 17:57, Andre Przywara wrote: > The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that > corresponds to an unimplemented CPU interface is RAZ/WI." > Currently we allow the guest to write any value in there and it can > read that back. > Mask the written value with the

Re: [PATCH v3] KVM: arm/arm64: Access CNTHCTL_EL2 bit fields correctly

On 01/12/16 19:32, Jintack Lim wrote: > Current KVM world switch code is unintentionally setting wrong bits to > CNTHCTL_EL2 when E2H == 1, which may allow guest OS to access physical > timer. Bit positions of CNTHCTL_EL2 are changing depending on > HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st

Re: [Qemu-devel] [kvm-unit-tests RFC 00/15] arm/arm64: add ITS framework

Hi, On 06/12/16 09:48, Andrew Jones wrote: > On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote: >> This series proposes a framework to test the virtual ITS. >> This is based on Drew's v7 series [1]. The last patch tests >> several ITS commands (collection/device mapping, interrupt >>

Re: [Qemu-devel] [kvm-unit-tests RFC 05/15] arm/arm64: GICv3: add cpu count

Hi Andre, Drew, On 06/12/2016 10:32, Andre Przywara wrote: > Hi, > > On 06/12/16 09:29, Andrew Jones wrote: >> On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote: >>> Add a new cpu_count field in gicv3_data indicating the >>> number of redistributors. This will be useful for enumeration

Re: [Qemu-devel] [kvm-unit-tests RFC 00/15] arm/arm64: add ITS framework

On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote: > This series proposes a framework to test the virtual ITS. > This is based on Drew's v7 series [1]. The last patch tests > several ITS commands (collection/device mapping, interrupt > translation service entry creation and LPI trigger

Re: [Qemu-devel] [kvm-unit-tests RFC 05/15] arm/arm64: GICv3: add cpu count

Hi, On 06/12/16 09:29, Andrew Jones wrote: > On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote: >> Add a new cpu_count field in gicv3_data indicating the >> number of redistributors. This will be useful for enumeration >> of their resources such as LPI pending tables. > > I'm fine with

Re: [Qemu-devel] [kvm-unit-tests RFC 05/15] arm/arm64: GICv3: add cpu count

On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote: > Add a new cpu_count field in gicv3_data indicating the > number of redistributors. This will be useful for enumeration > of their resources such as LPI pending tables. I'm fine with the additional state, but just curious, will it ever

Re: [Qemu-devel] [kvm-unit-tests RFC 03/15] arm/arm64: ITS skeleton

On Mon, Dec 05, 2016 at 10:46:34PM +0100, Eric Auger wrote: > At the moment we just detect the presence of ITS as part of the > GICv3 init routine and initialize its base address. > > Signed-off-by: Eric Auger > --- > arm/Makefile.common| 1 + >