Jonathan,
Thanks for the review, will correct the typo issue in the next patch version.
On 2017/8/22 15:54, Jonathan Cameron wrote:
> On Fri, 18 Aug 2017 22:11:50 +0800
> Dongjiu Geng wrote:
>
>> In the firmware-first RAS solution, corrupt data is detected in a
>> memory location when guest
This patch is used for GICv2 on GICv3.
About GICV_APRn hardware register access,the SPEC says:
When System register access is enabled for EL2, these registers access
ICH_AP1Rn_EL2, and all active priorities for virtual machines are held
in ICH_AP1Rn_EL2 regardless of interrupt group.
For GICv3 ha
It will be better that hide the underlying implementation for emulated GIC.
This patch extend the vgic_set/get_apr func (with group parameter) more general,
so that, the vGICv3 ICC_APRn sysreg uaccess can call this general interface
for GICv3 on GICv3.
Signed-off-by: wanghaibin
---
arch/arm64/kv
The SPEC defined GICC_APR (n = 0-3, 32-bit per register) to provide
information about interrupt active priorities for GICv2, and the user
access will traverse all of these registers no matter how many
priority levels we supported.
So we have to implement the uaccess interface cover all of these re
This patch is used for GICv2 on GICv2.
About GICV_APRn hardware register access,the SPEC says:
When System register access is disabled for EL2, these registers access
GICH_APRn, and all active priorities for virtual machines are held in
GICH_APRn regardless of interrupt group.
For GICv2 hardware,
v3: Coding style fix.
Add the valid APRn access check which Marc proposed.
v2: Split the patch again to make it easier for review
some fixes were proposed by Marc
v1: the problem describe:
In the case (GICv2 on GICv3 migration), I did the test on my board as follow:
vm boot => migrate to
Dave Martin writes:
> On Tue, Aug 22, 2017 at 05:21:19PM +0100, Alex Bennée wrote:
>>
>> Dave Martin writes:
>
> [...]
>
>> > --- a/arch/arm64/include/asm/processor.h
>> > +++ b/arch/arm64/include/asm/processor.h
>> > @@ -85,6 +85,8 @@ struct thread_struct {
>> >unsigned long tp2_
On Tue, Aug 22, 2017 at 05:22:11PM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
>
> > It's desirable to be able to reset the vector length to some sane
> > default for new processes, since the new binary and its libraries
> > processes may or may not be SVE-aware.
> >
> > This patch tracks
On Tue, Aug 22, 2017 at 05:21:19PM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
[...]
> > --- a/arch/arm64/include/asm/processor.h
> > +++ b/arch/arm64/include/asm/processor.h
> > @@ -85,6 +85,8 @@ struct thread_struct {
> > unsigned long tp2_value;
> > #endif
> > struct
Dave Martin writes:
> It's desirable to be able to reset the vector length to some sane
> default for new processes, since the new binary and its libraries
> processes may or may not be SVE-aware.
>
> This patch tracks the desired post-exec vector length (if any) in a
> new thread member sve_vl_
Dave Martin writes:
> This patch adds the core support for switching and managing the SVE
> architectural state of user tasks.
>
> Calls to the existing FPSIMD low-level save/restore functions are
> factored out as new functions task_fpsimd_{save,load}(), since SVE
> now dynamically may or may n
On Tue, Aug 22, 2017 at 04:03:20PM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
>
> > On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote:
[...]
> >> +
> >> +#define SVE_VQ_BITS 128 /* 128 bits in one quadword */
> >> +#define SVE_VQ_BYTES(SVE_VQ_BITS
On Tue, Aug 22, 2017 at 04:04:28PM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
>
> > To enable the kernel to use SVE, all SVE traps from EL1 must be
> > disabled. To take maximum advantage of the hardware, the full
> > available vector length also needs to be enabled for EL1 by
> > progra
Dave Martin writes:
> To enable the kernel to use SVE, all SVE traps from EL1 must be
> disabled. To take maximum advantage of the hardware, the full
> available vector length also needs to be enabled for EL1 by
> programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as
> required, but
Dave Martin writes:
> On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote:
>> >>
>> >> Dave Martin writes:
>
> [...]
>
>> >> > +/*
>> >> > + * The SVE architecture leaves space for future exp
Hi,
On 25/07/2017 17:41, Marc Zyngier wrote:
> On 25/07/17 15:48, Christoffer Dall wrote:
>> On Tue, Jul 25, 2017 at 02:47:55PM +0100, Marc Zyngier wrote:
>>> On 21/07/17 14:03, Christoffer Dall wrote:
On Fri, Jul 07, 2017 at 09:41:42AM +0200, Auger Eric wrote:
> Hi Marc,
>
> On 0
Hi Christoffer,
On 21/07/2017 13:44, Christoffer Dall wrote:
> On Thu, Jun 15, 2017 at 02:52:36PM +0200, Eric Auger wrote:
>> We want to reuse the core of the map/unmap functions for IRQ
>> forwarding. Let's move the computation of the hwirq in
>> kvm_vgic_map_phys_irq and pass the linux IRQ as pa
Hi Christoffer,
On 21/07/2017 14:11, Christoffer Dall wrote:
> On Thu, Jun 15, 2017 at 02:52:37PM +0200, Eric Auger wrote:
>> Currently, the line level of unmapped level sensitive SPIs is
>> toggled down by the maintenance IRQ handler/resamplefd mechanism.
>>
>> As mapped SPI completion is not tra
On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
>
> > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote:
> >>
> >> Dave Martin writes:
[...]
> >> > +/*
> >> > + * The SVE architecture leaves space for future expansion of the
> >> > + * vector len
Dave Martin writes:
> On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote:
>>
>> Dave Martin writes:
>>
>> > This patch defines the representation that will be used for the SVE
>> > register state in the signal frame, and implements support for
>> > saving and restoring the SVE register
On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote:
>
> Dave Martin writes:
>
> > This patch defines the representation that will be used for the SVE
> > register state in the signal frame, and implements support for
> > saving and restoring the SVE registers around signals.
> >
> > The
Dave Martin writes:
> This patch defines the representation that will be used for the SVE
> register state in the signal frame, and implements support for
> saving and restoring the SVE registers around signals.
>
> The same layout will also be used for the in-kernel task state.
>
> Due to the v
On Fri, 18 Aug 2017 22:11:51 +0800
Dongjiu Geng wrote:
> From: Xie XiuQi
>
> ARM's v8.2 Extentions add support for Reliability, Availability and
> Serviceability (RAS). On CPUs with these extensions system software
extensions, system software
> can use additional barriers to isolate errors an
On Fri, 18 Aug 2017 22:11:57 +0800
Dongjiu Geng wrote:
> After receive SError, KVM firstly call memory failure to
> deal with the Error. If memory failure wants user space to
> handle it, it will notify user space. This patch adds support
> to userspace that injects virtual SError with specified
On Fri, 18 Aug 2017 22:11:50 +0800
Dongjiu Geng wrote:
> In the firmware-first RAS solution, corrupt data is detected in a
> memory location when guest OS application software executing at EL0
> or guest OS kernel El1 software are reading from the memory. The
> memory node records errors in an er
On Fri, 18 Aug 2017 22:11:56 +0800
Dongjiu Geng wrote:
> when userspace gets SIGBUS signal, it does not know whether
> this is a synchronous external abort or SError, so needs
> to get the exception syndrome. so this patch allows userspace
> can get this values. For syndrome, only give userspace
On Fri, 18 Aug 2017 22:11:53 +0800
Dongjiu Geng wrote:
> ARMV8.2 requires implementation of the RAS extension, in
> this extension it adds SEI(SError Interrupt) notification
> type, this patch addes a new GHES error source handling
> function for SEI. Because this error source parse and handling
On Fri, 18 Aug 2017 22:11:54 +0800
Dongjiu Geng wrote:
> In armv8.2 RAS extension, it adds virtual SError exception
> syndrome registeri(VSESR_EL2), user space will specify that
> value. so user space will check whether CPU feature has RAS
> extension. if has, it will specify the virtual SError s
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