On Wed, Apr 08, 2015 at 09:15:13AM +0100, Marc Zyngier wrote:
> On Tue, 7 Apr 2015 17:20:15 +0100
> Paolo Bonzini wrote:
>
> Hi Paolo,
>
> > On 18/03/2015 08:55, Christoffer Dall wrote:
> > > Hi Stephen,
> > >
> > > On Wed, Mar 18, 2015 at 02:
r7, vcpu, #VCPU_VFP_GUEST
> +1: add r7, vcpu, #VCPU_VFP_GUEST
> store_vfp_state r7
> add r7, vcpu, #VCPU_VFP_HOST
> ldr r7, [r7]
> --
> 2.1.4
>
Reviewed-by: Christoffer Dall
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On Sat, Mar 28, 2015 at 01:48:20AM +, Andre Przywara wrote:
> Our in-kernel VGIC emulation still uses struct kvm_run briefly before
> writing back the emulation result into the guest register. Using a
> userspace mapped data structure within the kernel sounds dodgy, also
> we do some extra copy
On Thu, Apr 09, 2015 at 02:06:47PM +0200, Andrew Jones wrote:
> On Thu, Apr 09, 2015 at 08:57:23AM +0100, Marc Zyngier wrote:
> > On Thu, 9 Apr 2015 02:46:54 +0100
> > Mario Smarduch wrote:
> >
> > Hi Mario,
> >
> > > I'm working with AsyncPF, and currently using
> > > hyp call to communicate gu
On Wed, Apr 08, 2015 at 06:16:50PM +0100, Marc Zyngier wrote:
> On 08/04/15 12:40, Christoffer Dall wrote:
> > On Mon, Mar 16, 2015 at 10:59:43AM +, Marc Zyngier wrote:
> >> On VM entry, we disable access to the VFP registers in order to
> >> perform a lazy save
On Thu, Apr 09, 2015 at 03:59:46PM +0200, Andrew Jones wrote:
> On Thu, Apr 09, 2015 at 03:35:06PM +0200, Christoffer Dall wrote:
> > On Thu, Apr 09, 2015 at 02:06:47PM +0200, Andrew Jones wrote:
> > > On Thu, Apr 09, 2015 at 08:57:23AM +0100, Marc Zyngier wrote:
> > >
: Andre Przywara
Reviewed-by: Christoffer Dall
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actual limit. Also we remove the former legacy hard limit of
> 127 in the ioctl code.
>
> Signed-off-by: Andre Przywara
> CC: # 4.0, 3.19, 3.18
Reviewed-by: Christoffer Dall
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On Fri, Apr 10, 2015 at 05:52:05PM +0100, Andre Przywara wrote:
> Hi Christopher,
>
> On 10/04/15 16:29, Christopher Covington wrote:
> > Hi Andre,
> >
> > On 04/10/2015 11:17 AM, Andre Przywara wrote:
> >> When userland injects a SPI via the KVM_IRQ_LINE ioctl we currently
> >> only check it aga
On Mon, Apr 13, 2015 at 11:21:20AM +0100, Marc Zyngier wrote:
> On 13/04/15 11:04, Christoffer Dall wrote:
> > On Fri, Apr 10, 2015 at 05:52:05PM +0100, Andre Przywara wrote:
> >> Hi Christopher,
> >>
> >> On 10/04/15 16:29, Christopher Covington wrote:
> >
On Tue, Mar 31, 2015 at 04:07:59PM +0100, Alex Bennée wrote:
> Bring into line with the commentary for the other structures and their
> KVM_EXIT_* cases.
>
> Signed-off-by: Alex Bennée
>
> ---
>
> v2
> - add comments for other exit types
>
> diff --git a/include/uapi/linux/kvm.h b/include/ua
On Tue, Mar 31, 2015 at 04:08:00PM +0100, Alex Bennée wrote:
> Currently x86, powerpc and soon arm64 use the same two architecture
> specific bits for guest debug support for software and hardware
> breakpoints. This makes the shared values explicit while leaving the
> gate open for another archite
On Tue, Mar 31, 2015 at 04:08:01PM +0100, Alex Bennée wrote:
> This commit defines the API headers for guest debugging. There are two
> architecture specific debug structures:
>
> - kvm_guest_debug_arch, allows us to pass in HW debug registers
> - kvm_debug_exit_arch, signals the exact debug e
On Tue, Mar 31, 2015 at 04:08:02PM +0100, Alex Bennée wrote:
> This commit adds a stub function to support the KVM_SET_GUEST_DEBUG
> ioctl. Currently any operation flag will return EINVAL. Actual
> functionality will be added with further patches.
>
> Signed-off-by: Alex Bennée .
>
> ---
> v2
>
On Thu, Apr 09, 2015 at 05:53:59PM +0100, Marc Zyngier wrote:
> The world switch spends quite some time dealing with the FP/SIMD
> registers, as the state is quite sizeable (32 128bit registers,
> plus some crumbs on the side). We save/restore them on each
> entry/exit, so that both the host and th
On Mon, Apr 13, 2015 at 03:12:10PM +0100, Marc Zyngier wrote:
> On 13/04/15 13:57, Christoffer Dall wrote:
> > On Thu, Apr 09, 2015 at 05:53:59PM +0100, Marc Zyngier wrote:
> >> The world switch spends quite some time dealing with the FP/SIMD
> >> registers, as the
On Tue, Mar 31, 2015 at 04:08:03PM +0100, Alex Bennée wrote:
> This is a precursor for later patches which will need to do more to
> setup debug state before entering the hyp.S switch code. The existing
> functionality for setting mdcr_el2 has been moved out of hyp.S and now
> uses the value kept i
On Mon, Apr 13, 2015 at 04:36:23PM +0200, Christoffer Dall wrote:
[...]
> > +
> > +/**
> > + * kvm_arch_setup_debug - set-up debug related stuff
>
> nit: I think you want "set up" when it's a verb.
>
> > + *
> > + * @vcpu: the vcpu point
On Mon, Apr 13, 2015 at 03:51:33PM +0100, Alex Bennée wrote:
>
> Christoffer Dall writes:
>
> > On Tue, Mar 31, 2015 at 04:08:00PM +0100, Alex Bennée wrote:
> >> Currently x86, powerpc and soon arm64 use the same two architecture
> >> specific bits for gue
On Tue, Mar 31, 2015 at 04:08:04PM +0100, Alex Bennée wrote:
> This adds support for SW breakpoints inserted by userspace.
>
> We do this by trapping all BKPT exceptions in the
> hypervisor (MDCR_EL2_TDE).
you mean trapping all exceptions in the guest to the hypervisor?
> The kvm_debug_exit_arch
Hi Alex,
On Tue, Mar 31, 2015 at 04:08:05PM +0100, Alex Bennée wrote:
> This adds support for single-stepping the guest. As userspace can and
> will manipulate guest registers before restarting any tweaking of the
> registers has to occur just before control is passed back to the guest.
this sent
On Tue, Mar 31, 2015 at 04:08:06PM +0100, Alex Bennée wrote:
> This adds support for userspace to control the HW debug registers for
> guest debug. We'll only copy the $ARCH defined number across as that is
> all that hyp.S will use anyway.
I don't really understand what this sentence means?
> I
On Fri, Apr 10, 2015 at 02:25:21PM +0200, Andrew Jones wrote:
[...]
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -196,16 +196,49 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu
> > *vcpu,
> > * - If the dirty bit is set, save guest registers, restore hos
On Mon, Apr 13, 2015 at 08:59:21AM +0100, Alex Bennée wrote:
[...]
> >> + /* MDSCR_EL1 */
> >> + if (r->reg == MDSCR_EL1) {
> >> + if (p->is_write)
> >> + vcpu_debug_saved_reg(vcpu, mdscr_el1) =
> >> + *v
On Tue, Mar 31, 2015 at 04:08:07PM +0100, Alex Bennée wrote:
> When we are using the hardware registers for guest debug we need to deal
> with the guests access to them. There is already a mechanism for dealing
> with these accesses so we build on top of that.
>
> - mdscr_el1_bits is renamed as
On Tue, Mar 31, 2015 at 04:08:08PM +0100, Alex Bennée wrote:
> This includes trace points for:
> kvm_arch_setup_guest_debug
> kvm_arch_clear_guest_debug
> kvm_handle_guest_debug
>
> I've also added some generic register setting trace events so I can
> watch the register values being built up
-1947,7 +1947,7 @@ int kvm_irq_map_gsi(struct kvm *kvm,
> struct kvm_kernel_irq_routing_entry *entries,
> int gsi)
> {
> - return gsi;
> + return 0;
> }
>
> int kvm_irq_map_chip_pin(struct kvm *k
On Mon, Apr 13, 2015 at 11:04:00AM +0200, Ard Biesheuvel wrote:
> On 27 March 2015 at 01:02, Ard Biesheuvel wrote:
> > On 26 March 2015 at 09:09, Riku Voipio wrote:
> >> On 25 March 2015 at 21:32, Ard Biesheuvel
> >> wrote:
> >>> On 25 March 2015 at 17:14, Ard Biesheuvel
> >>> wrote:
> O
Hi Paolo and Marc,
On Tue, Apr 07, 2015 at 06:20:15PM +0200, Paolo Bonzini wrote:
>
>
> On 18/03/2015 08:55, Christoffer Dall wrote:
> > Hi Stephen,
> >
> > On Wed, Mar 18, 2015 at 02:41:11PM +1100, Stephen Rothwell wrote:
> >> Hi all,
> >>
> >
On Thu, Apr 16, 2015 at 09:39:06PM +0200, Paolo Bonzini wrote:
>
>
> On 16/04/2015 21:10, Christoffer Dall wrote:
> >> >
> > As it turns out, it was not the same logic as Stephen's resolution.
> > Stephen's resolution is bussy, because vlr is passed
On Thu, Apr 16, 2015 at 06:02:27PM +0200, Paolo Bonzini wrote:
>
>
> On 16/04/2015 17:54, Jérémy Fanguède wrote:
> > The guest kernel driver of the lsi device fails to enable it correctly
> > with a cache error:
> > [...]
> > sym53c8xx :00:01.0: enabling device (0100 -> 0103)
> > sym0: <895a>
On Fri, Apr 17, 2015 at 03:48:35PM +0200, Jérémy Fanguède wrote:
> On Fri, Apr 17, 2015 at 11:29 AM, Christoffer Dall
> wrote:
> > On Thu, Apr 16, 2015 at 06:02:27PM +0200, Paolo Bonzini wrote:
> >>
> >>
> >> On 16/04/2015 17:54, Jérémy Fangučde wrote:
&g
On Wed, Mar 18, 2015 at 03:10:31PM -0400, Andrew Jones wrote:
> Also rename to KVM_MEM_UNCACHED.
>
> Signed-off-by: Andrew Jones
> ---
> Documentation/virtual/kvm/api.txt | 16 ++--
> arch/arm/include/uapi/asm/kvm.h | 1 +
> arch/arm/kvm/arm.c| 1 +
> arch/arm/kvm
index
into our frame of SPIs.
When instantiating a GICv2m device, tell PCI that we have instantiated
something that can deal with MSIs. We rely on the board actually wiring
up the GICv2m to the PCI host controller.
Signed-off-by: Christoffer Dall
---
Changes since v1:
- Check that writes to MSI_S
ed-by: Peter Maydell
Signed-off-by: Christoffer Dall
---
Changes since v1:
- Added reviewed-by tag
hw/arm/virt.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 565f573..887bcef 100644
--- a/hw/arm/virt.c
+++ b/h
verifying MSIs going through as
expected.
See the individual patches for changelogs.
Christoffer Dall (3):
target-arm: Add GIC phandle to VirtBoardInfo
arm_gicv2m: Add GICv2m widget to support MSIs
target-arm: Add the GICv2m to the virt board
hw/arm/virt.c | 67 ++---
Add a GICv2m device to the virt board to enable MSIs on the generic PCI
host controller. We allocate 64 SPIs in the IRQ space for now (this can
be increased/decreased later) and map the GICv2m right after the GIC in
the memory map.
Signed-off-by: Christoffer Dall
---
Changes since v1:
- Remove
On Thu, Apr 23, 2015 at 03:26:53PM +0100, Alex Bennée wrote:
>
> Christoffer Dall writes:
>
> > On Tue, Mar 31, 2015 at 04:08:04PM +0100, Alex Bennée wrote:
> >> This adds support for SW breakpoints inserted by userspace.
> >>
> >> We do t
On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter Maydell wrote:
> On 28 April 2015 at 09:42, Alex Bennée wrote:
> > Peter Maydell writes:
> >> Does the kernel already have a conveniently implemented "inject
> >> exception into guest" lump of code? If so it might be less effort
> >> to do it that w
On Tue, Apr 28, 2015 at 03:37:01PM +0100, Alex Bennée wrote:
>
> Christoffer Dall writes:
>
> > On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter Maydell wrote:
> >> On 28 April 2015 at 09:42, Alex Bennée wrote:
> >> > Peter Maydell writes:
> >> &
On Wed, Apr 29, 2015 at 10:18:18AM +0100, Alex Bennée wrote:
>
> Christoffer Dall writes:
>
> > On Tue, Apr 28, 2015 at 03:37:01PM +0100, Alex Bennée wrote:
> >>
> >> Christoffer Dall writes:
> >>
> >> > On Tue, Apr 28, 2015 at 10:34:12A
On Wed, Apr 29, 2015 at 5:08 PM, Alex Bennée wrote:
>
> Christoffer Dall writes:
>
>> On Wed, Apr 29, 2015 at 10:18:18AM +0100, Alex Bennée wrote:
>>>
>>> Christoffer Dall writes:
>>>
>>> > On Tue, Apr 28, 2015 at 03:37:01PM +0100, Ale
his is a pre-requisite for save/restore of the GICv3 distributor
> state, we should also emulate their handling in the distributor and
> redistributor frames of an emulated GICv3.
>
> Signed-off-by: Andre Przywara
Acked-by: Christoffer Dall
Appl
On Thu, Apr 30, 2015 at 01:43:31PM +0200, Christian Borntraeger wrote:
> Use __kvm_guest_{enter|exit} instead of kvm_guest_{enter|exit}
> where interrupts are disabled.
>
> Signed-off-by: Christian Borntraeger
For the ARM part:
Acked-by: Chri
On Sun, May 03, 2015 at 11:37:29AM +0800, 孙晓阳 wrote:
> Hello,
> I am intersted in KVM/ARM and I am trying to do some work based on KVM/ARM.
> But here is some questions :
> 1. if I set HCR.TGE=1, does the system calls will traps into hyp mode and
> be handled by hyp_svc( arch/arm/kvm/interrupts.S)?
On Mon, May 04, 2015 at 11:24:22AM +0200, Paolo Bonzini wrote:
>
>
> On 04/05/2015 04:48, Tiejun Chen wrote:
> > We already check KVM_CAP_IRQFD in generic once enable CONFIG_HAVE_KVM_IRQFD,
> >
> > kvm_vm_ioctl_check_extension_generic()
> > |
> > + switch (arg) {
> > + ...
> >
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
> To maintain cache coherency on ARM, we may need a mechanism to flush
> the data cache.
In addition to generally just making this functionality available (see
below), do you have an actual use case in mind for this? To
On Wed, Feb 11, 2015 at 09:20:55AM +0100, Eric Auger wrote:
> Fix multiple injection of level sensitive forwarded IRQs.
> With current code, the second injection fails since the state bitmaps
> are not reset (process_maintenance is not called anymore).
>
> New implementation follows those principl
Hi Eric,
On Wed, Feb 11, 2015 at 09:20:53AM +0100, Eric Auger wrote:
> This series proposes some fixes that appeared to be necessary
> to integrate IRQ forwarding in KVM/VFIO.
>
> - deactivation of the forwarded IRQ in irq_disabled case
> - a specific handling of forwarded IRQ into the VGIC state
On Wed, May 06, 2015 at 05:32:53PM +0200, Eric Auger wrote:
> On 05/06/2015 04:27 PM, Christoffer Dall wrote:
> > Hi Eric,
> >
> > On Wed, Feb 11, 2015 at 09:20:53AM +0100, Eric Auger wrote:
> >> This series proposes some fixes that appeared to be necessary
> >
On Thu, May 07, 2015 at 09:48:25AM +0200, Eric Auger wrote:
> Hi Christoffer,
>
> On 05/06/2015 04:26 PM, Christoffer Dall wrote:
> > On Wed, Feb 11, 2015 at 09:20:55AM +0100, Eric Auger wrote:
> >> Fix multiple injection of level sensitive forwarded IRQs.
> >&
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
> On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
> wrote:
> > Hi Jérémy,
> >
> > On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
> >> To maintain cache coherency on ARM, we may n
On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
wrote:
> On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
> wrote:
>> On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
>>> On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
>>> wrote:
>>>
97,7 @@ struct kvm_run {
> struct {
> __u64 gprs[32];
> } osi;
> + /* KVM_EXIT_PAPR_HCALL */
> struct {
> __u64 nr;
> __u64 ret;
> --
> 2.3.5
>
otherwise:
Acked-by: Christoffer Dall
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On Wed, May 06, 2015 at 05:23:17PM +0100, Alex Bennée wrote:
> Currently x86, powerpc and soon arm64 use the same two architecture
> specific bits for guest debug support for software and hardware
> breakpoints. This makes the shared values explicit while leaving the
> gate open for another archite
hitecture specific debug control flags" seems more accurate.
> + * kvm_guest_debug->control
> + */
> +#define KVM_GUESTDBG_USE_SW_BP __KVM_GUESTDBG_USE_SW_BP
> +#define KVM_GUESTDBG_USE_HW_BP __KVM_GUESTDBG_USE_HW_BP
> +
> #endif /* __ARM_KVM_H__ */
> --
> 2.3.5
>
Otherwise:
Acked-by: Christoffer Dall
Thanks,
-Christoffer
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On Wed, May 06, 2015 at 05:23:20PM +0100, Alex Bennée wrote:
> This is a precursor for later patches which will need to do more to
> setup debug state before entering the hyp.S switch code. The existing
> functionality for setting mdcr_el2 has been moved out of hyp.S and now
> uses the value kept i
}
> +
> + return ret;
> +}
> +
> static exit_handle_fn arm_exit_handlers[] = {
> [ESR_ELx_EC_WFx]= kvm_handle_wfx,
> [ESR_ELx_EC_CP15_32]= kvm_handle_cp15_32,
> @@ -96,6 +130,8 @@ static exit_handle_fn arm_exit_handlers[] = {
>
On Wed, May 06, 2015 at 05:23:22PM +0100, Alex Bennée wrote:
> This adds support for single-stepping the guest. To do this we need to
> manipulate the guests PSTATE.SS and MDSCR_EL1.SS bits which we do in the
> kvm_arm_setup/clear_debug() so we don't affect the apparent state of the
> guest. Additi
kvm_guest_debug *dbg)
> {
> - return -EINVAL;
> + if (dbg->control & ~KVM_GUESTDBG_VALID_MASK)
> + return -EINVAL;
> +
> + if (dbg->control & KVM_GUESTDBG_ENABLE) {
> + vcpu->gu
On Thu, May 07, 2015 at 10:07:11AM +0100, Alex Bennée wrote:
> This is a pre-cursor to sharing the code with the guest debug support.
> This replaces the big macro that fishes data out of a fixed location
> with a more general helper macro to restore a set of debug registers. It
> uses macro substi
On Thu, May 07, 2015 at 10:07:12AM +0100, Alex Bennée wrote:
> This adds support for userspace to control the HW debug registers for
> guest debug. In the debug ioctl we copy the IMPDEF defined number of
> registers into a new register set called host_debug_state. There is now
> a new vcpu paramete
On Wed, May 06, 2015 at 05:23:15PM +0100, Alex Bennée wrote:
> Hi,
>
> Here is V3 of the KVM Guest Debug support for arm64.
>
> This sees the return of hyp.S re-factoring code which has been
> expanded to handle both the save and restore legs. The HW debug patch
> then adds a simple indirection t
On Thu, May 07, 2015 at 10:07:13AM +0100, Alex Bennée wrote:
> When we are using the hardware registers for guest debug we need to deal
> with the guests access to them. There is already a mechanism for dealing
> with these accesses so we build on top of that.
>
> - any access to mdscr_el1 is no
On Thu, May 07, 2015 at 10:07:14AM +0100, Alex Bennée wrote:
> Finally advertise the KVM capability for SET_GUEST_DEBUG. Once arm
> support is added this check can be moved to the common
> kvm_vm_ioctl_check_extension() code.
>
> Signed-off-by: Alex Bennée
>
Acked-by
On Thu, May 07, 2015 at 10:07:15AM +0100, Alex Bennée wrote:
> This includes trace points for:
> kvm_arch_setup_guest_debug
> kvm_arch_clear_guest_debug
> kvm_handle_guest_debug
>
> I've also added some generic register setting trace events and also a
> trace point to dump the array of hardw
On Fri, May 08, 2015 at 05:08:42PM +0100, Russell King wrote:
> BSYM() should only be used when refering to local symbols in the same
> assembly file which are resolved by the assembler, and not for
> linker-fixed up symbols. The use of BSYM() with panic is incorrect as
> the linker is involved in
On Sat, May 09, 2015 at 09:10:57PM +0100, Russell King - ARM Linux wrote:
> On Sat, May 09, 2015 at 10:07:17PM +0200, Christoffer Dall wrote:
> > On Fri, May 08, 2015 at 05:08:42PM +0100, Russell King wrote:
> > > BSYM() should only be used when refering to local symbols in the s
On Sat, May 09, 2015 at 10:10:56PM +0200, Ard Biesheuvel wrote:
> On 9 May 2015 at 22:07, Christoffer Dall wrote:
> > On Fri, May 08, 2015 at 05:08:42PM +0100, Russell King wrote:
> >> BSYM() should only be used when refering to local symbols in the same
> >> assembly
On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
> Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
> needed by ARM. This flag informs KVM that the given memory region
> is typically mapped by the guest as non-cacheable. KVM for ARM
> then ensures that that memory is inde
VM userspace access to it so that it may use it for hinting
> likely problematic regions. Also rename to KVM_MEM_UNCACHED.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Christoffer Dall
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On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
> When S1 and S2 memory attributes combine wrt to caching policy,
> non-cacheable types take precedence. If a guest maps a region as
> device memory, which KVM userspace is using to emulate the device
> using normal, cacheable memory, th
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
> Provide a method to change normal, cacheable memory to non-cacheable.
> KVM will make use of this to keep emulated device memory regions
> coherent with the guest.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Christo
On Fri, Mar 27, 2015 at 01:09:24PM +, Marc Zyngier wrote:
> Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF)
> to indicate that we have a system register GIC CPU interface
>
> This will help KVM switching to alternative instruction patching.
>
> Reviewed-by: Andre Przywara
> Ac
On Thu, May 14, 2015 at 01:09:34PM +0200, Laszlo Ersek wrote:
> On 05/14/15 12:30, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
> >> Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
> >> needed by ARM. This flag
On Thu, May 14, 2015 at 01:31:03PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 13:29, Christoffer Dall wrote:
> > > (It's probably worth looking at the documentation in the first hunk too,
> > > under the commit message.)
> >
> > Why is this a hac
change),
> and it makes sense to rely on the instruction patching instead.
>
> This leads to a nice cleanup of the code.
>
> Acked-by: Will Deacon
> Signed-off-by: Marc Zyngier
I gave this a quick spin on Juno as well and works as expecte
On Thu, May 14, 2015 at 01:38:38PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 13:36, Christoffer Dall wrote:
> > > > > (It's probably worth looking at the documentation in the first hunk
> > > > > too,
> > > > > under the commi
On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 14:00, Christoffer Dall wrote:
> > So, getting back to my original question. Is the point then that UEFI
> > must assume (from ACPI/DT) the cache-coherency properties of the PCI
> >
On Thu, May 14, 2015 at 02:28:49PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 14:24, Christoffer Dall wrote:
> > On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
> >>
> >>
> >> On 14/05/2015 14:00, Christoffer Dall wrote:
> >>
On Thu, May 14, 2015 at 03:46:44PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
> > > Provide a method to change normal, cacheable memory to non-cacheable.
> >
On Thu, May 14, 2015 at 03:32:13PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
> > > When S1 and S2 memory attributes combine wrt to caching policy,
> > &g
On Thu, May 14, 2015 at 03:36:37PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 02:11:59PM +0100, Peter Maydell wrote:
> > On 14 May 2015 at 14:03, Andrew Jones wrote:
> > > On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
> > >> On 14 May 2015 at 11:31, Andrew Jones wrote:
On Fri, May 15, 2015 at 01:43:57PM +0200, Laszlo Ersek wrote:
> On 05/07/15 19:01, Paolo Bonzini wrote:
> >
> >
> > On 07/05/2015 18:56, Jérémy Fanguède wrote:
> >> USB devices fail with a timeout error, as if the communication between
> >> the kernel and the devices fail at a certain point:
> >>
On Tue, May 19, 2015 at 12:18:54PM +0100, Catalin Marinas wrote:
> On Tue, May 19, 2015 at 11:03:22AM +0100, Andrew Jones wrote:
> > On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote:
> > > Another way would be to split the vma containing the non-cacheable
> > > memory so that you get
On Wed, May 06, 2015 at 05:39:28PM +0100, Peter Maydell wrote:
> On 6 May 2015 at 17:33, Peter Maydell wrote:
> > On 27 April 2015 at 18:31, Christoffer Dall
> > wrote:
> >> Now when we have a host generic PCIe controller in the virt board, it
> >> would be ni
Add a GICv2m device to the virt board to enable MSIs on the generic PCI
host controller. We allocate 64 SPIs in the IRQ space for now (this can
be increased/decreased later) and map the GICv2m right after the GIC in
the memory map.
Signed-off-by: Christoffer Dall
---
Changes since v2
to add the
v2m node as a child of the gic node.
Note that we must also expand the irq-map to reference the gic with the
right address-cells as a consequnce of this change.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christoffer Dall
---
Changes since v2:
- New separate patch factoring out
verifying MSIs going through as
expected.
See the individual patches for changelogs.
Christoffer Dall (3):
target-arm: Add GIC phandle to VirtBoardInfo
arm_gicv2m: Add GICv2m widget to support MSIs
target-arm: Add the GICv2m to the virt board
Shanker Donthineni (1):
target-arm: Extend th
index
into our frame of SPIs.
When instantiating a GICv2m device, tell PCI that we have instantiated
something that can deal with MSIs. We rely on the board actually wiring
up the GICv2m to the PCI host controller.
Signed-off-by: Christoffer Dall
---
Changes since v2:
- Renamed QOM type to "
ed-by: Peter Maydell
Signed-off-by: Christoffer Dall
---
Changes since v2:
- None
Changes since v1:
- Added reviewed-by tag
hw/arm/virt.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a7f9a10..f9f7482 100644
---
Hi Pavel,
On Mon, May 25, 2015 at 04:09:58PM +0300, Pavel Fedin wrote:
> Hello!
>
> > typedef struct MemMapEntry {
> > @@ -88,6 +90,7 @@ typedef struct VirtBoardInfo {
> > int fdt_size;
> > uint32_t clock_phandle;
> > uint32_t gic_phandle;
> > +uint32_t v2m_phandle;
> > } Vi
se the arm/arm64 implementation of
local_irq_(en/dis)able has an implicit barrier.
At the same time, move the trace_kvm_exit() call outside of the atomic
section, since there is no reason for us to do that with interrupts
disabled.
Signed-off-by: Christoffer Dall
---
This patch is based on
On Thu, May 28, 2015 at 10:27:14AM +0100, Marc Zyngier wrote:
> On 14/05/15 12:25, Christoffer Dall wrote:
> > On Fri, Mar 27, 2015 at 01:09:24PM +, Marc Zyngier wrote:
> >> Add a new item to the feature set (ARM64_HAS_SYSREG_GIC_CPUIF)
> >> to indicate that we hav
On Thu, May 28, 2015 at 02:49:09PM +0200, Christoffer Dall wrote:
> Until now we have been calling kvm_guest_exit after re-enabling
> interrupts when we come back from the guest, but this has the
> unfortunate effect that CPU time accounting done in the context of timer
> interr
ince there is no reason for us to do that with interrupts
disabled.
Signed-off-by: Christoffer Dall
---
This patch is based on kvm/queue, because it has the kvm_guest_enter/exit
rework recently posted by Christian Borntraeger. I hope I got the logic
of this right, there were 2 slightly worrying f
verifying MSIs going through as
expected.
Rebased on target-arm.next, see the individual patches for detailed
changelogs.
Christoffer Dall (4):
target-arm: Add GIC phandle to VirtBoardInfo
arm_gicv2m: Add GICv2m widget to support MSIs
target-arm: Extend the gic node properties
target-ar
Add a GICv2m device to the virt board to enable MSIs on the generic PCI
host controller. We allocate 64 SPIs in the IRQ space for now (this can
be increased/decreased later) and map the GICv2m right after the GIC in
the memory map.
Reviewed-by: Eric Auger
Signed-off-by: Christoffer Dall
child of the gic node.
Note that we must also expand the irq-map to reference the gic with the
right address-cells as a consequence of this change.
Reviewed-by: Eric Auger
Suggested-by: Shanker Donthineni
Signed-off-by: Christoffer Dall
---
Changes since v3:
- Rewrote patch and changed
index
into our frame of SPIs.
When instantiating a GICv2m device, tell PCI that we have instantiated
something that can deal with MSIs. We rely on the board actually wiring
up the GICv2m to the PCI host controller.
Reviewed-by: Eric Auger
Signed-off-by: Christoffer Dall
---
Changes since v3:
-
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