y not hit them again.
Signed-off-by: James Morse
---
arch/arm64/kvm/handle_exit.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 7debb74843a0..345fdbba6c2e 100644
--- a/arch/arm64/kvm/handle_exit.c
Hi gengdongjiu,
On 25/09/17 16:13, gengdongjiu wrote:
> On 2017/9/23 0:39, James Morse wrote:
>> On 18/09/17 14:36, gengdongjiu wrote:
>>> On 2017/9/14 21:00, James Morse wrote:
>>>> On 13/09/17 08:32, gengdongjiu wrote:
>>> Then for "BUS_MCEERR_AO&
Hi gengdongjiu,
On 27/09/17 12:07, gengdongjiu wrote:
> On 2017/9/23 0:51, James Morse wrote:
>> If this wasn't a firmware-first notification, then you're right KVM hands the
>> guest an asynchronous external abort. This could be considered a bug in KVM.
>> (
Hi Marc,
On 11/10/17 10:01, Marc Zyngier wrote:
> On Thu, Oct 05 2017 at 8:18:01 pm BST, James Morse
> wrote:
>> Non-VHE systems take an exception to EL2 in order to world-switch into the
>> guest. When returning from the guest KVM implicitly restores the DAIF
>> flag
Hi Julien,
On 11/10/17 17:30, Julien Thierry wrote:
> On 05/10/17 20:17, James Morse wrote:
>> There are a few places where we want to mask all exceptions. Today we
>> do this in a piecemeal fashion, typically we expect the caller to
>> have masked irqs and the arch code m
Hi Julien,
On 11/10/17 18:13, Julien Thierry wrote:
> On 05/10/17 20:18, James Morse wrote:
>> Following our 'dai' order, irqs should be processed with debug and
>> serror exceptions unmasked.
>> > Add a helper to unmask these two, (and fiq for good measure)
Hi Marc,
On 11/10/17 11:37, Marc Zyngier wrote:
> On Thu, Oct 05 2017 at 8:18:11 pm BST, James Morse
> wrote:
>> We expect to have firmware-first handling of RAS SErrors, with errors
>> notified via an APEI method. For systems without firmware-first, add
>> some
Hi Catalin,
On 13/10/17 16:31, Catalin Marinas wrote:
> On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote:
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index cd52d365d1f0..8e4c7da2b126 100644
>> --- a/arch/arm64/kernel/cpufe
Hi gengdongjiu,
On 13/10/17 10:25, gengdongjiu wrote:
> After checking this patch, I think my patch[1] already include this
> logic(only a little
> difference).
Your kvm_handle_guest_sei() is similar to where this series ends up, but the
purpose of this patch is to keep KVMs existing behaviour.
Hi gengdongjiu,
On 14/09/17 12:12, gengdongjiu wrote:
> On 2017/9/8 0:31, James Morse wrote:
>> KVM already handles external aborts from lower exception levels, no more work
>> needs doing for TEA.
> If it is firmware first solution, that is SCR_EL3.EA=1, all SError interrupt
Hi gengdongjiu,
On 16/10/17 04:17, gengdongjiu wrote:
>> In fact I have below method for that, what do you think about that?
>>
>> 1. If there is no RAS, old method, directly inject virtual SError, not need
>> to specify ESR, as shown in the [1]
>> 2. If there is RAS, KVM set "the kvm_run" gues
Hi gengdongjiu,
On 15/10/17 17:09, gengdongjiu wrote:
>> On 13/10/17 10:25, gengdongjiu wrote:
>>> In my first version patch [2], It sets the virtual ESR in the KVM, but
>>> Marc and other people disagree that[3][4],and propose to set its value
>>> and injection by userspace(when RAS is enabled).
Hi Catalin,
On 16/10/17 14:41, Catalin Marinas wrote:
> On Fri, Sep 22, 2017 at 07:26:10PM +0100, James Morse wrote:
>> diff --git a/arch/arm64/kernel/sdei-entry.S b/arch/arm64/kernel/sdei-entry.S
>> new file mode 100644
>> index ..cf12f8da0789
>> --- /d
Hi Catalin,
On 13/10/17 16:42, Catalin Marinas wrote:
> On Fri, Sep 22, 2017 at 07:26:09PM +0100, James Morse wrote:
>> diff --git a/arch/arm64/include/asm/vmap_stack.h
>> b/arch/arm64/include/asm/vmap_stack.h
>> new file mode 100644
>> index ..f41d043cac3
Hi Catalin,
On 16/10/17 14:52, Catalin Marinas wrote:
> On Fri, Sep 22, 2017 at 07:26:11PM +0100, James Morse wrote:
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index f24bfb2b9a2d..466b949474df 100644
>> --- a/include/linux/cpuhotplug.h
&
Hi Catalin,
On 16/10/17 10:58, Catalin Marinas wrote:
> On Fri, Oct 13, 2017 at 05:50:45PM +0100, James Morse wrote:
>> On 13/10/17 16:31, Catalin Marinas wrote:
>>> On Fri, Sep 22, 2017 at 07:26:05PM +0100, James Morse wrote:
>>>> diff --git a/arch/arm64/kernel/c
ccess any
per-cpu variables. To allow this on systems with vhe we need to make
the host use tpidr_el2, saving KVM from save/restoring it.
__guest_enter() stores the host_ctxt on the stack, do the same with
the vcpu.
Signed-off-by: James Morse
Reviewed-by: Christoffer Dall
---
Changes sin
Now that KVM uses tpidr_el2 in the same way as Linux's cpu_offset in
tpidr_el1, merge the two. This saves KVM from save/restoring tpidr_el1
on VHE hosts, and allows future code to blindly access per-cpu variables
without triggering world-switch.
Signed-off-by: James Morse
Review
the SDE firmware interface.
Signed-off-by: James Morse
Acked-by: Rob Herring
---
Changes since v2:
* Added Rob's Ack
* Fixed 'childe node' typo
Changes since v1:
* Added bound IRQ description for binding,
* Reference SMC-CC, not 'AAPCS like'
* Move sdei node under fi
will make this unnecessary for VHE hosts)
We print out the vcpu pointer as part of the panic message. Add a back
reference to the 'running vcpu' in the host cpu context to preserve this.
Signed-off-by: James Morse
Reviewed-by: Christoffer Dall
---
Changes since v1:
* Added a co
.
Signed-off-by: James Morse
---
Changes since v3:
* Added BUILD_BUG() instead of a spooky link error
arch/arm64/include/asm/vmap_stack.h | 38 +
arch/arm64/kernel/irq.c | 13 ++---
2 files changed, 40 insertions(+), 11 deletions(-)
create mode
been initialised
so that we can parse the table, but before GHES devices are created, which
may register SDE events if they use SDEI as their notification type.
Signed-off-by: James Morse
---
drivers/firmware/arm_sdei.c | 41 -
1 file changed, 40 insertions(
will be added by later patches.
Signed-off-by: James Morse
---
Changes since v3:
* Depend on arm64 from the beginning, add a placeholder arch asm file.
* Added MAINTAINER record
* Renamed sdei.h files to arm_sdei.h
* Removed IS_SDEI_CALL(), KVM won't need this...
Changes since v2:
* Cop
es
[Changes since previous versions are noted on each patch]
James Morse (13):
KVM: arm64: Store vcpu on the stack during __guest_enter()
KVM: arm/arm64: Convert kvm_host_cpu_state to a static per-cpu
allocation
KVM: arm64: Change hyp_panic()s dependency on tpidr_el2
arm64: alternatives:
kvm_host_cpu_state is a per-cpu allocation made from kvm_arch_init()
used to store the host EL1 registers when KVM switches to a guest.
Make it easier for ASM to generate pointers into this per-cpu memory
by making it a static allocation.
Signed-off-by: James Morse
Acked-by: Christoffer Dall
en if we interrupted the kernel, in this case
the code in entry.S will save/restore sp_el0 and use the value in
__entry_task.
When we have VMAP stacks we can interrupt the stack-overflow test, which
stirs x0 into sp, meaning we have to have our own VMAP stack.
Signed-off-by: James Morse
-registered when the CPU is brought back online. This saves bringing
secondary cores back online to call private_reset() on shutdown, kexec
and resume from hibernate.
Signed-off-by: James Morse
---
drivers/firmware/arm_sdei.c | 242 +---
1 file changed, 228
fiers necessary to do this. We only support shared events
so all events are left registered and enabled over CPU hotplug.
Signed-off-by: James Morse
---
Changes since v3:
* Renamed CPUHP enum entry to have an ARM_ prefix.
drivers/firmware/arm_sdei.c
SDEI inherits the 'use hvc' bit that is also used by PSCI. PSCI does all
its initialisation early, SDEI does its late.
Remove the __init annotation from acpi_psci_use_hvc().
Signed-off-by: James Morse
---
The function name is unchanged as this bit is named 'PSCI_USE_HVC&#x
opy into kvm-init instead.
Signed-off-by: James Morse
Reviewed-by: Christoffer Dall
---
Changes since v1:
* Switched KVM<->arm64 in the subject.
arch/arm64/kvm/hyp-init.S | 4
arch/arm64/kvm/hyp/s2-setup.c | 3 ---
arch/arm64/kvm/hyp/sysreg-sr.c | 16
3 file
Hi Vladimir,
On 11/10/17 13:19, Vladimir Murzin wrote:
> Common Not Private (CNP) is a feature of ARMv8.2 extension which
> allows translation table entries to be shared between different PEs in
> the same inner shareable domain, so the hardware can use this fact to
> optimise the caching of such
Hi Catalin,
On 18/10/17 17:43, Catalin Marinas wrote:
> On Thu, Oct 05, 2017 at 08:18:05PM +0100, James Morse wrote:
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index b68f5e93baac..29df2a93688c 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/K
Hi Dongjiu Geng,
On 17/10/17 15:14, Dongjiu Geng wrote:
> ARMv8.2 adds a new bit HCR_EL2.TEA which controls to
> route synchronous external aborts to EL2, and adds a
> trap control bit HCR_EL2.TERR which controls to
> trap all Non-secure EL1&0 error record accesses to EL2.
The bulk of this patch
.
FIQ is never expected, but we mask it when we mask debug exceptions, and
unmask it at all other times.
Given masking debug exceptions masks everything, we don't need macros
to save/restore that bit independently. Remove them and switch the last
caller over to use the daif calls.
Signed-off-by: J
tention by adding
helpers to do exactly that.
This will let us unmask SError without having to add 'oh and SError'
to these paths.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
Remove the disable IRQs comment above cpu_die(): we return from
iu Geng (1):
KVM: arm64: Trap RAS error registers and set HCR_EL2's TERR & TEA
James Morse (18):
arm64: explicitly mask all exceptions
arm64: introduce an order for exceptions
arm64: Move the async/fiq helpers to explicitly set process context
flags
arm64: Mask all exceptions
andle interrupts.
The boot CPU unmasks SError during early boot once it can print an error
message. If we can print an error message about SError, we can do the
same for FIQ. Debug exceptions are already enabled by __cpu_setup(),
which has also configured MDSCR_EL1 to disable MDE and KDE.
Signed-off-by:
the end
of the ret_to_user loop, which has already masked all exceptions so this
is no longer needed.
Remove disable_dbg, add a comment that enable_step_tsk's caller should
have masked debug.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
arch/arm64/include
avoids an extra pstate-write.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
Changes since v3:
* swapped verb/daif word-order.
arch/arm64/kernel/entry.S | 10 +-
arch/arm64/kernel/signal.c | 8 ++--
2 files changed, 11 insertions(+), 7 del
r symmetry.
Signed-off-by: James Morse
---
Give me a kick if you want this reworked as a fix (which will then
conflict with this series), or a backportable version.
arch/arm64/include/asm/kvm_host.h | 10 ++
virt/kvm/arm/arm.c| 4
2 files changed, 14 insertions(+)
expect firmware to have handled any deferred SError. By the
same logic we clear DISR in the idle path.
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/assembler.h | 7 +++
arch/arm64/include/asm/esr.h | 7 +++
arch/arm64/include/asm/exception.h
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
arch/arm64/Kconfig | 16
arch/arm64/include/asm/barrier.h | 1 +
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 2 ++
arch/arm64/kernel/cpufeature.c | 13 +
panic(), even if we received
a corrected error. Add code to decode the severity of RAS errors. We can
safely ignore contained errors where the CPU can continue to make
progress. For all other errors we continue to panic().
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
I couldn'
t may require additional firmware support.
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
Note the sneaky KVM change,
Changes since v3:
* removed IESB Kconfig option
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/processor.h
d.
For the other cases we can inherit whatever we interrupted.
Add a macro inherit_daif to set daif based on the interrupted pstate.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/assembler.h | 6 ++
arch/arm64/kern
patch, added compat path, renamed, enabled debug
exceptions]
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
arch/arm64/Kconfig| 2 +-
arch/arm64/kernel/entry.S | 36 +---
arch/arm64/kernel/traps.c | 13 +
3 files changed, 43
the other cases we can unmask
everything. This changes the behaviour of fpsimd_{acc,exc} and el0_inv
which previously ran with irqs masked.
This patch removed the last user of enable_dbg_and_irq, remove it.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
SError and decode its severity.
Signed-off-by: James Morse
---
arch/arm64/kvm/hyp/switch.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index af37658223a0..cba6d8ac105c 100644
--- a/arch/arm64/kvm/hyp/swit
Following our 'dai' order, irqs should be processed with debug and
serror exceptions unmasked.
Add a helper to unmask these two, (and fiq for good measure).
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
Changes since v3:
* Added comme
his bit during __deactivate_traps() and hardware clears the
bit once the guest has consumed the virtual-SError.
Future patches may add an API (or KVM CAP) to pend a virtual SError with
a specified ESR.
Cc: Dongjiu Geng
Signed-off-by: James Morse
---
arch/arm64/include/asm/kvm_emulate.h | 5 +++
Use the alternatives to synchronise and consume any SError using ESB
instead of unmasking and taking the SError. Set ARM_EXIT_WITH_SERROR_BIT
in the exit_code so that we can restart the vcpu if it turns out this
SError has no impact on the vcpu.
Signed-off-by: James Morse
---
Changes since v3:
* Move
y not hit them again.
Signed-off-by: James Morse
---
arch/arm64/kvm/handle_exit.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 7debb74843a0..345fdbba6c2e 100644
--- a/arch/arm64/kvm/handle_exit.c
hing,
rephrased parts of the commit message]
Signed-off-by: James Morse
---
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/include/asm/kvm_emulate.h | 7 +++
arch/arm64/include/asm/sysreg.h | 10 ++
arch/arm64/kvm/sys_regs.c| 10 ++
4 files changed
any RAS errors to be synchronised and taken on the host before
we enter world switch.
RAS errors that become pending during world switch are still taken
once we enter the guest.
Signed-off-by: James Morse
---
arch/arm64/include/asm/kvm_host.h | 1 +
1 file changed, 1 insertion(+)
diff --git a
userspace as DISR_EL1.
Signed-off-by: James Morse
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kvm/hyp/sysreg-sr.c| 6 ++
arch/arm64/kvm/sys_regs.c | 1 +
4 files changed, 9 insertions(+)
diff --git a/arch/arm64/include/asm
Hi gengdongjiu,
On 20/10/17 17:44, gengdongjiu wrote:
> 2017-10-19 22:58 GMT+08:00 James Morse :
>> Prior to v8.2's RAS Extensions, the HCR_EL2.VSE 'virtual SError' feature
>> generated an SError with an implementation defined ESR_EL1.ISS, because we
>> had n
Hi Will,
On 18/10/17 18:19, Will Deacon wrote:
> On Tue, Oct 17, 2017 at 06:44:30PM +0100, James Morse wrote:
>> Private SDE events are per-cpu, and need to be registered and enabled
>> on each CPU.
>>
>> Hide this detail from the caller by adapting our {,un}register a
Hi Will,
On 18/10/17 18:17, Will Deacon wrote:
> On Tue, Oct 17, 2017 at 06:44:29PM +0100, James Morse wrote:
>> When a CPU enters an idle lower-power state or is powering off, we
>> need to mask SDE events so that no events can be delivered while we
>> are messing with the
Hi gengdongjiu,
On 20/10/17 16:33, gengdongjiu wrote:
> As we discuss below solution:
> When guest happen SEA/SEI, KVM calls memory_failure() to send an asynchronous
> SIGBUS
> signal(BUS_MCEERR_AO) to QEMU, and make this address to poisoned.
> after QEMU receive this BUS_MCEERR_AO, it will recor
Hi gengdongjiu,
On 27/10/17 07:26, gengdongjiu wrote:
> On 2017/10/19 22:58, James Morse wrote:
>> +alternative_if ARM64_HAS_RAS_EXTN
>> +// If we have the RAS extensions we can consume a pending error
>> +// without an unmask-SError and isb.
>> +esb
>&
Hi Christoffer,
On 30/10/17 10:51, Christoffer Dall wrote:
> On Mon, Oct 30, 2017 at 08:59:51AM +0100, Christoffer Dall wrote:
>> On Thu, Oct 19, 2017 at 03:58:01PM +0100, James Morse wrote:
>>> Prior to v8.2's RAS Extensions, the HCR_EL2.VSE 'virtual SError' fea
ation last and switch to the
vanilla version that makes the call for all online CPUs. Add a call
to forcibly mask CPUs in the error path.
Suggested-by: Will Deacon
Signed-off-by: James Morse
---
drivers/firmware/arm_sdei.c | 24
1 file changed, 12 insertions(+), 12 dele
Hi Christoffer,
On 31/10/17 06:23, Christoffer Dall wrote:
> On Thu, Oct 19, 2017 at 03:58:06PM +0100, James Morse wrote:
>> On VHE systems KVM masks SError before switching the VBAR value. Any
>> host RAS error that the CPU knew about before world-switch may become
>> pendin
Hi Dongjiu Geng,
On 01/11/17 19:14, Dongjiu Geng wrote:
> Some hardware platform can support RAS Extension, but not support IESB,
> such as Huawei's platform, so software need to insert Synchronization Barrier
> operations at exception handler entry.
>
> This series patches are based on James's
Hi guys,
On 31/10/17 10:08, Will Deacon wrote:
> On Tue, Oct 31, 2017 at 07:35:35AM +0100, Christoffer Dall wrote:
>> On Thu, Oct 19, 2017 at 03:57:46PM +0100, James Morse wrote:
>>> The aim of this series is to enable IESB and add ESB-instructions to let us
>>> kick
Hi Will,
On 24/10/17 18:34, James Morse wrote:
> On 18/10/17 18:19, Will Deacon wrote:
>> On Tue, Oct 17, 2017 at 06:44:30PM +0100, James Morse wrote:
>>> Private SDE events are per-cpu, and need to be registered and enabled
>>> on each CPU.
>>>
>>>
ing on cpu-hotplug's
mechanics to ensure the callback sees the correct value.
Reported-by: Will Deacon
Signed-off-by: James Morse
---
drivers/firmware/arm_sdei.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/arm_sdei.c b/drivers/
Hi Marc,
On 31/10/17 05:47, Marc Zyngier wrote:
> On Tue, Oct 31 2017 at 4:26:01 am GMT, Marc Zyngier
> wrote:
>> On Thu, Oct 19 2017 at 4:58:03 pm BST, James Morse
>> wrote:
>>> When we exit a guest due to an SError the vcpu fault info isn't updated
>
tention by adding
helpers to do exactly that.
This will let us unmask SError without having to add 'oh and SError'
to these paths.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
==
Remove the disable IRQs comment above cpu_die(): we return from
Hello,
This is repost of the SError Rework bits of the bigger series [0].
None of these patches have changed since v3.
Thanks,
James
[0] https://www.spinics.net/lists/arm-kernel/msg612870.html
James Morse (8):
arm64: explicitly mask all exceptions
arm64: introduce an order for
.
FIQ is never expected, but we mask it when we mask debug exceptions, and
unmask it at all other times.
Given masking debug exceptions masks everything, we don't need macros
to save/restore that bit independently. Remove them and switch the last
caller over to use the daif calls.
Signed-off-by: J
the end
of the ret_to_user loop, which has already masked all exceptions so this
is no longer needed.
Remove disable_dbg, add a comment that enable_step_tsk's caller should
have masked debug.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
arch/arm64/include
andle interrupts.
The boot CPU unmasks SError during early boot once it can print an error
message. If we can print an error message about SError, we can do the
same for FIQ. Debug exceptions are already enabled by __cpu_setup(),
which has also configured MDSCR_EL1 to disable MDE and KDE.
Signed-off-by:
avoids an extra pstate-write.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
==
Changes since v3:
* swapped verb/daif word-order.
---
arch/arm64/kernel/entry.S | 10 +-
arch/arm64/kernel/signal.c | 8 ++--
2 files changed, 11 insertions(
the other cases we can unmask
everything. This changes the behaviour of fpsimd_{acc,exc} and el0_inv
which previously ran with irqs masked.
This patch removed the last user of enable_dbg_and_irq, remove it.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
Following our 'dai' order, irqs should be processed with debug and
serror exceptions unmasked.
Add a helper to unmask these two, (and fiq for good measure).
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
==
Changes since v3:
* Added comme
d.
For the other cases we can inherit whatever we interrupted.
Add a macro inherit_daif to set daif based on the interrupted pstate.
Signed-off-by: James Morse
Reviewed-by: Julien Thierry
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/assembler.h | 6 ++
arch/arm64/kern
patch, added compat path, renamed, enabled debug
exceptions]
Signed-off-by: James Morse
Reviewed-by: Catalin Marinas
---
arch/arm64/Kconfig| 2 +-
arch/arm64/kernel/entry.S | 36 +---
arch/arm64/kernel/traps.c | 13 +
3 files changed, 43
Hi Christoffer,
On 30/10/17 07:40, Christoffer Dall wrote:
> On Thu, Oct 19, 2017 at 03:57:55PM +0100, James Morse wrote:
>> Non-VHE systems take an exception to EL2 in order to world-switch into the
>> guest. When returning from the guest KVM implicitly restores the DAIF
>>
Hi Will,
On 31/10/17 13:50, Will Deacon wrote:
> On Thu, Oct 19, 2017 at 03:57:58PM +0100, James Morse wrote:
>> Prior to v8.2, SError is an uncontainable fatal exception. The v8.2 RAS
>> extensions use SError to notify software about RAS errors, these can be
>> contained b
Hi Will,
On 31/10/17 13:14, Will Deacon wrote:
> On Thu, Oct 19, 2017 at 03:57:57PM +0100, James Morse wrote:
>> From: Xie XiuQi
>>
>> ARM's v8.2 Extentions add support for Reliability, Availability and
>> Serviceability (RAS). On CPUs with these extensions syste
Hi Christoffer,
On 01/11/17 04:55, Christoffer Dall wrote:
> On Tue, Oct 31, 2017 at 11:43:42AM +0000, James Morse wrote:
>> On 31/10/17 06:23, Christoffer Dall wrote:
>>> On Thu, Oct 19, 2017 at 03:58:06PM +0100, James Morse wrote:
>>>> On VHE systems KVM masks SE
Hi Christoffer,
On 03/11/17 12:49, Christoffer Dall wrote:
> Does a non-secure esb() cause the error to be delivered to firmware on
> the secure side if anything is pending?
Yes, the ESB-instruction causes 'synchronisable' errors to become pending as an
SError. They then follow the normal SError
Hi Christoffer,
On 03/11/17 12:45, Christoffer Dall wrote:
> On Thu, Nov 02, 2017 at 12:14:28PM +0000, James Morse wrote:
>> On 30/10/17 07:40, Christoffer Dall wrote:
>>> On Thu, Oct 19, 2017 at 03:57:55PM +0100, James Morse wrote:
>>>> Non-VHE systems take an exce
Hi gengdongjiu,
On 27/10/17 08:21, gengdongjiu wrote:
> On 2017/10/26 1:42, James Morse wrote:
>> On 20/10/17 16:33, gengdongjiu wrote:
>>> As we discuss below solution:
>>> When guest happen SEA/SEI, KVM calls memory_failure() to send an
>>> asynchronous SIGB
On 01/11/17 15:59, James Morse wrote:
> dpm_suspend() calls the freeze/thaw callbacks for hibernate before
> disable_non_bootcpus() takes down secondaries.
>
> This leads to a fun race where the freeze/thaw callbacks reset the
> SDEI interface (as we may be restoring a kernel w
move_state() to make it look like
secondary CPUs have gone offline.
Suggested-by: Will Deacon
Signed-off-by: James Morse
---
drivers/firmware/arm_sdei.c | 60 +++--
1 file changed, 31 insertions(+), 29 deletions(-)
diff --git a/drivers/firmware/arm_s
Hi Manoj,
On 08/11/17 19:05, Manoj Iyer wrote:
> On Thu, 2 Nov 2017, Shanker Donthineni wrote:
>> The ARM architecture defines the memory locations that are permitted
>> to be accessed as the result of a speculative instruction fetch from
>> an exception level for which all stages of translation a
Hi Shanker, Robin,
On 04/11/17 21:43, Shanker Donthineni wrote:
> On 11/03/2017 10:11 AM, Robin Murphy wrote:
>> On 03/11/17 03:27, Shanker Donthineni wrote:
>>> The ARM architecture defines the memory locations that are permitted
>>> to be accessed as the result of a speculative instruction fetch
Hi guys,
On 19/10/17 15:57, James Morse wrote:
> Known issues:
[...]
> * KVM-Migration: VDISR_EL2 is exposed to userspace as DISR_EL1, but how
> should
>HCR_EL2.VSE or VSESR_EL2 be migrated when the guest has an SError pending
> but
>hasn't taken it yet...?
I
Hi Shanker,
On 09/11/17 15:22, Shanker Donthineni wrote:
> On 11/09/2017 05:08 AM, James Morse wrote:
>> On 04/11/17 21:43, Shanker Donthineni wrote:
>>> On 11/03/2017 10:11 AM, Robin Murphy wrote:
>>>> On 03/11/17 03:27, Shanker Donthineni wrote:
>>>>
Hi Dongjiu Geng,
On 10/11/17 19:54, Dongjiu Geng wrote:
> If it is not RAS SError, directly inject virtual SError,
> which will keep the old way. If it is RAS SError, firstly
> let host ACPI module to handle it.
> For the ACPI handling,
> if the error address is invalid, APEI driver will not
> id
Hi Dongjiu Geng,
On 10/11/17 19:54, Dongjiu Geng wrote:
> This series patches mainly do below things:
>
> 1. Trap RAS ERR* registers Accesses to EL2 from Non-secure EL1,
>KVM will will do a minimum simulation, there registers are simulated
>to RAZ/WI in KVM.
> 2. Route synchronous Externa
Hi Christoffer,
On 13/11/17 11:29, Christoffer Dall wrote:
> On Thu, Nov 09, 2017 at 06:14:56PM +0000, James Morse wrote:
>> On 19/10/17 15:57, James Morse wrote:
>>> Known issues:
>> [...]
>>> * KVM-Migration: VDISR_EL2 is exposed to userspace as DISR_EL1, but h
Hi Drew,
On 13/11/17 16:14, Andrew Jones wrote:
> On Mon, Nov 13, 2017 at 12:29:46PM +0100, Christoffer Dall wrote:
>> On Thu, Nov 09, 2017 at 06:14:56PM +0000, James Morse wrote:
>>> On 19/10/17 15:57, James Morse wrote:
>>>> Known issues:
>>>> * KVM-Mi
Hi gengdongjiu,
On 15/11/17 09:15, gengdongjiu wrote:
> On 2017/11/15 0:03, James Morse wrote:
>>> Hope this helps?
>> Yes, I'll go looking for a way to expose VSESR_EL2 to user-space.
>
> what is the purpose to expose VSESR_EL2?
> do you mean set its value aft
Hi Christoffer,
On 23/11/17 20:59, Christoffer Dall wrote:
> On Thu, Oct 12, 2017 at 04:49:44PM +0100, Marc Zyngier wrote:
>> On 12/10/17 11:41, Christoffer Dall wrote:
>>> We already have the percpu area for the host cpu state, which points to
>>> the VCPU, so there's no need to store the VCPU po
,
James
[Changes since previous versions are noted on each patch]
[0] https://lkml.org/lkml/2017/12/6/306
[1] https://lkml.org/lkml/2017/12/6/340
James Morse (16):
KVM: arm64: Store vcpu on the stack during __guest_enter()
KVM: arm/arm64: Convert kvm_host_cpu_state to a static per-cpu
kvm_host_cpu_state is a per-cpu allocation made from kvm_arch_init()
used to store the host EL1 registers when KVM switches to a guest.
Make it easier for ASM to generate pointers into this per-cpu memory
by making it a static allocation.
Signed-off-by: James Morse
Acked-by: Christoffer Dall
Now that KVM uses tpidr_el2 in the same way as Linux's cpu_offset in
tpidr_el1, merge the two. This saves KVM from save/restoring tpidr_el1
on VHE hosts, and allows future code to blindly access per-cpu variables
without triggering world-switch.
Signed-off-by: James Morse
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