Re: [PATCH 1/2] arm64: KVM: Fix AArch32 to AArch64 register mapping

u_reg, particularly in the shared 32-bit code, this does seem to be the only one which involves a potentially-banked register number that didn't originally come from an ESR read, and thus needs translation. Reviewed-by: Robin Murphy <robin.mur...@arm.com> (unfortunately I don't

Re: [RFC v3 05/15] iommu/arm-smmu: implement alloc/free_reserved_iova_domain

Hi Eric, On 12/02/16 08:13, Eric Auger wrote: Implement alloc/free_reserved_iova_domain for arm-smmu. we use the iova allocator (iova.c). The iova_domain is attached to the arm_smmu_domain struct. A mutex is introduced to protect it. The IOMMU API currently leaves IOVA management entirely up

Re: [PATCH] arm64: KVM: Turn kvm_ksym_ref into a NOP on VHE

Hi Marc, On 18/03/16 17:25, Marc Zyngier wrote: When running with VHE, there is no need to translate kernel pointers to the EL2 memory space, since we're already there (and we have a much saner memory map to start with). Unfortunately, kvm_ksym_ref is getting in the way, and the first call

[PATCH v2] kvm: arm: Enforce some NS-SVC initialisation

getting away with it thanks to implementation details of ARMv7 cores and/or bootloader behaviour, but for the sake of forwards compatibility let's try to ensure that we have a minimally sane state before dropping down into it. Signed-off-by: Robin Murphy <robin.mur...@arm.com> --- v2: Init

Re: [PATCH] kvm: arm: Enforce some NS-SVC initialisation

Hi Marc, On 16/08/16 14:33, Marc Zyngier wrote: > On 21/07/16 13:01, Robin Murphy wrote: >> Since the non-secure copies of banked registers lack architecturally >> defined reset values, there is no actual guarantee when entering in Hyp >> from secure-only firmware that the

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On 05/12/16 08:09, Maninder Singh wrote: > This patch corrects format specifier for printing 64 bit addresses. > > Signed-off-by: Maninder Singh > Signed-off-by: Vaneet Narang > --- > arch/arm64/kernel/signal.c | 2 +- > arch/arm64/kvm/sys_regs.c

Re: [PATCH 1/1] arm64: Correcting format specifier for printing 64 bit addresses

On 06/12/16 16:11, Christoffer Dall wrote: > On Mon, Dec 05, 2016 at 01:39:53PM +0530, Maninder Singh wrote: >> This patch corrects format specifier for printing 64 bit addresses. >> >> Signed-off-by: Maninder Singh >> Signed-off-by: Vaneet Narang

Re: [PATCH 3/3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

Hi Marc, On 15/03/17 13:43, Marc Zyngier wrote: > On 15/03/17 13:35, Christoffer Dall wrote: >> On Wed, Mar 15, 2017 at 01:28:07PM +, Marc Zyngier wrote: >>> On 15/03/17 10:56, Christoffer Dall wrote: On Wed, Mar 15, 2017 at 09:39:26AM +, Marc Zyngier wrote: > On 15/03/17 09:21,

Re: [report] boot a vm that with PCI only hierarchy devices and with GICv3 , it's failed.

On 18/07/17 10:15, Marc Zyngier wrote: > On 18/07/17 05:07, wanghaibin wrote: >> Hi, all: >> >> I met a problem, I just try to test PCI only hierarchy devices model >> (qemu/docs/pcie.txt sections 2.3) >> >> Here is part of qemu cmd: >> -device i82801b11-bridge,id=pci.1,bus=pcie.0,addr=0x1

Re: [report] boot a vm that with PCI only hierarchy devices and with GICv3 , it's failed.

On 18/07/17 12:07, wanghaibin wrote: > On 2017/7/18 18:02, Robin Murphy wrote: > >> On 18/07/17 10:15, Marc Zyngier wrote: >>> On 18/07/17 05:07, wanghaibin wrote: >>>> Hi, all: >>>> >>>> I met a problem, I just try to test PCI only hierar

Re: [PATCH 3/3] arm64: Add software workaround for Falkor erratum 1041

On 03/11/17 03:27, Shanker Donthineni wrote: > The ARM architecture defines the memory locations that are permitted > to be accessed as the result of a speculative instruction fetch from > an exception level for which all stages of translation are disabled. > Specifically, the core is permitted to

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

On 01/11/17 19:14, Dongjiu Geng wrote: > ARMv8.2 adds a control bit to each SCTLR_ELx to insert implicit > Error Synchronization Barrier(IESB) operations at exception handler entry > and exit. But not all hardware platform which support RAS Extension > can support IESB. So for this case, software

Re: [PATCH v1 0/3] manually add Error Synchronization Barrier at exception handler entry and exit

On 01/11/17 19:14, Dongjiu Geng wrote: > Some hardware platform can support RAS Extension, but not support IESB, > such as Huawei's platform, so software need to insert Synchronization Barrier > operations at exception handler entry. > > This series patches are based on James's series patches

Re: [PATCH v1 1/3] arm64: add a macro for SError synchronization

On 01/11/17 12:54, gengdongjiu wrote: > Hi Robin, > > On 2017/11/1 19:24, Robin Murphy wrote: >>> + esb >>> +alternative_else_nop_endif >>> +1: >>> + .endm >> Having a branch in here is pretty horrible, and furthermore using label >>

Re: [PATCH 02/14] arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and EL1

On 24/05/18 11:52, Mark Rutland wrote: On Wed, May 23, 2018 at 10:23:20AM +0100, Julien Grall wrote: Hi Marc, On 05/22/2018 04:06 PM, Marc Zyngier wrote: diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index ec2ee720e33e..f33e6aed3037 100644 --- a/arch/arm64/kernel/entry.S

Re: [PATCH 14/14] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support

On 26/01/18 14:28, Marc Zyngier wrote: Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. It is lovely. Really. Signed-off-by: Marc Zyngier --- arch/arm64/kernel/bpi.S| 20 arch/arm64/kernel/cpu_errata.c | 71

Re: [PATCH v2 13/16] firmware/psci: Expose SMCCC version through psci_ops

On 29/01/18 17:45, Marc Zyngier wrote: Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed, let's do that at boot time, and expose the version of the calling convention as part of the psci_ops structure. Signed-off-by: Marc Zyngier ---

Re: [PATCH v2 04/16] arm/arm64: KVM: Add PSCI_VERSION helper

On 29/01/18 17:45, Marc Zyngier wrote: As we're about to trigger a PSCI version explosion, it doesn't hurt to introduce a PSCI_VERSION helper that is going to be used everywhere. Signed-off-by: Marc Zyngier --- include/kvm/arm_psci.h | 5 +++-- virt/kvm/arm/psci.c|

Re: [PATCH v2 10/16] arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support

On 29/01/18 17:45, Marc Zyngier wrote: A new feature of SMCCC 1.1 is that it offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for CVE-2017-5715. If the host has some mitigation for this issue, report that we deal with it using

Re: [PATCH v3 13/18] firmware/psci: Expose PSCI conduit

On 01/02/18 11:46, Marc Zyngier wrote: In order to call into the firmware to apply workarounds, it is useful to find out whether we're using HVC or SMC. Let's expose this through the psci_ops. Reviewed-by: Robin Murphy <robin.mur...@arm.com> Acked-by: Lorenzo Pieralisi <loren

Re: [PATCH v3 16/18] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive

"volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do {\ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(i

Re: [PATCH v3 16/18] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive

On 01/02/18 13:54, Marc Zyngier wrote: On 01/02/18 13:34, Robin Murphy wrote: On 01/02/18 11:46, Marc Zyngier wrote: One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline

Re: [PATCH v3 14/18] firmware/psci: Expose SMCCC version through psci_ops

e, this assignment now does precisely nothing. With the condition flipped and the redundant else case removed (or an explanation of why I'm wrong...) Reviewed-by: Robin Murphy <robin.mur...@arm.com> + else + psci_ops.smccc_version = SMCCC_VERSION_1_1;

Re: [PATCH v3 15/18] arm/arm64: smccc: Make function identifiers an unsigned quantity

ibly wrong. Reviewed-by: Robin Murphy <robin.mur...@arm.com> Cc: sta...@vger.kernel.org Reported-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheu...@linaro.org> Signed-off-by:

Re: [PATCH 1/2] ARM: kvm: fix building with gcc-8

On 02/02/18 15:55, Robin Murphy wrote: On 02/02/18 15:07, Arnd Bergmann wrote: In banked-sr.c, we use a top-level '__asm__(".arch_extension virt")' statement to allow compilation of a multi-CPU kernel for ARMv6 and older ARMv7-A that don't normally support access to the banked

Re: [PATCH 1/2] ARM: kvm: fix building with gcc-8

On 02/02/18 16:29, Arnd Bergmann wrote: On Fri, Feb 2, 2018 at 5:23 PM, Robin Murphy <robin.mur...@arm.com> wrote: On 02/02/18 15:55, Robin Murphy wrote: On 02/02/18 15:07, Arnd Bergmann wrote: In banked-sr.c, we use a top-level '__asm__(".arch_extension virt")' st

Re: [PATCH 1/2] ARM: kvm: fix building with gcc-8

On 02/02/18 15:07, Arnd Bergmann wrote: In banked-sr.c, we use a top-level '__asm__(".arch_extension virt")' statement to allow compilation of a multi-CPU kernel for ARMv6 and older ARMv7-A that don't normally support access to the banked registers. This is considered to be a programming error

Re: [PATCH v2 15/16] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive

On 29/01/18 17:45, Marc Zyngier wrote: One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the

Re: [PATCH 4/4] vfio: Allow type-1 IOMMU instantiation with a virtio-iommu

On 14/02/18 15:26, Alex Williamson wrote: On Wed, 14 Feb 2018 14:53:40 + Jean-Philippe Brucker wrote: When enabling both VFIO and VIRTIO_IOMMU modules, automatically select VFIO_IOMMU_TYPE1 as well. Signed-off-by: Jean-Philippe Brucker

Re: [PATCH v1 02/16] irqchip: gicv3-its: Add helpers for handling 52bit address

On 08/02/18 11:20, Suzuki K Poulose wrote: On 07/02/18 15:10, Christoffer Dall wrote: Hi Suzuki, On Tue, Jan 09, 2018 at 07:03:57PM +, Suzuki K Poulose wrote: Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER register. When ITS uses 64K page size, the 52bits of physical

Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

On 22/02/18 16:33, Mark Rutland wrote: On Thu, Feb 22, 2018 at 04:28:03PM +, Robin Murphy wrote: [Apologies to keep elbowing in, and if I'm being thick here...] On 22/02/18 15:22, Mark Rutland wrote: On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: +#define

Re: [PATCH v4] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

[Apologies to keep elbowing in, and if I'm being thick here...] On 22/02/18 15:22, Mark Rutland wrote: On Thu, Feb 22, 2018 at 08:51:30AM -0600, Shanker Donthineni wrote: +#define CTR_B31_SHIFT 31 Since this is just a RES1 bit, I think we don't need a mnemonic for it, but I'll defer

Re: [PATCH v3] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

On 21/02/18 16:14, Shanker Donthineni wrote: [...] @@ -1100,6 +1114,20 @@ static int cpu_copy_el2regs(void *__unused) .enable = cpu_clear_disr, }, #endif /* CONFIG_ARM64_RAS_EXTN */ +#ifdef CONFIG_ARM64_SKIP_CACHE_POU + { + .desc = "DCache clean to

Re: [PATCH v2 1/5] dt-bindings: virtio: Specify #iommu-cells value for a virtio-iommu

On 27/06/18 18:46, Rob Herring wrote: On Tue, Jun 26, 2018 at 11:59 AM Jean-Philippe Brucker wrote: On 25/06/18 20:27, Rob Herring wrote: On Thu, Jun 21, 2018 at 08:06:51PM +0100, Jean-Philippe Brucker wrote: A virtio-mmio node may represent a virtio-iommu device. This is discovered by the

Re: [PATCH v6] arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

On 01/03/18 04:14, Shanker Donthineni wrote: [...] diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2985a06..0b64b55 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -199,12 +199,12 @@ static int __init

Re: [PATCH] KVM: arm/arm64: replacing per-VM's per-CPU variable

On 13/03/18 13:01, Marc Zyngier wrote: [You're repeatedly posting to the kvmarm mailing list without being subscribed to it. I've flushed the queue now, but please consider subscribing to the list, it will help everyone] On 13/03/18 21:03, Peng Hao wrote: Using a global per-CPU variable

Re: [PATCH 1/4] iommu: Add virtio-iommu driver

On 21/03/18 13:14, Jean-Philippe Brucker wrote: On 21/03/18 06:43, Tian, Kevin wrote: [...] + +#include + +#define MSI_IOVA_BASE 0x800 +#define MSI_IOVA_LENGTH0x10 this is ARM specific, and according to virtio-iommu spec isn't it better probed

Re: [PATCH 2/4] iommu/virtio: Add probe request

On 14/02/18 14:53, Jean-Philippe Brucker wrote: When the device offers the probe feature, send a probe request for each device managed by the IOMMU. Extract RESV_MEM information. When we encounter a MSI doorbell region, set it up as a IOMMU_RESV_MSI region. This will tell other subsystems that

Re: [PATCH 1/4] iommu: Add virtio-iommu driver

On 14/02/18 14:53, Jean-Philippe Brucker wrote: The virtio IOMMU is a para-virtualized device, allowing to send IOMMU requests such as map/unmap over virtio-mmio transport without emulating page tables. This implementation handles ATTACH, DETACH, MAP and UNMAP requests. The bulk of the code

Re: [PATCH v3 3/7] PCI: OF: Allow endpoints to bypass the iommu

On 12/10/18 20:41, Bjorn Helgaas wrote: s/iommu/IOMMU/ in subject On Fri, Oct 12, 2018 at 03:59:13PM +0100, Jean-Philippe Brucker wrote: Using the iommu-map binding, endpoints in a given PCI domain can be managed by different IOMMUs. Some virtual machines may allow a subset of endpoints to

Re: [PATCH] kvm: arm64: fix caching of host MDCR_EL2 value

in events not being counted. In these cases, only the fixed-purpose cycle counter appears to work as expected. Fix this by always stashing the host MDCR_EL2 value, regardless of VHE. FWIW, Tested-by: Robin Murphy Fixes: 1e947bad0b63b351 ("arm64: KVM: Skip HYP setup when already running in

Re: [RFC v2 12/20] dma-iommu: Implement NESTED_MSI cookie

Hi Eric, On 2018-09-18 3:24 pm, Eric Auger wrote: Up to now, when the type was UNMANAGED, we used to allocate IOVA pages within a range provided by the user. This does not work in nested mode. If both the host and the guest are exposed with SMMUs, each would allocate an IOVA. The guest

Re: [RFC v2 12/20] dma-iommu: Implement NESTED_MSI cookie

On 2018-10-24 7:44 pm, Auger Eric wrote: Hi Robin, On 10/24/18 8:02 PM, Robin Murphy wrote: Hi Eric, On 2018-09-18 3:24 pm, Eric Auger wrote: Up to now, when the type was UNMANAGED, we used to allocate IOVA pages within a range provided by the user. This does not work in nested mode

Re: [virtio-dev] Re: [PATCH v5 5/7] iommu: Add virtio-iommu driver

On 2018-12-12 3:27 pm, Auger Eric wrote: Hi, On 12/12/18 3:56 PM, Michael S. Tsirkin wrote: On Fri, Dec 07, 2018 at 06:52:31PM +, Jean-Philippe Brucker wrote: Sorry for the delay, I wanted to do a little more performance analysis before continuing. On 27/11/2018 18:10, Michael S. Tsirkin

Re: Question: KVM: Failed to bind vfio with PCI-e / SMMU on Juno-r2

On 16/03/2019 04:56, Leo Yan wrote: Hi Robin, On Fri, Mar 15, 2019 at 12:54:10PM +, Robin Murphy wrote: Hi Leo, Sorry for the delay - I'm on holiday this week, but since I've made the mistake of glancing at my inbox I should probably save you from wasting any more time... Sorry

Re: [RFC v3 09/21] iommu/smmuv3: Get prepared for nested stage support

On 08/01/2019 10:26, Eric Auger wrote: To allow nested stage support, we need to store both stage 1 and stage 2 configurations (and remove the former union). arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE. We add a nested_bypass field to the S1 configuration as

Re: Question: KVM: Failed to bind vfio with PCI-e / SMMU on Juno-r2

Hi Leo, Sorry for the delay - I'm on holiday this week, but since I've made the mistake of glancing at my inbox I should probably save you from wasting any more time... On 2019-03-15 11:03 am, Auger Eric wrote: Hi Leo, + Jean-Philippe On 3/15/19 10:37 AM, Leo Yan wrote: Hi Eric, Robin,

Re: [PATCH v2] KVM: arm64: Skip more of the SError vaxorcism

Hi James, On 10/06/2019 17:30, James Morse wrote: During __guest_exit() we need to consume any SError left pending by the guest so it doesn't contaminate the host. With v8.2 we use the ESB-instruction. For systems without v8.2, we use dsb+isb and unmask SError. We do this on every guest exit.

Re: [PATCH v7 18/23] iommu/smmuv3: Report non recoverable faults

On 13/05/2019 13:32, Auger Eric wrote: Hi Robin, On 5/13/19 1:54 PM, Robin Murphy wrote: On 13/05/2019 08:46, Auger Eric wrote: Hi Robin, On 5/8/19 7:20 PM, Robin Murphy wrote: On 08/04/2019 13:19, Eric Auger wrote: When a stage 1 related fault event is read from the event queue, let's

Re: [PATCH v7 18/23] iommu/smmuv3: Report non recoverable faults

On 13/05/2019 08:46, Auger Eric wrote: Hi Robin, On 5/8/19 7:20 PM, Robin Murphy wrote: On 08/04/2019 13:19, Eric Auger wrote: When a stage 1 related fault event is read from the event queue, let's propagate it to potential external fault listeners, ie. users who registered a fault handler

Re: [PATCH v7 12/23] iommu/smmuv3: Get prepared for nested stage support

On 10/05/2019 15:34, Auger Eric wrote: Hi Robin, On 5/8/19 4:24 PM, Robin Murphy wrote: On 08/04/2019 13:19, Eric Auger wrote: To allow nested stage support, we need to store both stage 1 and stage 2 configurations (and remove the former union). A nested setup is characterized by both s1_cfg

Re: [PATCH v7 13/23] iommu/smmuv3: Implement attach/detach_pasid_table

On 10/05/2019 15:35, Auger Eric wrote: Hi Robin, On 5/8/19 4:38 PM, Robin Murphy wrote: On 08/04/2019 13:19, Eric Auger wrote: On attach_pasid_table() we program STE S1 related info set by the guest into the actual physical STEs. At minimum we need to program the context descriptor GPA

Re: [PATCH v7 14/23] iommu/smmuv3: Implement cache_invalidate

On 13/05/2019 13:16, Auger Eric wrote: Hi Robin, On 5/8/19 5:01 PM, Robin Murphy wrote: On 08/04/2019 13:19, Eric Auger wrote: Implement domain-selective and page-selective IOTLB invalidations. Signed-off-by: Eric Auger --- v6 -> v7 - check the uapi version v3 -> v4: - adapt to c

Re: [PATCH v7 18/23] iommu/smmuv3: Report non recoverable faults

On 08/04/2019 13:19, Eric Auger wrote: When a stage 1 related fault event is read from the event queue, let's propagate it to potential external fault listeners, ie. users who registered a fault handler. Signed-off-by: Eric Auger --- v4 -> v5: - s/IOMMU_FAULT_PERM_INST/IOMMU_FAULT_PERM_EXEC

Re: [PATCH v7 15/23] dma-iommu: Implement NESTED_MSI cookie

On 08/04/2019 13:19, Eric Auger wrote: Up to now, when the type was UNMANAGED, we used to allocate IOVA pages within a reserved IOVA MSI range. If both the host and the guest are exposed with SMMUs, each would allocate an IOVA. The guest allocates an IOVA (gIOVA) to map onto the guest MSI

Re: [PATCH v7 06/23] iommu: Introduce bind/unbind_guest_msi

On 08/04/2019 13:18, Eric Auger wrote: On ARM, MSI are translated by the SMMU. An IOVA is allocated for each MSI doorbell. If both the host and the guest are exposed with SMMUs, we end up with 2 different IOVAs allocated by each. guest allocates an IOVA (gIOVA) to map onto the guest MSI doorbell

Re: [PATCH v7 11/23] iommu/arm-smmu-v3: Maintain a SID->device structure

On 08/04/2019 13:18, Eric Auger wrote: From: Jean-Philippe Brucker When handling faults from the event or PRI queue, we need to find the struct device associated to a SID. Add a rb_tree to keep track of SIDs. Out of curiosity, have you looked at whether an xarray might now be a more

Re: [PATCH v7 12/23] iommu/smmuv3: Get prepared for nested stage support

On 08/04/2019 13:19, Eric Auger wrote: To allow nested stage support, we need to store both stage 1 and stage 2 configurations (and remove the former union). A nested setup is characterized by both s1_cfg and s2_cfg set. We introduce a new ste.abort field that will be set upon guest stage1

Re: [PATCH v7 13/23] iommu/smmuv3: Implement attach/detach_pasid_table

On 08/04/2019 13:19, Eric Auger wrote: On attach_pasid_table() we program STE S1 related info set by the guest into the actual physical STEs. At minimum we need to program the context descriptor GPA and compute whether the stage1 is translated/bypassed or aborted. Signed-off-by: Eric Auger

Re: [PATCH v7 14/23] iommu/smmuv3: Implement cache_invalidate

On 08/04/2019 13:19, Eric Auger wrote: Implement domain-selective and page-selective IOTLB invalidations. Signed-off-by: Eric Auger --- v6 -> v7 - check the uapi version v3 -> v4: - adapt to changes in the uapi - add support for leaf parameter - do not use arm_smmu_tlb_inv_range_nosync or

Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure

On 15/02/2020 10:28 am, Marc Zyngier wrote: On Fri, 14 Feb 2020 22:01:01 +, Robin Murphy wrote: Hi Robin, Hi Marc, On 2020-02-14 6:36 pm, Marc Zyngier wrote: [...] @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) pmc->

Re: [RFC PATCH 0/5] Removing support for 32bit KVM/arm host

On 20/02/2020 1:15 pm, Marc Zyngier wrote: Hi Marek, On 2020-02-20 12:44, Marek Szyprowski wrote: Hi Marc, On 10.02.2020 15:13, Marc Zyngier wrote: KVM/arm was merged just over 7 years ago, and has lived a very quiet life so far. It mostly works if you're prepared to deal with its

Re: [RFC PATCH 0/5] Removing support for 32bit KVM/arm host

On 20/02/2020 2:01 pm, Marc Zyngier wrote: On 2020-02-20 13:32, Robin Murphy wrote: On 20/02/2020 1:15 pm, Marc Zyngier wrote: Hi Marek, On 2020-02-20 12:44, Marek Szyprowski wrote: Hi Marc, On 10.02.2020 15:13, Marc Zyngier wrote: KVM/arm was merged just over 7 years ago, and has lived

Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure

Hi Marc, On 2020-02-14 6:36 pm, Marc Zyngier wrote: [...] @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) pmc->idx != ARMV8_PMU_CYCLE_IDX) return; + /* +* If we have a filter in place and that the event

Re: [PATCH 1/5] KVM: arm64: Fix missing RES1 in emulation of DBGBIDR

On 18/02/2020 5:43 pm, James Morse wrote: Hi Marc, $subject typo: ~/DBGBIDR/DBGDIDR/ On 16/02/2020 18:53, Marc Zyngier wrote: The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current emulation doesn't set. Just add the missing bit. So it does. Reviewed-by: James Morse diff

Re: [PATCHv6 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters

On 03/03/2020 7:07 pm, Mark Rutland wrote: On Mon, Mar 02, 2020 at 06:17:49PM +, Mark Rutland wrote: This is a respin of Andrew Murray's series to enable support for 64-bit counters as introduced in ARMv8.5. I've given this a spin on (ARMv8.2) hardware, to test that there are no

Re: [PATCH v2] KVM: arm64: Allow to limit number of PMU counters

On 2020-09-10 11:18, Alexander Graf wrote: On 10.09.20 12:06, Marc Zyngier wrote: On 2020-09-08 21:57, Alexander Graf wrote: We currently pass through the number of PMU counters that we have available in hardware to guests. So if my host supports 10 concurrently active PMU counters, my

Re: [PATCH v2] KVM: arm64: Allow to limit number of PMU counters

On 2020-09-10 17:46, Alexander Graf wrote: On 10.09.20 17:52, Robin Murphy wrote: On 2020-09-10 11:18, Alexander Graf wrote: On 10.09.20 12:06, Marc Zyngier wrote: On 2020-09-08 21:57, Alexander Graf wrote: We currently pass through the number of PMU counters that we have available

Re: [trivial PATCH] treewide: Convert switch/case fallthrough; to break;

On 2020-09-09 21:06, Joe Perches wrote: fallthrough to a separate case/default label break; isn't very readable. Convert pseudo-keyword fallthrough; statements to a simple break; when the next label is case or default and the only statement in the next label block is break; Found using: $

Re: [PATCH 1/2] KVM: arm64: Make vcpu_cp1x() work on Big Endian hosts

On 2020-06-09 09:49, Marc Zyngier wrote: AArch32 CP1x registers are overlayed on their AArch64 counterparts in the vcpu struct. This leads to an interesting problem as they are stored in their CPU-local format, and thus a CP1x register doesn't "hit" the lower 32bit portion of the AArch64

Re: [PATCH] arm64: Work around broken GCC handling of "S" constraint

On 2020-12-07 19:04, Marc Zyngier wrote: Hi Robin, On Mon, 07 Dec 2020 18:42:23 +, Robin Murphy wrote: On 2020-12-07 17:47, Ard Biesheuvel wrote: On Mon, 7 Dec 2020 at 18:41, Marc Zyngier wrote: On 2020-12-07 17:19, Ard Biesheuvel wrote: (resend with David's email address fixed

Re: [PATCH] arm64: Work around broken GCC handling of "S" constraint

On 2020-12-07 17:47, Ard Biesheuvel wrote: On Mon, 7 Dec 2020 at 18:41, Marc Zyngier wrote: On 2020-12-07 17:19, Ard Biesheuvel wrote: (resend with David's email address fixed) Irk. Thanks for that. +#ifdef CONFIG_CC_HAS_BROKEN_S_CONSTRAINT +#define SYM_CONSTRAINT "i" +#else +#define

Re: [PATCH v2] KVM: arm64: Disabling disabled PMU counters wastes a lot of time

On 2021-07-12 16:17, Alexandre Chartre wrote: In a KVM guest on arm64, performance counters interrupts have an unnecessary overhead which slows down execution when using the "perf record" command and limits the "perf record" sampling period. The problem is that when a guest VM disables counters

Re: [PATCH v2] KVM: arm64: Disabling disabled PMU counters wastes a lot of time

On 2021-07-12 16:51, Alexandru Elisei wrote: Hi Robin, On 7/12/21 4:44 PM, Robin Murphy wrote: On 2021-07-12 16:17, Alexandre Chartre wrote: In a KVM guest on arm64, performance counters interrupts have an unnecessary overhead which slows down execution when using the "perf record&quo

Re: [RFC PATCH 01/11] iommu/arm-smmu-v3: Add feature detection for HTTU

On 2021-02-05 09:13, Keqian Zhu wrote: Hi Robin and Jean, On 2021/2/5 3:50, Robin Murphy wrote: On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun The SMMU which supports HTTU (Hardware Translation Table Update) can update the access flag and the dirty state of TTD by hardware

Re: [RFC PATCH 01/11] iommu/arm-smmu-v3: Add feature detection for HTTU

On 2021-02-05 11:48, Robin Murphy wrote: On 2021-02-05 09:13, Keqian Zhu wrote: Hi Robin and Jean, On 2021/2/5 3:50, Robin Murphy wrote: On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun The SMMU which supports HTTU (Hardware Translation Table Update) can update the access flag

Re: [RFC PATCH 10/11] vfio/iommu_type1: Optimize dirty bitmap population based on iommu HWDBM

On 2021-02-07 09:56, Yi Sun wrote: Hi, On 21-01-28 23:17:41, Keqian Zhu wrote: [...] +static void vfio_dma_dirty_log_start(struct vfio_iommu *iommu, +struct vfio_dma *dma) +{ + struct vfio_domain *d; + + list_for_each_entry(d, >domain_list,

Re: [RFC PATCH 10/11] vfio/iommu_type1: Optimize dirty bitmap population based on iommu HWDBM

On 2021-02-09 11:57, Yi Sun wrote: On 21-02-07 18:40:36, Keqian Zhu wrote: Hi Yi, On 2021/2/7 17:56, Yi Sun wrote: Hi, On 21-01-28 23:17:41, Keqian Zhu wrote: [...] +static void vfio_dma_dirty_log_start(struct vfio_iommu *iommu, +struct vfio_dma *dma)

Re: [RFC PATCH 06/11] iommu/arm-smmu-v3: Scan leaf TTD to sync hardware dirty log

On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun During dirty log tracking, user will try to retrieve dirty log from iommu if it supports hardware dirty log. This adds a new interface named sync_dirty_log in iommu layer and arm smmuv3 implements it, which scans leaf TTD and treats it's

Re: [RFC PATCH 04/11] iommu/arm-smmu-v3: Split block descriptor to a span of page

On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun Block descriptor is not a proper granule for dirty log tracking. This adds a new interface named split_block in iommu layer and arm smmuv3 implements it, which splits block descriptor to an equivalent span of page descriptors. During

Re: [RFC PATCH 01/11] iommu/arm-smmu-v3: Add feature detection for HTTU

On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun The SMMU which supports HTTU (Hardware Translation Table Update) can update the access flag and the dirty state of TTD by hardware. It is essential to track dirty pages of DMA. This adds feature detection, none functional change.

Re: [RFC PATCH 05/11] iommu/arm-smmu-v3: Merge a span of page to block descriptor

On 2021-01-28 15:17, Keqian Zhu wrote: From: jiangkunkun When stop dirty log tracking, we need to recover all block descriptors which are splited when start dirty log tracking. This adds a new interface named merge_page in iommu layer and arm smmuv3 implements it, which reinstall block

Re: [PATCH 1/3] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements

On 2021-07-15 12:11, Marc Zyngier wrote: Hi Alex, On Wed, 14 Jul 2021 16:48:07 +0100, Alexandru Elisei wrote: Hi Marc, On 7/13/21 2:58 PM, Marc Zyngier wrote: A number of the PMU sysregs expose reset values that are not in compliant with the architecture (set bits in the RES0 ranges, for

Re: Any way to disable KVM VHE extension?

On 2021-07-15 09:55, Qu Wenruo wrote: Hi, Recently I'm playing around the Nvidia Xavier AGX board, which has VHE extension support. In theory, considering the CPU and memory, it should be pretty powerful compared to boards like RPI CM4. But to my surprise, KVM runs pretty poor on Xavier.

Re: Any way to disable KVM VHE extension?

On 2021-07-15 10:44, Qu Wenruo wrote: On 2021/7/15 下午5:28, Robin Murphy wrote: On 2021-07-15 09:55, Qu Wenruo wrote: Hi, Recently I'm playing around the Nvidia Xavier AGX board, which has VHE extension support. In theory, considering the CPU and memory, it should be pretty powerful