Re: [PATCH v5 0/7] Add RAS virtualization support to SEA/SEI notification type

Jonathan, Thanks for the review, will correct the typo issue in the next patch version. On 2017/8/22 15:54, Jonathan Cameron wrote: > On Fri, 18 Aug 2017 22:11:50 +0800 > Dongjiu Geng wrote: > >> In the firmware-first RAS solution, corrupt data is detected in a >>

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

Dave Martin writes: > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote: >> >> Dave Martin writes: >> >> > This patch defines the representation that will be used for the SVE >> > register state in the signal frame, and implements support for

Re: [PATCH 12/27] arm64/sve: Support vector length resetting for new processes

On Tue, Aug 22, 2017 at 05:22:11PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > It's desirable to be able to reset the vector length to some sane > > default for new processes, since the new binary and its libraries > > processes may or may not be SVE-aware. > >

[PATCH v3 3/4] kvm: arm/arm64: vgic-v3: add ICH_AP[01]Rn accessors for GICv3

This patch is used for GICv2 on GICv3. About GICV_APRn hardware register access,the SPEC says: When System register access is enabled for EL2, these registers access ICH_AP1Rn_EL2, and all active priorities for virtual machines are held in ICH_AP1Rn_EL2 regardless of interrupt group. For GICv3

[PATCH v3 1/4] kvm: arm/arm64: vgic: Implement the vGICv2 GICC_APRn uaccess interface.

The SPEC defined GICC_APR (n = 0-3, 32-bit per register) to provide information about interrupt active priorities for GICv2, and the user access will traverse all of these registers no matter how many priority levels we supported. So we have to implement the uaccess interface cover all of these

[PATCH v3 2/4] kvm: arm/arm64: vgic-v2: Add GICH_APRn accessors for GICv2

This patch is used for GICv2 on GICv2. About GICV_APRn hardware register access,the SPEC says: When System register access is disabled for EL2, these registers access GICH_APRn, and all active priorities for virtual machines are held in GICH_APRn regardless of interrupt group. For GICv2

[PATCH v3 0/4] kvm: arm/arm64: vgic: APRn uaccess support.

v3: Coding style fix. Add the valid APRn access check which Marc proposed. v2: Split the patch again to make it easier for review some fixes were proposed by Marc v1: the problem describe: In the case (GICv2 on GICv3 migration), I did the test on my board as follow: vm boot => migrate

[PATCH v3 4/4] kvm: arm/arm64: vgic: clean up vGICv3 ICC_APRn sysreg uaccess

It will be better that hide the underlying implementation for emulated GIC. This patch extend the vgic_set/get_apr func (with group parameter) more general, so that, the vGICv3 ICC_APRn sysreg uaccess can call this general interface for GICv3 on GICv3. Signed-off-by: wanghaibin

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

Dave Martin writes: > On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote: >> >> Dave Martin writes: >> >> > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote: >> >> >> >> Dave Martin writes: > > [...] > >> >> >

Re: [PATCH 11/27] arm64/sve: Core task context handling

On Tue, Aug 22, 2017 at 05:21:19PM +0100, Alex Bennée wrote: > > Dave Martin writes: [...] > > --- a/arch/arm64/include/asm/processor.h > > +++ b/arch/arm64/include/asm/processor.h > > @@ -85,6 +85,8 @@ struct thread_struct { > > unsigned long tp2_value; > >

Re: [PATCH v2 4/8] KVM: arm/arm64: vgic: restructure kvm_vgic_(un)map_phys_irq

Hi Christoffer, On 21/07/2017 13:44, Christoffer Dall wrote: > On Thu, Jun 15, 2017 at 02:52:36PM +0200, Eric Auger wrote: >> We want to reuse the core of the map/unmap functions for IRQ >> forwarding. Let's move the computation of the hwirq in >> kvm_vgic_map_phys_irq and pass the linux IRQ as

Re: [PATCH v2 5/8] KVM: arm/arm64: vgic: Handle mapped level sensitive SPIs

Hi Christoffer, On 21/07/2017 14:11, Christoffer Dall wrote: > On Thu, Jun 15, 2017 at 02:52:37PM +0200, Eric Auger wrote: >> Currently, the line level of unmapped level sensitive SPIs is >> toggled down by the maintenance IRQ handler/resamplefd mechanism. >> >> As mapped SPI completion is not

Re: [PATCH 11/27] arm64/sve: Core task context handling

Dave Martin writes: > This patch adds the core support for switching and managing the SVE > architectural state of user tasks. > > Calls to the existing FPSIMD low-level save/restore functions are > factored out as new functions task_fpsimd_{save,load}(), since SVE > now

Re: [PATCH v2 5/8] KVM: arm/arm64: vgic: Handle mapped level sensitive SPIs

Hi, On 25/07/2017 17:41, Marc Zyngier wrote: > On 25/07/17 15:48, Christoffer Dall wrote: >> On Tue, Jul 25, 2017 at 02:47:55PM +0100, Marc Zyngier wrote: >>> On 21/07/17 14:03, Christoffer Dall wrote: On Fri, Jul 07, 2017 at 09:41:42AM +0200, Auger Eric wrote: > Hi Marc, > > On

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

On Tue, Aug 22, 2017 at 04:03:20PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote: [...] > >> + > >> +#define SVE_VQ_BITS 128 /* 128 bits in one quadword */ > >> +#define SVE_VQ_BYTES

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

On Tue, Aug 22, 2017 at 02:53:49PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote: > >> > >> Dave Martin writes: [...] > >> > +/* > >> > + * The SVE architecture leaves space for

Re: [PATCH 10/27] arm64/sve: Low-level CPU setup

On Tue, Aug 22, 2017 at 04:04:28PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > To enable the kernel to use SVE, all SVE traps from EL1 must be > > disabled. To take maximum advantage of the hardware, the full > > available vector length also needs to be enabled

Re: [PATCH 12/27] arm64/sve: Support vector length resetting for new processes

Dave Martin writes: > It's desirable to be able to reset the vector length to some sane > default for new processes, since the new binary and its libraries > processes may or may not be SVE-aware. > > This patch tracks the desired post-exec vector length (if any) in a > new

Re: [PATCH 10/27] arm64/sve: Low-level CPU setup

Dave Martin writes: > To enable the kernel to use SVE, all SVE traps from EL1 must be > disabled. To take maximum advantage of the hardware, the full > available vector length also needs to be enabled for EL1 by > programming ZCR_EL2.LEN. (The kernel will program

Re: [PATCH 11/27] arm64/sve: Core task context handling

Dave Martin writes: > On Tue, Aug 22, 2017 at 05:21:19PM +0100, Alex Bennée wrote: >> >> Dave Martin writes: > > [...] > >> > --- a/arch/arm64/include/asm/processor.h >> > +++ b/arch/arm64/include/asm/processor.h >> > @@ -85,6 +85,8 @@ struct

Re: [PATCH v5 0/7] Add RAS virtualization support to SEA/SEI notification type

On Fri, 18 Aug 2017 22:11:50 +0800 Dongjiu Geng wrote: > In the firmware-first RAS solution, corrupt data is detected in a > memory location when guest OS application software executing at EL0 > or guest OS kernel El1 software are reading from the memory. The > memory

Re: [PATCH v5 1/7] arm64: cpufeature: Detect CPU RAS Extentions

On Fri, 18 Aug 2017 22:11:51 +0800 Dongjiu Geng wrote: > From: Xie XiuQi > > ARM's v8.2 Extentions add support for Reliability, Availability and > Serviceability (RAS). On CPUs with these extensions system software extensions, system software >

Re: [PATCH v5 7/7] arm64: kvm: handle SEI notification and inject virtual SError

On Fri, 18 Aug 2017 22:11:57 +0800 Dongjiu Geng wrote: > After receive SError, KVM firstly call memory failure to > deal with the Error. If memory failure wants user space to > handle it, it will notify user space. This patch adds support > to userspace that injects

Re: [PATCH v5 3/7] acpi: apei: Add SEI notification type support for ARMv8

On Fri, 18 Aug 2017 22:11:53 +0800 Dongjiu Geng wrote: > ARMV8.2 requires implementation of the RAS extension, in > this extension it adds SEI(SError Interrupt) notification > type, this patch addes a new GHES error source handling > function for SEI. Because this error

Re: [PATCH v5 4/7] support user space to query RAS extension feature

On Fri, 18 Aug 2017 22:11:54 +0800 Dongjiu Geng wrote: > In armv8.2 RAS extension, it adds virtual SError exception > syndrome registeri(VSESR_EL2), user space will specify that > value. so user space will check whether CPU feature has RAS > extension. if has, it will

Re: [PATCH v5 6/7] KVM: arm64: Allow get exception information from userspace

On Fri, 18 Aug 2017 22:11:56 +0800 Dongjiu Geng wrote: > when userspace gets SIGBUS signal, it does not know whether > this is a synchronous external abort or SError, so needs > to get the exception syndrome. so this patch allows userspace > can get this values. For

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

Dave Martin writes: > This patch defines the representation that will be used for the SVE > register state in the signal frame, and implements support for > saving and restoring the SVE registers around signals. > > The same layout will also be used for the in-kernel task

Re: [PATCH 09/27] arm64/sve: Signal frame and context structure definition

On Tue, Aug 22, 2017 at 11:22:44AM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > This patch defines the representation that will be used for the SVE > > register state in the signal frame, and implements support for > > saving and restoring the SVE registers