Maintenence IRQ */
};
--
1.7.9.5
This looks good to me and works with 4K and 64K pages on the mustang I
have at hand.
Acked-by: Christoffer Dall christoffer.d...@linaro.org
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On Thu, Feb 19, 2015 at 12:23:15PM -0600, Rob Herring wrote:
On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar
psawargaon...@apm.com wrote:
In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
in the dt are 4K aligned. This breaks KVM when kernel is built with
Hi Stephen,
On Wed, Mar 18, 2015 at 02:41:11PM +1100, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the kvm-arm tree got a conflict in
virt/kvm/arm/vgic.c between commit ae705930fca6 (arm/arm64: KVM: Keep
elrsr/aisr in sync with software model) from Linus' tree and commit
On Fri, Mar 06, 2015 at 03:34:39PM +0100, Ard Biesheuvel wrote:
The page size and the number of translation levels, and hence the supported
virtual address range, are build-time configurables on arm64 whose optimal
values are use case dependent. However, in the current implementation, if
the
...@linaro.org
Acked-by: Christoffer Dall christoffer.d...@linaro.org
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 1ad3eb0..2f21ae7 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s
On Tue, Mar 17, 2015 at 04:18:16PM +, Peter Maydell wrote:
On 16 March 2015 at 11:01, Alex Bennée alex.ben...@linaro.org wrote:
From: Christoffer Dall christoffer.d...@linaro.org
The current code was negatively indexing the cpu state array and not
synchronizing banked spsr register
On Tue, Mar 17, 2015 at 06:02:41PM +, Andre Przywara wrote:
Hej,
On 14/03/15 14:30, Christoffer Dall wrote:
On Fri, Mar 13, 2015 at 04:10:09PM +, Andre Przywara wrote:
Using the framework provided by the recent vgic.c changes we register
a kvm_io_bus device when initializing
On Tue, Mar 17, 2015 at 07:19:35PM +, Peter Maydell wrote:
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env-banked_spsr[1] field.
Correct the buggy regdef that put it in banked_spsr[0]
put it in banked_spsr[0].
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
Alex, will you respin the SPSR patch based on this one then? You can
change the authorship on the SPSR patch to yourself if you prefer.
Thanks
On Thu, Mar 19, 2015 at 03:44:51PM +, Andre Przywara wrote:
Hej Christoffer,
On 14/03/15 14:27, Christoffer Dall wrote:
On Fri, Mar 13, 2015 at 04:10:08PM +, Andre Przywara wrote:
Currently we use a lot of VGIC specific code to do the MMIO
dispatching.
Use the previous reworks
On Wed, Mar 04, 2015 at 02:35:52PM +, Alex Bennée wrote:
From: Christoffer Dall christoffer.d...@linaro.org
The current code was negatively indexing the cpu state array and not
synchronizing banked spsr register state with the current mode's spsr
state, causing occasional failures
On Mon, Mar 09, 2015 at 10:31:19PM +0900, Peter Maydell wrote:
On 9 March 2015 at 21:56, Christoffer Dall christoffer.d...@linaro.org
wrote:
this function, however, is not used only when migration, but should
generally cover the case where you want to synchronize QEMU's state into
KVM's
On Mon, Mar 09, 2015 at 04:34:21PM +, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
Hi Alex,
The subject of this change has a typo, and I also think it's not about
exposing the pause state (that's just an internal name/concept), but
about exposing
On Wed, Jan 21, 2015 at 06:42:13PM +, Marc Zyngier wrote:
Now that we have page aging in Stage-2, it becomes obvious that
we're doing way too much work handling the fault.
The page is not going anywhere (it is still mapped), the page
tables are already allocated, and all we want is to
change.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Christoffer Dall christoffer.d...@linaro.org
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On Wed, Jan 21, 2015 at 06:42:12PM +, Marc Zyngier wrote:
Until now, KVM/arm didn't care much for page aging (who was swapping
anyway?), and simply provided empty hooks to the core KVM code. With
server-type systems now being available, things are quite different.
This patch implements
Hi Alex and Marc,
On Fri, Mar 13, 2015 at 05:02:51PM +, Alex Bennée wrote:
Some fairly minor updates from the last series I sent out:
- Re-based on v4.0-rc3
- Use KVM_MP_STATE_STOPPED instead of KVM_MP_STATE_HALTED
- Some minor textual tidy ups on commit msgs and comments
-
...@virtualopensystems.com
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Acked-by: Paolo Bonzini pbonzini at redhat.com
Acked-by: Christoffer Dall christoffer.d...@linaro.org
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On Fri, Mar 13, 2015 at 04:10:11PM +, Andre Przywara wrote:
From: Nikolay Nikolaev n.nikol...@virtualopensystems.com
On IO memory abort, try to handle the MMIO access through the KVM
registered read/write callbacks. This is done by invoking the relevant
kvm_io_bus_* API.
[Andre: Since
On Fri, Mar 13, 2015 at 04:10:06PM +, Andre Przywara wrote:
In kvm_destroy_vm() we call kvm_io_bus_destroy() pretty early,
especially before calling kvm_arch_destroy_vm(). To avoid
unregistering devices from the already destroyed bus, let's mark
the bus with NULL to let other users know it
and
arm64 kvm Makefile.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Acked-by: Christoffer Dall christoffer.d...@linaro.org
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On Fri, Mar 13, 2015 at 04:10:09PM +, Andre Przywara wrote:
Using the framework provided by the recent vgic.c changes we register
a kvm_io_bus device when initializing the virtual GICv2.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
---
include/kvm/arm_vgic.h |1 +
-by: Christoffer Dall christoffer.d...@linaro.org
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On Wed, Mar 11, 2015 at 2:13 PM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Christoffer,
On 11/03/15 12:16, Christoffer Dall wrote:
Hi Marc,
On Tue, Mar 10, 2015 at 07:06:59PM +, Marc Zyngier wrote:
We're using __get_free_pages with to allocate the guest's stage-2
PGD. The standard
Hi Marc,
On Tue, Mar 10, 2015 at 07:06:59PM +, Marc Zyngier wrote:
We're using __get_free_pages with to allocate the guest's stage-2
PGD. The standard behaviour of this function is to return a set of
pages where only the head page has a valid refcount.
This behaviour gets us into
strings to the VGIC code. The of_device_id
entries are padded to keep the probe fucntion data aligned.
Signed-off-by: Mark Rutland mark.rutl...@arm.com
Cc: Andre Przywara andre.przyw...@arm.com
Cc: Christoffer Dall christoffer.d...@linaro.org
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Michal
On Thu, Mar 12, 2015 at 06:16:49PM +, Marc Zyngier wrote:
So far, KVM/arm doesn't implement any support for page aging, leading
to rather bad performance when the system is swapping. This short
series implements the required hooks and fault handling to deal with
pages being marked
. The !CONFIG_KVM_ARM_VGIC/TIMER case is pretty much an untested
code path anyway, so we're better off just getting rid of it.
Signed-off-by: Christoffer Dall christoffer.d...@linaro.org
---
This depends on Paolo's patch:
KVM: arm/arm64: prefer IS_ENABLED to a static variable
I've applied it to queue
On Wed, Mar 11, 2015 at 3:03 PM, Andrew Jones drjo...@redhat.com wrote:
On Wed, Mar 11, 2015 at 02:20:56PM +0100, Christoffer Dall wrote:
On Wed, Mar 11, 2015 at 2:13 PM, Marc Zyngier marc.zyng...@arm.com wrote:
Hi Christoffer,
On 11/03/15 12:16, Christoffer Dall wrote:
Hi Marc
On Thu, Feb 26, 2015 at 02:50:38PM +0100, Andrew Jones wrote:
On Thu, Feb 26, 2015 at 12:34:02PM +0100, Christoffer Dall wrote:
On Sun, Feb 01, 2015 at 07:34:28PM +0100, Andrew Jones wrote:
This series extends the kvm-unit-tests/arm[64] framework to support smp.
A break down
Hi Rich,
On Tue, Feb 24, 2015 at 11:59:35AM +, Richard W.M. Jones wrote:
https://bugzilla.redhat.com/show_bug.cgi?id=1194366
Has anyone seen this KVM error? Or have suggestions how to debug it
further?
kvm [2028]: load/store instruction decoding not implemented
This typically
On Sun, Feb 01, 2015 at 07:34:28PM +0100, Andrew Jones wrote:
This series extends the kvm-unit-tests/arm[64] framework to support smp.
A break down of the patches is as follows
01-02: prepare general framework for smp use
03-06: arm/arm64 fixups not 100% related to this series,
but
On Sun, Feb 01, 2015 at 07:34:31PM +0100, Andrew Jones wrote:
Sprinkle in some more isbs after context-changing operations,
as the ARM ARM states we should. I haven't seen any problems
without them, but we should do it right. Also, *actually* set
the MAIR in asm_mmu_enable. We were reading,
, since they need to be tagged with
the respective redistributor (read: VCPU) they are connected with.
We use the kvm_io_bus framework to register one devices per VCPU.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
On Thu, Mar 26, 2015 at 02:39:35PM +, Andre Przywara wrote:
Using the framework provided by the recent vgic.c changes we register
a kvm_io_bus device when initializing the virtual GICv2.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Reviewed-by: Christoffer Dall christoffer.d
.
Since the spec mandates those two pages to be contigious, we could as
well merge them and save the churn with the second KVM I/O bus device.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
do not make use of it yet, but will be enabled
with the following patches.
Signed-off-by: Andre Przywara andre.przyw...@arm.com
Reviewed-by: Marc Zyngier marc.zyng...@arm.com
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
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On Thu, Mar 26, 2015 at 02:39:38PM +, Andre Przywara wrote:
Currently we have struct kvm_exit_mmio for encapsulating MMIO abort
data to be passed on from syndrome decoding all the way down to the
VGIC register handlers. Now as we switch the MMIO handling to be
routed through the KVM MMIO
Hi Alex,
On Tue, Mar 31, 2015 at 04:08:05PM +0100, Alex Bennée wrote:
This adds support for single-stepping the guest. As userspace can and
will manipulate guest registers before restarting any tweaking of the
registers has to occur just before control is passed back to the guest.
this
On Tue, Mar 31, 2015 at 04:08:04PM +0100, Alex Bennée wrote:
This adds support for SW breakpoints inserted by userspace.
We do this by trapping all BKPT exceptions in the
hypervisor (MDCR_EL2_TDE).
you mean trapping all exceptions in the guest to the hypervisor?
The kvm_debug_exit_arch
On Mon, Apr 13, 2015 at 03:51:33PM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Mar 31, 2015 at 04:08:00PM +0100, Alex Bennée wrote:
Currently x86, powerpc and soon arm64 use the same two architecture
specific bits for guest debug support
On Fri, Apr 10, 2015 at 02:25:21PM +0200, Andrew Jones wrote:
[...]
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -196,16 +196,49 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu
*vcpu,
* - If the dirty bit is set, save guest registers, restore host
*
(struct kvm *kvm,
struct kvm_kernel_irq_routing_entry *entries,
int gsi)
{
- return gsi;
+ return 0;
}
int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin)
--
Acked-by: Christoffer Dall christoffer.d...@linaro.org
On Tue, Mar 31, 2015 at 04:08:06PM +0100, Alex Bennée wrote:
This adds support for userspace to control the HW debug registers for
guest debug. We'll only copy the $ARCH defined number across as that is
all that hyp.S will use anyway.
I don't really understand what this sentence means?
I've
On Mon, Apr 13, 2015 at 08:59:21AM +0100, Alex Bennée wrote:
[...]
+ /* MDSCR_EL1 */
+ if (r-reg == MDSCR_EL1) {
+ if (p-is_write)
+ vcpu_debug_saved_reg(vcpu, mdscr_el1) =
+ *vcpu_reg(vcpu,
On Wed, Mar 18, 2015 at 03:10:31PM -0400, Andrew Jones wrote:
Also rename to KVM_MEM_UNCACHED.
Signed-off-by: Andrew Jones drjo...@redhat.com
---
Documentation/virtual/kvm/api.txt | 16 ++--
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm/kvm/arm.c| 1 +
On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter Maydell wrote:
On 28 April 2015 at 09:42, Alex Bennée alex.ben...@linaro.org wrote:
Peter Maydell peter.mayd...@linaro.org writes:
Does the kernel already have a conveniently implemented inject
exception into guest lump of code? If so it might
On Wed, Apr 29, 2015 at 10:18:18AM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Apr 28, 2015 at 03:37:01PM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Tue, Apr 28, 2015 at 10:34:12AM +0100, Peter
On Thu, Apr 30, 2015 at 01:43:31PM +0200, Christian Borntraeger wrote:
Use __kvm_guest_{enter|exit} instead of kvm_guest_{enter|exit}
where interrupts are disabled.
Signed-off-by: Christian Borntraeger borntrae...@de.ibm.com
For the ARM part:
Acked-by: Christoffer Dall christoffer.d
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
To maintain cache coherency on ARM, we may need a mechanism to flush
the data cache.
In addition to generally just making this functionality available (see
below), do you have an actual use case in mind for this? To
Hi Eric,
On Wed, Feb 11, 2015 at 09:20:53AM +0100, Eric Auger wrote:
This series proposes some fixes that appeared to be necessary
to integrate IRQ forwarding in KVM/VFIO.
- deactivation of the forwarded IRQ in irq_disabled case
- a specific handling of forwarded IRQ into the VGIC state
On Thu, May 07, 2015 at 09:48:25AM +0200, Eric Auger wrote:
Hi Christoffer,
On 05/06/2015 04:26 PM, Christoffer Dall wrote:
On Wed, Feb 11, 2015 at 09:20:55AM +0100, Eric Auger wrote:
Fix multiple injection of level sensitive forwarded IRQs.
With current code, the second injection fails
{
__u64 nr;
__u64 ret;
--
2.3.5
otherwise:
Acked-by: Christoffer Dall christoffer.d...@linaro.org
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On Wed, May 06, 2015 at 05:23:17PM +0100, Alex Bennée wrote:
Currently x86, powerpc and soon arm64 use the same two architecture
specific bits for guest debug support for software and hardware
breakpoints. This makes the shared values explicit while leaving the
gate open for another
__KVM_GUESTDBG_USE_HW_BP
+
#endif /* __ARM_KVM_H__ */
--
2.3.5
Otherwise:
Acked-by: Christoffer Dall christoffer.d...@linaro.org
Thanks,
-Christoffer
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On Thu, May 07, 2015 at 10:07:11AM +0100, Alex Bennée wrote:
This is a pre-cursor to sharing the code with the guest debug support.
This replaces the big macro that fishes data out of a fixed location
with a more general helper macro to restore a set of debug registers. It
uses macro
On Thu, May 07, 2015 at 10:07:15AM +0100, Alex Bennée wrote:
This includes trace points for:
kvm_arch_setup_guest_debug
kvm_arch_clear_guest_debug
kvm_handle_guest_debug
I've also added some generic register setting trace events and also a
trace point to dump the array of hardware
On Thu, May 07, 2015 at 10:07:13AM +0100, Alex Bennée wrote:
When we are using the hardware registers for guest debug we need to deal
with the guests access to them. There is already a mechanism for dealing
with these accesses so we build on top of that.
- any access to mdscr_el1 is now
On Thu, May 07, 2015 at 10:07:12AM +0100, Alex Bennée wrote:
This adds support for userspace to control the HW debug registers for
guest debug. In the debug ioctl we copy the IMPDEF defined number of
registers into a new register set called host_debug_state. There is now
a new vcpu parameter
On Wed, May 06, 2015 at 05:23:15PM +0100, Alex Bennée wrote:
Hi,
Here is V3 of the KVM Guest Debug support for arm64.
This sees the return of hyp.S re-factoring code which has been
expanded to handle both the save and restore legs. The HW debug patch
then adds a simple indirection to
-by: Christoffer Dall christoffer.d...@linaro.org
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On Sat, May 09, 2015 at 09:10:57PM +0100, Russell King - ARM Linux wrote:
On Sat, May 09, 2015 at 10:07:17PM +0200, Christoffer Dall wrote:
On Fri, May 08, 2015 at 05:08:42PM +0100, Russell King wrote:
BSYM() should only be used when refering to local symbols in the same
assembly file
On Mon, May 04, 2015 at 11:24:22AM +0200, Paolo Bonzini wrote:
On 04/05/2015 04:48, Tiejun Chen wrote:
We already check KVM_CAP_IRQFD in generic once enable CONFIG_HAVE_KVM_IRQFD,
kvm_vm_ioctl_check_extension_generic()
|
+ switch (arg) {
+ ...
+ #ifdef
On Fri, May 08, 2015 at 05:08:42PM +0100, Russell King wrote:
BSYM() should only be used when refering to local symbols in the same
assembly file which are resolved by the assembler, and not for
linker-fixed up symbols. The use of BSYM() with panic is incorrect as
the linker is involved in
On Thu, May 7, 2015 at 4:50 PM, Jérémy Fanguède
j.fangu...@virtualopensystems.com wrote:
On Thu, May 7, 2015 at 1:20 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
On Thu, May 07, 2015 at 12:50:50PM +0200, Jérémy Fanguède wrote:
On Wed, May 6, 2015 at 4:12 PM, Christoffer Dall
christoffer.d...@linaro.org wrote:
Hi Jérémy,
On Tue, May 05, 2015 at 11:13:11AM +0200, Jérémy Fanguède wrote:
To maintain cache coherency on ARM, we may need a mechanism
] = kvm_handle_guest_debug,
};
static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
--
2.3.5
Besides the nit:
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
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On Wed, May 06, 2015 at 05:23:22PM +0100, Alex Bennée wrote:
This adds support for single-stepping the guest. To do this we need to
manipulate the guests PSTATE.SS and MDSCR_EL1.SS bits which we do in the
kvm_arm_setup/clear_debug() so we don't affect the apparent state of the
guest.
On Thu, May 14, 2015 at 01:38:38PM +0200, Paolo Bonzini wrote:
On 14/05/2015 13:36, Christoffer Dall wrote:
(It's probably worth looking at the documentation in the first hunk
too,
under the commit message.)
Why is this a hack/unintuitive? Is the semantics
),
and it makes sense to rely on the instruction patching instead.
This leads to a nice cleanup of the code.
Acked-by: Will Deacon will.dea...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
I gave this a quick spin on Juno as well and works as expected:
Reviewed-by: Christoffer Dall
On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
On 14/05/2015 14:00, Christoffer Dall wrote:
So, getting back to my original question. Is the point then that UEFI
must assume (from ACPI/DT) the cache-coherency properties of the PCI
controller which exists in hardware
On Thu, May 14, 2015 at 02:28:49PM +0200, Paolo Bonzini wrote:
On 14/05/2015 14:24, Christoffer Dall wrote:
On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
On 14/05/2015 14:00, Christoffer Dall wrote:
So, getting back to my original question. Is the point
On Thu, May 14, 2015 at 03:36:37PM +0200, Andrew Jones wrote:
On Thu, May 14, 2015 at 02:11:59PM +0100, Peter Maydell wrote:
On 14 May 2015 at 14:03, Andrew Jones drjo...@redhat.com wrote:
On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
On 14 May 2015 at 11:31, Andrew Jones
On Thu, May 14, 2015 at 03:46:44PM +0200, Andrew Jones wrote:
On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
Provide a method to change normal, cacheable memory to non-cacheable.
KVM will make use
On Thu, May 14, 2015 at 03:32:13PM +0200, Andrew Jones wrote:
On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
When S1 and S2 memory attributes combine wrt to caching policy,
non-cacheable types take precedence
On Thu, May 14, 2015 at 01:09:34PM +0200, Laszlo Ersek wrote:
On 05/14/15 12:30, Christoffer Dall wrote:
On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
needed by ARM. This flag informs KVM that the given memory
On Thu, May 14, 2015 at 01:31:03PM +0200, Paolo Bonzini wrote:
On 14/05/2015 13:29, Christoffer Dall wrote:
(It's probably worth looking at the documentation in the first hunk too,
under the commit message.)
Why is this a hack/unintuitive? Is the semantics of the QEMU PCI bus
On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
When S1 and S2 memory attributes combine wrt to caching policy,
non-cacheable types take precedence. If a guest maps a region as
device memory, which KVM userspace is using to emulate the device
using normal, cacheable memory, then
-by: Christoffer Dall christoffer.d...@linaro.org
But you obviously need Russell and Will/Catalin to ack/merge this.
-Christoffer
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Hi Paolo and Marc,
On Tue, Apr 07, 2015 at 06:20:15PM +0200, Paolo Bonzini wrote:
On 18/03/2015 08:55, Christoffer Dall wrote:
Hi Stephen,
On Wed, Mar 18, 2015 at 02:41:11PM +1100, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the kvm-arm tree got a conflict
On Tue, Mar 31, 2015 at 04:08:01PM +0100, Alex Bennée wrote:
This commit defines the API headers for guest debugging. There are two
architecture specific debug structures:
- kvm_guest_debug_arch, allows us to pass in HW debug registers
- kvm_debug_exit_arch, signals the exact debug exit
On Mon, Apr 13, 2015 at 11:21:20AM +0100, Marc Zyngier wrote:
On 13/04/15 11:04, Christoffer Dall wrote:
On Fri, Apr 10, 2015 at 05:52:05PM +0100, Andre Przywara wrote:
Hi Christopher,
On 10/04/15 16:29, Christopher Covington wrote:
Hi Andre,
On 04/10/2015 11:17 AM, Andre Przywara
On Mon, Apr 13, 2015 at 04:36:23PM +0200, Christoffer Dall wrote:
[...]
+
+/**
+ * kvm_arch_setup_debug - set-up debug related stuff
nit: I think you want set up when it's a verb.
+ *
+ * @vcpu: the vcpu pointer
+ *
+ * This is called before each entry in to the hypervisor
On Thu, Apr 09, 2015 at 05:53:59PM +0100, Marc Zyngier wrote:
The world switch spends quite some time dealing with the FP/SIMD
registers, as the state is quite sizeable (32 128bit registers,
plus some crumbs on the side). We save/restore them on each
entry/exit, so that both the host and the
On Thu, Apr 09, 2015 at 03:59:46PM +0200, Andrew Jones wrote:
On Thu, Apr 09, 2015 at 03:35:06PM +0200, Christoffer Dall wrote:
On Thu, Apr 09, 2015 at 02:06:47PM +0200, Andrew Jones wrote:
On Thu, Apr 09, 2015 at 08:57:23AM +0100, Marc Zyngier wrote:
On Thu, 9 Apr 2015 02:46:54 +0100
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
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On Wed, Apr 08, 2015 at 09:15:13AM +0100, Marc Zyngier wrote:
On Tue, 7 Apr 2015 17:20:15 +0100
Paolo Bonzini pbonz...@redhat.com wrote:
Hi Paolo,
On 18/03/2015 08:55, Christoffer Dall wrote:
Hi Stephen,
On Wed, Mar 18, 2015 at 02:41:11PM +1100, Stephen Rothwell wrote:
Hi all
On Fri, Jun 05, 2015 at 05:24:07AM -0700, Mario Smarduch wrote:
On 06/02/2015 02:27 AM, Christoffer Dall wrote:
On Mon, Jun 01, 2015 at 08:48:22AM -0700, Mario Smarduch wrote:
On 05/30/2015 11:59 PM, Christoffer Dall wrote:
Hi Mario,
On Fri, May 29, 2015 at 03:34:47PM -0700, Mario
On Mon, Jun 08, 2015 at 06:50:08PM +0100, Marc Zyngier wrote:
Hi Christoffer,
On 28/05/15 19:49, Christoffer Dall wrote:
Until now we have been calling kvm_guest_exit after re-enabling
interrupts when we come back from the guest, but this has the
unfortunate effect that CPU time
On Fri, May 29, 2015 at 10:30:26AM +0100, Alex Bennée wrote:
This adds support for userspace to control the HW debug registers for
guest debug. In the debug ioctl we copy the IMPDEF defined number of
registers into a new register set called host_debug_state. There is now
a new vcpu parameter
]= kvm_handle_guest_debug,
[ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug,
[ESR_ELx_EC_BRK64] = kvm_handle_guest_debug,
};
--
2.4.1
As for the code of this patch:
Reviewed-by: Christoffer Dall christoffer.d...@linaro.org
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On Thu, Jun 04, 2015 at 11:34:46AM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Fri, May 29, 2015 at 10:30:24AM +0100, Alex Bennée wrote:
This is a pre-cursor to sharing the code with the guest debug support.
This replaces the big macro that fishes
On Thu, Jun 25, 2015 at 07:32:27AM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Fri, Jun 19, 2015 at 01:23:47PM +0100, Alex Bennée wrote:
This introduces a level of indirection for the debug registers. Instead
of using the sys_regs[] directly we
Hi,
[sorry for reviving this thread late]
On Tue, Jun 09, 2015 at 12:24:13PM +0100, Peter Maydell wrote:
On 9 June 2015 at 11:52, Marc Zyngier marc.zyng...@arm.com wrote:
On 08/06/15 11:52, Peter Maydell wrote:
On 8 June 2015 at 11:32, Igor Mammedov imamm...@redhat.com wrote:
On Thu, 4
On Wed, Jun 24, 2015 at 03:54:57PM +0100, Marc Zyngier wrote:
Userspace is allowed to set the guest's view of CNTVCT, which turns
into setting CNTVOFF for the whole VM. One thing userspace is not supposed
to do is to update that register while the guest is running. Time will
either move
On Wed, Jun 24, 2015 at 10:32:38AM +0100, Marc Zyngier wrote:
Hi Christoffer,
On 24/06/15 09:51, Christoffer Dall wrote:
On Wed, Jun 24, 2015 at 09:29:56AM +0100, Marc Zyngier wrote:
On 22/06/15 09:44, Peter Maydell wrote:
On 17 June 2015 at 10:00, Suzuki K. Poulose suzuki.poul
On Thu, Jun 25, 2015 at 10:06:20AM +0100, Peter Maydell wrote:
On 25 June 2015 at 09:00, Christoffer Dall christoffer.d...@linaro.org
wrote:
Of course, KVM can deny an unsupported configuration, but I am wondering
if we really think anybody will care about the 'model such specific
On Wed, Jun 24, 2015 at 09:29:56AM +0100, Marc Zyngier wrote:
On 22/06/15 09:44, Peter Maydell wrote:
On 17 June 2015 at 10:00, Suzuki K. Poulose suzuki.poul...@arm.com wrote:
From: Suzuki K. Poulose suzuki.poul...@arm.com
This patch adds a generic ARM v8 KVM target cpu type for use
by
On Thu, Jun 25, 2015 at 07:38:33AM +0100, Alex Bennée wrote:
Christoffer Dall christoffer.d...@linaro.org writes:
On Fri, Jun 19, 2015 at 01:23:48PM +0100, Alex Bennée wrote:
This adds support for userspace to control the HW debug registers for
guest debug. In the debug ioctl we copy
to the guest debug state.
+ */
+ if (vcpu-guest_debug KVM_GUESTDBG_USE_HW)
+ vcpu-arch.debug_ptr = vcpu-arch.vcpu_debug_state;
I still think this would be more cleanly done in the setup_debug
function, but ok:
Reviewed-by: Christoffer Dall christoffer.d
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