On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
(...)
+
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch moves some of the ST specific register extensions access under
condition, so that other SOCs like Qualcomm or ARM would not a side effect of
writing to
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of
On Tue, Apr 29, 2014 at 10:21 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some bits which control Command Path State Machine (CPSM) are new in Qcom
integration, so this patch adds support to those bits.
Signed-off-by: Srinivas
On Tue, Apr 29, 2014 at 10:21 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still
Thanks Linus W.
On 13/05/14 08:17, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but
On 13/05/14 08:20, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Thanks Linus W for reviewing the patches.
On 13/05/14 08:29, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
On 13/05/14 09:08, Linus Walleij wrote:
/* Keep ST Micro busy mode if enabled */
- datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
+ if (host-hw_designer == AMBA_VENDOR_ST)
+ datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
Do not hard-check the
Thanks Linus W,
On 13/05/14 09:28, Linus Walleij wrote:
code is conditioned on hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
(...)
+ if (host-hw_designer == AMBA_VENDOR_QCOM) {
+ host-cclk = host-mclk;
+ }
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off-by:
On 29 April 2014 10:18, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register
On 13/05/14 11:04, Ulf Hansson wrote:
On 29 April 2014 10:18, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit
On Fri, May 09, 2014 at 12:57:39AM +0300, Stanimir Vabanov wrote:
Hi Herbert,
On 04/28/2014 11:59 AM, Herbert Xu wrote:
On Mon, Apr 14, 2014 at 03:48:37PM +0300, Stanimir Varbanov wrote:
+#define QCE_MAJOR_VERSION50x05
+#define QCE_QUEUE_LENGTH 50
What is the purpose of
This patch fixes the calculation for determining whether to use FIFO or BLOCK
mode.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index
This set of patches provides a few fixes for the SPI QUP driver and support for
an earlier version of the QUP.
The first patch removes the use of the controller's own chip select
functionality. The user should instead use GPIOs and make use of the SPI core's
GPIO chip select feature.
The second
This patch removes the chip select function. Chip select should instead be
supported using GPIOs, defining the DT entry cs-gpios, and letting the SPI
core assert/deassert the chip select as it sees fit.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 11 +++
1
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/spi/spi-qup.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index
On 05/13, Andy Gross wrote:
@@ -488,7 +491,7 @@ static int spi_qup_probe(struct platform_device *pdev)
struct resource *res;
struct device *dev;
void __iomem *base;
- u32 data, max_freq, iomode;
+ u32 data = 0, max_freq, iomode;
It looks like data is unused? But
On 05/13, Srinivas Kandagatla wrote:
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is
On Tue, May 13, 2014 at 03:08:45PM -0700, Stephen Boyd wrote:
On 05/13, Andy Gross wrote:
@@ -488,7 +491,7 @@ static int spi_qup_probe(struct platform_device *pdev)
struct resource *res;
struct device *dev;
void __iomem *base;
- u32 data, max_freq, iomode;
+ u32 data =
Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
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