become idle. I belive two values should
be considered, but are they?
1. The card need BKOPS to be performed for some status level.
2. Request inactivity for a certain timeout has occured.
Have you considered to use runtime PM for the card device instead of
the workqueue?
Kind regards
Ulf Hansson
will be interrupted.
As for the effect on the battery consumption, this is probably something
specific to our controller, so sorry if I created a confusion.
Additional comments inline.
Thanks,
Maya
On Tue, December 4, 2012 1:52 am, Ulf Hansson wrote:
On 3 December 2012 10:49, me...@codeaurora.org
at http://vger.kernel.org/majordomo-info.html
Kind regards
Ulf Hansson
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in
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Acked-by: Ulf Hansson ulf.hans...@linaro.org
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More
On 6 December 2012 16:25, Subhash Jadavani subha...@codeaurora.org wrote:
On 12/6/2012 4:03 PM, Ulf Hansson wrote:
On 4 December 2012 12:36, Subhash Jadavani subha...@codeaurora.org
wrote:
If SDIO keep power flag (MMC_PM_KEEP_POWER) is not set, card would
be reinitialized during resume
://vger.kernel.org/majordomo-info.html
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
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to poll for the BKOPS status.
Thanks,
Maya
-Original Message-
From: linux-mmc-ow...@vger.kernel.org
[mailto:linux-mmc-ow...@vger.kernel.org] On Behalf Of Ulf Hansson
Sent: Thursday, December 13, 2012 12:18 PM
To: me...@codeaurora.org
Cc: Jaehoon Chung; linux-...@vger.kernel.org; linux
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Please read the FAQ at http://www.tux.org/lkml/
Kind regards
Ulf Hansson
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Please read the FAQ at http://www.tux.org/lkml/
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I agree that some update to the commit msg is wanted; since this fixup
is not related to runtime suspend as such.
Anyway, you have my ack!
Acked-by: Ulf Hansson ulf.hans...@linaro.org
Kind regards
Ulf Hansson
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with new clk tree topology */
clk_debug_reparent(clk, parent);
--
1.7.8.3
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
Looks good! Thanks for having another round to fixup this kind of
tricky code. :-)
Acked-by: Ulf Hansson
?
Kind regards
Ulf Hansson
/***helper functions ***/
Mike,
Thoughts? Picking it up? Removing the existing auto-disable code (I think
they are still useful)?
-Saravana
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to the regulator for the vdd (core voltage) supply.
+- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage)
supply.
The common naming of the above regulators are vmmc and vqmmc. Is
there any specific reason to why you can't use these names?
Kind regards
Ulf Hansson
+- pinctrl-names
= THIS_MODULE,
+ .of_match_table = sdhci_msm_dt_match,
+ },
+};
+
+module_platform_driver(sdhci_msm_driver);
+
+MODULE_DESCRIPTION(Qualcomm Secure Digital Host Controller Interface
driver);
+MODULE_LICENSE(GPL v2);
--
1.7.9.5
Kind regards
Ulf Hansson
.
Looks good to me!
For the complete patchset:
Acked-by: Ulf Hansson ulf.hans...@linaro.org
Thanks,
Georgi
On 03/10/2014 05:37 PM, Georgi Djakov wrote:
This patchset adds basic support of the Secure Digital Host Controller
Interface compliant controller found in Qualcomm SoCs.
Tested
them this way,
unless of course Russell have other opinions.
git://git.linaro.org/people/ulf.hansson/mmc.git next
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error here.
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for mclk_delayed_writes no matter of variant.
How about, adding a new function pointer in the struct mmci_host, for
writel operations which you could set up in probe phase instead?
Kind regards
Ulf Hansson
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, if this
--
1.9.1
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,
+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
Linus, will have to confirm this. I don't know if the u300 variant
support 8-bit.
Kind regards
Ulf Hansson
.datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
.datalength_bits= 16,
.sdio = true,
@@ -144,6 +147,7
at %u Hz\n, mmc-f_max);
/* Get regulators and the supported OCR mask */
--
1.9.1
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On 26 May 2014 16:21, Ulf Hansson ulf.hans...@linaro.org wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers like Qcom SD card controller where cclk is mclk and mclk
should
be directly controlled
time this function gets invoked.
+
if (status MCI_TXACTIVE)
len = mmci_pio_write(host, buffer, remain, status);
So no changes needed for pio_write at this point? Or those will come later?
--
1.9.1
Kind regards
Ulf Hansson
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On 27 May 2014 00:39, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Ulf,
Thankyou for the comments.
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers
!
clk_round_rate(mclk, 100KHz), might be better though - since that is
actually the lowest request frequency whatsoever.
Kind regards
Ulf Hansson
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not a big deal to me - let's keep it as is for now.
Kind regards
Ulf Hansson
I will make sure that the macro is named more appropriately to reflect the
same.
thanks,
srini
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On 28 May 2014 10:28, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On 28/05/14 09:02, Linus Walleij wrote:
On Tue, May 27, 2014 at 12:39 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52
this patch datactrl register is updated with wrong ddrmode mask on non
ST SOCs, resulting in card detection failures.
The above statement seems not correct. We don't have any issues
currently, right. :-)
Kind regards
Ulf Hansson
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
= 0x000f,
+ .data = variant_qcom,
+ },
{ 0, 0 },
};
Shouldn't this patch be moved to very end of this patchset?
If we would apply this patch on it's own - the Qcom variant wouldn't
work, right?
Kind regards
Ulf Hansson
--
1.9.1
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0x010
#define MMCIRESPONSE0 0x014
#define MMCIRESPONSE1 0x018
--
1.9.1
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intmclk_req;
How about clock_cache instead?
unsigned intcclk;
u32 pwr_reg;
u32 pwr_reg_add;
--
1.9.1
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= clk_get_rate(host-clk);
--
1.9.1
Looks good otherwise!
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stuff */
struct sg_mapping_iter sg_miter;
unsigned intsize;
+ int (*pio_read)(struct mmci_host *h, char *buf, unsigned int remain);
#ifdef CONFIG_DMA_ENGINE
/* DMA stuff */
--
1.9.1
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On 2 June 2014 11:03, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Thankyou Linus W, Ulf H, Russell K and everyone for reviewing RFC to v5
patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC
On 10 June 2014 20:27, Stephen Boyd sb...@codeaurora.org wrote:
The sdhci core was refactored recently and some of those
refactorings required changes in every sdhci platform driver.
Those updates happened around the same time as when the msm
driver was merged so the refactorings missed the
On 11 July 2014 19:48, Georgi Djakov gdja...@mm-sol.com wrote:
This patchset contains fixes in the documentation, cleanups
and enables COMPILE_TEST for better testing coverage.
Georgi Djakov (3):
mmc: sdhci-msm: Fix the binding example
mmc: sdhci-msm: Remove unnecessary header file
On 29 July 2014 04:50, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to assist dma transfers.
This hardware needs to be setup before any dma transfer is requested.
DML itself is
On 19 August 2014 13:14, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
From: Ulf Hansson ulf.hans...@linaro.org
For the ux500v2 variant of the PL18x block, any block sizes are
supported. This will make it possible to decrease data overhead
for SDIO transfers.
This patch is based
On 3 September 2014 01:58, Stephen Boyd sb...@codeaurora.org wrote:
If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that assumes the CPU is little-endian.
Change the table to be an
On 4 September 2014 07:06, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Stephen.
On 09/03/2014 10:57 PM, Stephen Boyd wrote:
If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that
On 9 September 2014 10:34, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
This patch fixes a typo which resulted in 'is never less
than zero warning' reported by static checker.
drivers/mmc/host/mmci_qcom_dml.c:131 dml_hw_init()
warn: unsigned 'producer_id' is never
On 22 August 2014 06:54, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
This patch adds sdio enable mask in variant data, SOCs like ST have
special bits in datactrl register to enable sdio. Unconditionally setting
this bit in this driver breaks other SOCs like Qualcomm which maps
On 22 August 2014 06:55, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
This patch renames sdio flag in vendor data to st_sdio, as this flag is
only used to enable ST specific sdio setup. This will also ensure that
the ST specfic setup is not done on other vendor like Qualcomm.
On 22 August 2014 06:54, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
From: Ulf Hansson ulf.hans...@linaro.org
For the ux500v2 variant of the PL18x block, any block sizes are
supported. This will make it possible to decrease data overhead
for SDIO transfers.
This patch is based
On 10 September 2014 11:07, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Ulf,
On 10/09/14 08:58, Ulf Hansson wrote:
On 22 August 2014 06:54, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
From: Ulf Hansson ulf.hans...@linaro.org
For the ux500v2 variant
2014-09-15 23:45 GMT+02:00 Stephen Boyd sb...@codeaurora.org:
On 09/04/14 15:01, Stephen Boyd wrote:
8
From: Stephen Boyd sb...@codeaurora.org
Subject: [PATCH] mmc: Consolidate emmc tuning blocks
The same tuning block array exists in the dw_mmc h.c and sdhci-msm.c
files. Move these
On 22 September 2014 21:26, Stephen Boyd sb...@codeaurora.org wrote:
If we're tuning on a big-endian CPU we'll never determine we properly
tuned the device because we compare the data we received from the
controller with a table that assumes the CPU is little-endian.
Change the table to be an
On 22 September 2014 21:26, Stephen Boyd sb...@codeaurora.org wrote:
The same tuning block exists in the dw_mmc h.c and sdhci-msm.c
files. Move these into mmc.c so that they can be shared across
drivers.
Reported-by: Jaehoon Chung jh80.ch...@samsung.com
Signed-off-by: Stephen Boyd
On 2 December 2014 at 12:53, Asutosh Das asuto...@codeaurora.org wrote:
In this patch series, we propose a method to add support for
Command Queueing(CQ) feature added to eMMC-5.1 specification.
This feature includes new commands for issuing tasks to the
device and orders the execution of
[...]
Also, please don't forget to provide some perfomance numbers.
I can provide some performance numbers in the last week of february or in
the beginning of March. Is that fine ?
Do you want the comments addressed before I publish the performance numbers
or do you prefer the comments to
On 22 January 2015 at 20:34, Stephen Boyd sb...@codeaurora.org wrote:
These drivers don't need to include clk-private.h. Remove the
include.
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Stephen Boyd sb...@codeaurora.org
Acked-by: Ulf
On 5 January 2015 at 20:52, Bjorn Andersson bj...@kryo.se wrote:
On Sun, Dec 21, 2014 at 7:01 PM, Tim Kryger tim.kry...@gmail.com wrote:
On Wed, Dec 17, 2014 at 11:57 AM, Bjorn Andersson bj...@kryo.se wrote:
[..]
Non-the-less, feel free to propose a patch and I will give it a test.
Lets
On 13 March 2015 at 19:09, Stephen Boyd sb...@codeaurora.org wrote:
This driver is orphaned now that mach-msm has been removed.
Delete it.
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: Chris Ball ch...@printf.net
Cc: David Brown dav...@codeaurora.org
Cc: Bryan Huntsman bry...@codeaurora.org
.
This follows the model that is used for all other devices
on the msm platform that require a clk reset.
Signed-off-by: Arnd Bergmann a...@arndb.de
Acked-by: Ulf Hansson ulf.hans...@linaro.org
---
arch/arm/mach-msm/board-qsd8x50.c | 18 +-
arch/arm/mach-msm/board-trout
one
device.
Signed-off-by: Arnd Bergmann a...@arndb.de
Acked-by: Ulf Hansson ulf.hans...@linaro.org
---
arch/arm/mach-msm/devices-msm7x00.c | 44 +++
arch/arm/mach-msm/devices-qsd8x50.c | 44 +++
drivers/mmc/host/msm_sdcc.c
other drivers should be added
in the future that use the same data mover, the best approach
would be to convert this code into a dmaengine driver and use
the generic interfaces for that.
Signed-off-by: Arnd Bergmann a...@arndb.de
Acked-by: Ulf Hansson ulf.hans...@linaro.org
---
arch/arm
On 23 March 2015 at 17:47, Georgi Djakov georgi.dja...@linaro.org wrote:
Some versions of this controller do not advertise their 3.0v and
8bit bus-width support capabilities. It is required to explicitly
set these capabilities for the specific controller versions.
Signed-off-by: Georgi Djakov
On 4 March 2015 at 20:32, Arnd Bergmann a...@arndb.de wrote:
This is my final piece of the puzzle for ARMv6/v7 multiplatform
support. In combination with the other patches that are now
at git://kernel.org/pub/scm/linux/kernel/git/arnd/playground.git
multiplatform-4.0-rc2 and the at91 and
On 23 April 2015 at 10:45, Rajendra Nayak rna...@codeaurora.org wrote:
Add runtime PM support to handle (core and iface) clocks for devices
without a controllable power domain. Once the drivers for these devices
are converted to use runtime PM apis, all clock handling (for core and
iface) from
/pm_runtime.c| 47
++
include/linux/pm_clock.h | 10
6 files changed, 54 insertions(+), 143 deletions(-)
I guess you don't need more acks/reviewed by for this patchset. Still,
and also for my own reference.
Acked-by: Ulf Hansson
On 14 April 2015 at 15:12, Rajendra Nayak rna...@codeaurora.org wrote:
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.
Signed-off-by: Rajendra Nayak rna...@codeaurora.org
---
On 24 April 2015 at 12:55, Rajendra Nayak rna...@codeaurora.org wrote:
On 04/24/2015 03:15 PM, Ulf Hansson wrote:
On 14 April 2015 at 15:12, Rajendra Nayak rna...@codeaurora.org wrote:
msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add
On 23 April 2015 at 10:45, Rajendra Nayak rna...@codeaurora.org wrote:
With platform support now in place to manage clocks from within runtime PM
callbacks, get rid of all clock handling from the driver and convert the
driver to use runtime PM apis.
Signed-off-by: Rajendra Nayak
On 27 April 2015 at 04:32, Rajendra Nayak rna...@codeaurora.org wrote:
On 04/24/2015 09:13 PM, Ulf Hansson wrote:
On 24 April 2015 at 12:55, Rajendra Nayak rna...@codeaurora.org wrote:
On 04/24/2015 03:15 PM, Ulf Hansson wrote:
On 14 April 2015 at 15:12, Rajendra Nayak rna
On 24 April 2015 at 12:58, Rajendra Nayak rna...@codeaurora.org wrote:
On 04/24/2015 03:33 PM, Ulf Hansson wrote:
On 23 April 2015 at 10:45, Rajendra Nayak rna...@codeaurora.org wrote:
Add runtime PM support to handle (core and iface) clocks for devices
without a controllable power domain
On 6 July 2015 at 14:16, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
Following changes aimed to fix some aspects of card detection, when
BROKEN_CARD_DETECTION quirk is set.
Changes since first version [1]:
* Patch 1/3 is a modified to first check for MMC_CAP_NONREMOVABLE
and then check
On 6 July 2015 at 13:53, Ivan T. Ivanov ivan.iva...@linaro.org wrote:
Ensure SDCC is working with maximum clock otherwise card
detection could be extremely slow, up to 7 seconds.
Signed-off-by: Ivan T. Ivanov ivan.iva...@linaro.org
Reviewed-by: Georgi Djakov georgi.dja...@linaro.org
[...]
>> Ahh, I see.
>>
>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and
+ Stephen Rothwell
On 25 August 2015 at 14:06, Ulf Hansson ulf.hans...@linaro.org wrote:
On 17 August 2015 at 13:58, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Some of the pin-controllers like the Qualcomms qcom,pm8921, which
require a pinconf to be setup to use pins as gpios
On 17 August 2015 at 13:58, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Some of the pin-controllers like the Qualcomms qcom,pm8921, which
require a pinconf to be setup to use pins as gpios. Using the pins
directly without pinconf setup would result in incorrect output voltage
or
On 17 November 2015 at 23:37, Lina Iyer wrote:
> From: Axel Haslam
>
> From: Axel Haslam
>
> Add the core changes to be able to declare multiple states.
> When trying to set a power domain to off, genpd will be able to
On 17 November 2015 at 23:37, Lina Iyer wrote:
> From: Marc Titinger
>
> This purpose of these debug seq-files is to help investigate
> generic power domain state transitions, based on device constraints.
> requires the "multiple states" patches from
On 17 November 2015 at 23:37, Lina Iyer wrote:
> From: Marc Titinger
>
> From: Marc Titinger
>
> This patch allows cluster-level idle-states to being soaked in as
> generic domain power states, in order for the domain
On 16 December 2015 at 12:44, Ivan T. Ivanov <ivan.iva...@linaro.org> wrote:
>
>> On Dec 16, 2015, at 12:18 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
>>
>> [...]
>>
>>>> It seems like a reasonable assumption that the controller can't cope
&
[...]
>>
>> A general comment. Static functions in genpd shall start with one of
>> the following prefix.
>>
>> genpd_*
>> _genpd_*
>> __genpd_*
>>
>> Please change accordingly.
>
>
> Many static routines were already prefixed like the exported functions with
> "pm_", shall I make a separate
[...]
>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>
On 18 November 2015 at 02:38, Stephen Boyd <sb...@codeaurora.org> wrote:
> On 11/16, Ulf Hansson wrote:
>> [...]
>>
>>
>> >
>> > In case you're wondering, the max frequency for sdc1 on 8974ac is
>> > 400MHz. If it's just a plain 8974pro then t
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