implementation using Intel New Instructions) to leverage cryptd for
asynchronous processing.
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Gabriele Paoloni gabriele.paol...@intel.com
Signed-off-by: Aidan O'Mahony aidan.o.mah
://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/
gcm/gcm-test-vectors.tar.gz
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Gabriele Paoloni gabriele.paol...@intel.com
Signed-off-by: Aidan O'Mahony aidan.o.mah
://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/
gcm/gcm-test-vectors.tar.gz
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Gabriele Paoloni gabriele.paol...@intel.com
Signed-off-by: Aidan O'Mahony aidan.o.mah
://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/
gcm/gcm-test-vectors.tar.gz
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Gabriele Paoloni gabriele.paol...@intel.com
Signed-off-by: Aidan O'Mahony aidan.o.mah
binutils.
Regards,
Tadeusz
Signed-off-by: Aidan O'Mahony aidan.o.mah...@intel.com
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Gabriele Paoloni gabriele.paol...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
arch/x86/crypto/aesni-intel_asm.S | 598
From: Tadeusz Struk tadeusz.st...@intel.com
Date: Sun, 16 Jan 2011 16:41:11 +
Subject: RE: [PATCH] rfc4106, Intel, AES-NI: Don't leak memory in
rfc4106_set_hash_subkey().
Hi Jesper,
Thanks, but I think there is still a problem here. You don't want to kfree
req_data
when the kmalloc failed
From: Tadeusz Struk tadeusz.st...@intel.com
Date: Wed, 9 Mar 2011 15:01:06 +
Subject: [PATCH] RFC4106 AES-GCM Driver - fixed problem with packets that are
not multiple of 64bytes
Hi Herbert,
This patch fixes problem with packets that are not multiple of 64bytes.
Regards,
Tadeusz
Signed-off
allocated 3 times. That's ~0%
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/api.c | 25 ++---
include/linux/crypto.h |3 ++-
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/crypto/api.c b/crypto/api.c
index a2b39c5..0c0f1c3 100644
With DMA-API debug enabled testmgr triggers a DMA-API: device driver maps
memory from stack warning, when tested on a crypto HW accelerator.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/testmgr.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
Third patch adds dh895xcc hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Update to makefiles etc.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Documentation/ioctl/ioctl-number.txt | 1 +
MAINTAINERS | 6 ++
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
firmware/Makefile
on the hardware accelerator and the Quick Assist can be on:
https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang pingchaox.y...@intel.com
On 06/03/2014 12:16 PM, Randy Dunlap wrote:
+source drivers/crypto/qat/Kconfig
Missing that file ^^^
Hi,
Something went wrong. I need to resend v2.
Thanks Randy
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To unsubscribe from this list: send the line unsubscribe linux-crypto in
the body of a message to
on the hardware accelerator and the Quick Assist Technology can be
found on:
https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang
Third patch adds Intel DH895xCC hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Update to makefiles etc.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Documentation/ioctl/ioctl-number.txt | 1 +
MAINTAINERS | 6 ++
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
firmware/Makefile
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang pingchaox.y...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Tadeusz Struk (4):
crypto: Intel(R) QAT driver framework
crypto: Intel(R) QAT FW Loader
crypto: Intel(R) QAT dh895xcc
Update to makefiles etc.
Don't update the firmware/Makefile yet since there is no FW binary in
the crypto repo yet. This will be added later.
v3 - removed change to ./firmware/Makefile
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Third patch adds DH895xCC hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
noise.
Regards,
Tadeusz
On 06/04/2014 03:53 PM, Tadeusz Struk wrote:
Hi,
This patchset adds support for Intel(R) QuickAssist Technology (QAT) and
DH895xCC hardware accelerator.
First patch adds a common infractructure that will be used by all QAT
devices.
Second patch adds a firmware loader
This patch adds FW interface structure definitions.
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/icp_qat_fw.h | 316
.../crypto
...@intel.com
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang pingchaox.y...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Tadeusz Struk (8):
crypto: Update to makefiles
crypto: Intel(R) QAT DH895xcc accelerator
crypto: Intel(R) QAT
This patch adds microcode part of the firmware loader.
v4 - splits FW loader part into two smaller patches.
Acked-by: Bo Cui bo@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Karen Xiang karen.xi...@intel.com
Signed-off-by: Pingchaox Yang
This patch adds DH895xCC hardware specific code.
It hooks to the common infrastructure and provides acceleration for crypto
algorithms.
Acked-by: John Griffin john.grif...@intel.com
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Update to makefiles etc.
Don't update the firmware/Makefile yet since there is no FW binary in
the crypto repo yet. This will be added later.
v3 - removed change to ./firmware/Makefile
Reviewed-by: Bruce W. Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
The following series fixes minor format issues, updates FW info, and fixes
error path crash when no firmware is present.
---
Tadeusz Struk (4):
crypto: qat: Fix random config build warnings
crypto: qat: Updated Firmware Info Metadata
crypto: qat: Fixed new checkpatch warnings
Updated Firmware Info Metadata
Reviewed-by: Bruce Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/Kconfig|1 +
drivers/crypto/qat/qat_dh895xcc/adf_drv.c |1 +
2 files changed, 2 insertions(+)
diff --git a/drivers
Firmware loader crashes when no firmware file is present.
Reviewed-by: Bruce Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_common_drv.h |2 +-
drivers/crypto/qat/qat_common/qat_uclo.c | 10 +-
2 files
Fix random config build warnings:
Implicit-function-declaration ‘__raw_writel’
Cast to pointer from integer of different size [-Wint-to-pointer-cast]
Reviewed-by: Bruce Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common
After updates to checkpatch new warnings pops up this patch fixes them.
Signed-off-by: Bruce Allan bruce.w.al...@intel.com
Acked-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_aer.c|1 +
drivers/crypto/qat/qat_common/adf_cfg.c|3
issue.
Hi,
Minor cleanups for the qat driver.
The last patch fixes SKU1 device startup issue.
Rest of the patches clean up new checkpatch issues plus some minor
and cosmetic updates.
---
Tadeusz Struk (10):
crypto: qat: Fixed SKU1 dev issue
crypto: qat: Cleanup - Use hweight for bit
Remove unnecessary return code variables and change function types
accordingly.
Signed-off-by: Bruce Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_uclo.c | 23 ---
1 file changed, 8 insertions
Removed additional bufer for HW state for partial requests, which are not going
to be supported.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c | 66 +++---
1 file changed, 7 insertions(+), 59 deletions(-)
diff --git
Fix typo. resp_hanlder should be resp_handler
Signed-off-by: Bruce Allan bruce.w.al...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
.../crypto/qat/qat_common/adf_transport_internal.h |2 +-
drivers/crypto/qat/qat_dh895xcc/adf_isr.c |8
2 files
Hi Prarit,
On 10/07/2014 05:12 PM, Prarit Bhargava wrote:
The method in which the qat code determines the numa node for memory
allocations is a bit clunky. On 2 socket, single node systems it is
possible that adf_get_dev_node_id() returns node 1, even though node 1
doesn't exist.
This code
Hi,
These two patches fix invalid (zero length) dma mapping and
enforce numa configuration for maximum performance.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Tadeusz Struk (2):
crypto: qat - Prevent dma mapping zero length assoc data.
crypto: qat - Enforce valid numa
In a system with NUMA configuration we want to enforce that the accelerator is
connected to a node with memory to avoid cross QPI memory transaction.
Otherwise there is no point in using the accelerator as the encryption in
software will be faster.
Signed-off-by: Tadeusz Struk tadeusz.st
Do not attempt to dma map associated data if it is zero length.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/qat/qat_common/qat_algs.c
b/drivers/crypto/qat/qat_common
On 10/08/2014 10:57 AM, Prarit Bhargava wrote:
node = adf_get_dev_node_id(pdev);
^^^ I don't think you should ever make this call. IMO it is wrong to do it
that
way. Just stick with
node = dev_to_node(pdev-dev)
as the line below forces a default to that anyway.
But then
On 10/08/2014 11:35 AM, Prarit Bhargava wrote:
But then how do I know which node I'm physically connected to?
The pci_dev maps to the bus which maps to a numa node. The pci_dev's numa
value
is copied directly from the bus (or busses depending on how deep it is).
I'd argue (strongly) that
On 10/08/2014 12:01 PM, Prarit Bhargava wrote:
No that isn't correct. dev_to_node() will return the node the device is
connected to.
include/linux/device.h:
static inline int dev_to_node(struct device *dev)
{
return dev-numa_node;
}
struct device {
.
int numa_node; /* NUMA node this
On 10/09/2014 04:23 AM, Prarit Bhargava wrote:
int numa_node; /* NUMA node this device is close to */
...
That's just bad english. The numa node value (for pci devices) is
read from the ACPI tables on the system and represents the node that
the pci_dev is connected to.
};
In case
On 10/09/2014 10:32 AM, Prarit Bhargava wrote:
This calculation is sole for multi-socket configuration. This is why is
was introduced and what it was tested for.
There is no point discussing NUMA for single-socket configuration.
Single socket configurations are not NUMA. In this case
On 10/09/2014 02:42 PM, Prarit Bhargava wrote:
I don't think cpu hotplug matters here. This is one (probe) time
determination if the configuration is optimal or not and if it makes
sense to use this accelerator or not.
It absolutely matters. num_online_cpus() *changes* depending on the #
On 10/10/2014 04:23 AM, Prarit Bhargava wrote:
Sure, but I still think that we are safe here.
No, you're not. Dropping a single CPU changes num_online_cpus(), which
results in
static uint8_t adf_get_dev_node_id(struct pci_dev *pdev)
{
unsigned int bus_per_cpu = 0;
On 10/10/2014 03:15 PM, Prarit Bhargava wrote:
In short, that calcuation is wrong. Don't use it; stick with the widely
accepted and used dev_to_node of the pci_dev. It is used in other cases IIRC
to
determine the numa location of the device. It shouldn't be any different for
this driver.
Do not attempt to dma map associated data if it is zero length.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/qat/qat_common/qat_algs.c
b/drivers/crypto/qat/qat_common
In a system with NUMA configuration we want to enforce that the accelerator is
connected to a node with memory to avoid cross QPI memory transaction.
Otherwise there is no point in using the accelerator as the encryption in
software will be faster.
Signed-off-by: Tadeusz Struk tadeusz.st
Hi,
These two patches fix invalid (zero length) dma mapping and
enforce numa configuration for maximum performance.
Change log:
v2 - Removed numa node calculation based bus number and use predefined
functions instead.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Tadeusz Struk (2
On 10/14/2014 03:53 AM, Prarit Bhargava wrote:
-node = adf_get_dev_node_id(pdev);
-accel_dev = kzalloc_node(sizeof(*accel_dev), GFP_KERNEL, node);
+if (num_possible_nodes() 1 dev_to_node(pdev-dev) 0) {
+/* If the accelerator is connected to a node with no memory
+
On 10/14/2014 08:41 AM, Prarit Bhargava wrote:
Oh, that's a really good point. But can you at least change the message to
do a
FW_BUG and dump the node information? That would be useful for debugging.
But this not always will be a FW_BUG. If a user will not populate one of
the nodes with
On 10/15/2014 04:25 AM, Prarit Bhargava wrote:
I just gave a quick run of these patches and they seem to fix the NUMA issue
and
the 0 length warnings.
Tested-by: Nikolay Aleksandrov niko...@redhat.com
Thanks Nik :)
Reviewed-by: Prarit Bhargava pra...@redhat.com
Thank you Nik and
Move PCI BARs definitions to device specific module where it belongs.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_accel_devices.h |2 --
drivers/crypto/qat/qat_common/qat_hal.c|3 ++-
.../crypto/qat/qat_dh895xcc
Hi,
On 11/02/2014 12:35 PM, Stephan Mueller wrote:
+ * type:
+ - blkcipher for symmetric block ciphers
blkcipher for synchronous block ciphers
+ - ablkcipher for asymmetric block ciphers
ablkcipher for asynchronous block ciphers
+ - cipher for single
Add PKE firmware header file and code that loads the PKE firmware.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_accel_devices.h |4 +
drivers/crypto/qat/qat_common/adf_accel_engine.c | 44 -
drivers/crypto/qat/qat_common/adf_ctl_drv.c
is notified when it is ready
by calling select on the socket.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
Tadeusz Struk (4):
crytpo: qat - Fix 64 bytes requests
crypto: qat - Add PKE firmware
crypto: qat - Add userspace instances
crypto: qat - Add new algif
Fix invalid inflights calculation for 64byte PKE requests that will be sent
from userspace.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
.../qat/qat_common/adf_transport_access_macros.h |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto
Add new socket algif interface for userspace for symmetric and asymmetric
crypto.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/Kconfig |9
drivers/crypto/qat/qat_common/Makefile |3
drivers/crypto/qat/qat_common
Add code that creates and manages userspace crypto instances.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_accel_devices.h | 15 +
drivers/crypto/qat/qat_common/adf_cfg_strings.h |1
drivers/crypto/qat/qat_common/adf_common_drv.h| 21
Hi Herbert,
On 11/06/2014 06:56 PM, Herbert Xu wrote:
Add new socket algif interface for userspace for symmetric and asymmetric
crypto.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
No this is not acceptable. algif is meant to expose generic
algorithms to user-space
On 11/06/2014 08:05 PM, Herbert Xu wrote:
I see. What we need to do is first fold the current asymmetric
crypto code under crypto/asymmetric into the crypto API properly
and then export that through algif.
You can then simply implement a hardware driver for such algorithms
as you currently
Hi Herbert,
On 11/06/2014 09:31 PM, Herbert Xu wrote:
On Thu, Nov 06, 2014 at 09:24:22PM -0800, Tadeusz Struk wrote:
What about aead? Using my algif_qat I can build a single request to HW
that preforms both encryption and authentication in one go, ever for
things like aes-cbc-hmac-sha1
Hi,
On 11/06/2014 09:31 PM, Herbert Xu wrote:
On Thu, Nov 06, 2014 at 09:24:22PM -0800, Tadeusz Struk wrote:
What about aead? Using my algif_qat I can build a single request to HW
that preforms both encryption and authentication in one go, ever for
things like aes-cbc-hmac-sha1. This allows
Hi Herbert,
On 11/13/2014 05:19 PM, Herbert Xu wrote:
This way I can get much higher throughput than with algif_skcipher.
Yes that's a worthy optimisation. See if you can change the
current implementation (without changing the interface) to achieve
this.
Ok, I'll have a look. What about the
Use the new memzero_explicit function to cleanup sensitive data.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c | 36 ++
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/crypto/qat/qat_common
On 10/24/2014 07:45 AM, Herbert Xu wrote:
On Wed, Oct 15, 2014 at 07:25:45AM -0400, Prarit Bhargava wrote:
On 10/15/2014 06:35 AM, Nikolay Aleksandrov wrote:
On 14/10/14 03:24, Tadeusz Struk wrote:
Hi,
These two patches fix invalid (zero length) dma mapping and
enforce numa configuration
On 11/17/2014 08:59 AM, Greg KH wrote:
Because it showed up in Linus's tree _after_ 3.17.3-rc1 was released?
How can I go back in time?
I thought it was already possible, no? :)
So will it be in 3.17.4?
Thanks,
Tadeusz
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:
for_each_sg(sgl, sg, sg_nents, i)
sg_virt(sg)
This patch marks the last one with data as the last one to process.
Also removed some unneeded code.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/algif_skcipher.c |6 +-
1 file changed, 1 insertion(+), 5 deletions
Fix invalid inflights calculation for 64 bytes requests.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
.../qat/qat_common/adf_transport_access_macros.h |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qat/qat_common
Hi Herbert,
On 11/25/2014 06:42 AM, Herbert Xu wrote:
Please put these clean-ups in a separate patch.
Ok, will do.
@@ -469,6 +464,7 @@ static int skcipher_recvmsg(struct kiocb *unused,
struct socket *sock,
if (!used)
goto free;
+
Remover unneeded code.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/algif_skcipher.c |4
1 file changed, 4 deletions(-)
diff --git a/crypto/algif_skcipher.c b/crypto/algif_skcipher.c
index 46a0758..1bf31bc 100644
--- a/crypto/algif_skcipher.c
+++ b/crypto
:
for_each_sg(sgl, sg, sg_nents, i)
sg_virt(sg)
This patch marks the last one with data as the last one to process.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/algif_skcipher.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/crypto/algif_skcipher.c b/crypto
Hi Herbert,
On 12/01/2014 06:40 AM, Herbert Xu wrote:
+nents = sg_nents(ctx-rsgl.sg);
+ sg_mark_end(sg[nents - 1]);
Huh? You're getting nents from the RX side and using it to mark
the TX side? This makes no sense because RX may have no relationship
On 12/01/2014 07:00 AM, Herbert Xu wrote:
As I said the two are arbitrary and we don't place any restrictions
on them at all (apart from the fact that the TX length in bytes must
obviously be longer than the RX bytes).
So you can have a 1-element TX list with a multi-element RX list.
Ok, I
Hi,
On 12/02/2014 06:33 AM, Herbert Xu wrote:
I think marking the end is useful. How about doing the marking
and unmarking whenever sgl-cur is updated?
I have a v2 ready where I mark it based on the actual data.
Thanks
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:
for_each_sg(sgl, sg, sg_nents, i)
sg_virt(sg)
This patch marks the last one with data as the last one to process.
Changes:
v2 - use data len to find the last buffer instead of nents in RX list.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/algif_skcipher.c | 22
On 12/02/2014 04:21 AM, Dan Carpenter wrote:
drivers/crypto/qat/qat_common/adf_transport.c
407 /* Enable IRQ coalescing always. This will allow to use
408 * the optimised flag and coalesc register.
409 * If it is disabled in the config file just use min
On 12/02/2014 08:49 AM, Tadeusz Struk wrote:
On 12/02/2014 04:21 AM, Dan Carpenter wrote:
drivers/crypto/qat/qat_common/adf_transport.c
407 /* Enable IRQ coalescing always. This will allow to use
408 * the optimised flag and coalesc register.
409
coalescing on error.
Reported-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/adf_transport.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/qat/qat_common
On 10/13/2014 06:24 PM, Tadeusz Struk wrote:
Hi,
These two patches fix invalid (zero length) dma mapping and
enforce numa configuration for maximum performance.
Change log:
v2 - Removed numa node calculation based bus number and use predefined
functions instead.
Signed-off-by: Tadeusz
data len to find the last buffer instead of nents in RX list.
v3 - Mark/unmark end when data is added and sgl-cur changed.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
crypto/algif_skcipher.c |8
1 file changed, 8 insertions(+)
diff --git a/crypto/algif_skcipher.c b/crypto
Fixed invalid assumpion that the sgl in and sgl out will always have the same
number of entries.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c | 82 +---
drivers/crypto/qat/qat_common/qat_crypto.h |1
2 files
Add support for cbc(aes) ablkcipher.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
Acked-by: Bruce W. Allan bruce.w.al...@intel.com
---
drivers/crypto/qat/qat_common/icp_qat_hw.h |2
drivers/crypto/qat/qat_common/qat_algs.c | 528 ++--
drivers/crypto/qat
On 12/08/2014 12:08 PM, Tadeusz Struk wrote:
Add support for cbc(aes) ablkcipher.
Hi Herbert,
These two:
[PATCH] crypto: qat - add support for cbc(aes) ablkcipher
[PATCH] crypto: qat - Fix assumption that sg in and out will have the...
are generated against cryptodev with these two on top
On 01/25/2015 04:10 PM, Herbert Xu wrote:
On Sun, Jan 25, 2015 at 08:26:50AM -0800, Tadeusz Struk wrote:
Hi Stephan,
On 01/25/2015 12:58 AM, Stephan Mueller wrote:
+static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
+ unsigned int key_len
Changed the __driver-gcm-aes-aesni to be a proper aead algorithm.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
arch/x86/crypto/aesni-intel_glue.c | 53 ++--
1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/x86/crypto/aesni
On 01/15/2015 06:00 PM, Herbert Xu wrote:
But then would you like to extend AIO interface to take the IV and
something that would indicate the encrypt/decrypt operation on
aio_write()? Also as far as I can see AIO doesn't support splice()
Any metadata such as the IV can still go through the
On 01/26/2015 11:20 AM, Stephan Mueller wrote:
Here we have two instances of crypto_aead algorithm, one the
rfc4106(gcm(aes)), whose setkey points to rfc4106_set_key(), and the
internal helper __gcm-aes-aesni (wrapped in by the cryptd interface),
whose setkey points to
On 02/01/2015 10:31 AM, Stephan Mueller wrote:
Hi Tadeusz,
The way the algif_skcipher works currently is that on sendmsg/sendpage it
builds an sgl for the input data and then on read/recvmsg it sends the job
for encryption putting the user to sleep till the data is processed.
This way
by modules
that can use it in interrupt context as we don't have a good fallback mechanism
in this case.
Signed-off-by: Adrian Hoban adrian.ho...@intel.com
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
arch/x86/crypto/aesni-intel_glue.c | 164
1
Hi Stephan,
On 01/17/2015 10:23 AM, Stephan Mueller wrote:
during testing of my algif_aead patch with the different GCM implementations
I
am able to trigger a kernel crash from user space using __driver-gcm-aes-
aesni.
As I hope that algif_aead is going to be included, unprivileged
Hi Herbert,
On 01/13/2015 09:38 PM, Herbert Xu wrote:
What you want is AIO so we should try to use that interface rather
than creating some funky crypto-specific interface.
Dave, the AIO hooks in net/socket.c is currently simply pointing
to the sync implementation. What are you thoughts on
On 01/22/2015 01:20 PM, Stephan Mueller wrote:
That would be correct. But if I understood Herbert correctly, he is
creating a patch that disables these service ciphers for general usage.
Yes, and this should also implicitly fix the problem with user space.
Thanks,
Tadeusz
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On 01/22/2015 02:23 PM, Herbert Xu wrote:
Yes but we should also fix this so that it's a proper aead
algorithm.
Ok, I'll do that.
Thanks,
Tadeusz
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We don't need the qat_auth_state structure anymore.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
drivers/crypto/qat/qat_common/qat_algs.c |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/crypto/qat/qat_common/qat_algs.c
b/drivers/crypto/qat/qat_common/qat_algs.c
On 01/20/2015 05:25 PM, Stephan Mueller wrote:
Rather than adding a bogus setkey function, please fix this mess
properly by moving the top-level setkey function into the __driver
one where it should be. Compare with how we handle it in the
ablk_helper which is pretty much the same thing.
On 01/29/2015 03:13 PM, Tadeusz Struk wrote:
AIO read or write are not currently supported on sockets.
This patch enables real socket async read/write.
Please note - this patch is generated against cryptodev.
Signed-off-by: Tadeusz Struk tadeusz.st...@intel.com
---
include/net/sock.h
Hi Stephan,
On 01/25/2015 12:58 AM, Stephan Mueller wrote:
+static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
+ unsigned int key_len)
{
struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
struct crypto_aead *cryptd_child =
On 02/11/2015 02:28 AM, Markus Stockhausen wrote:
I want to ensure that the key data in an AES ctx structure is 8 byte aligned
to avoid aligment exceptions afterwards. Other fields don't need that
restriction. At the moment I'm using the following (ugly) implementation.
struct ppc_aes_ctx {
On 02/13/2015 08:49 AM, Markus Stockhausen wrote:
thanks for the tip. I will at least move the data definitions to the
beginning of
my structure.
But while it sounds logical for data types that are directly created from
that
structure I'm unsure about a context. If I understand it
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