On Tuesday 15 November 2016 03:21 PM, Mark Rutland wrote:
On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:
On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
+ - scl-id : The Super Cluster ID. This can be the ID
On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:
> On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> >>+ - scl-id : The Super Cluster ID. This can be the ID of the CPU die
> >>+ or IO die in the chip.
>
On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
Hi,
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Hi,
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
>
> Signed-off-by: Anurup M
> Signed-off-by: Shaokun Zhang
> ---
On Thursday 03 November 2016 11:56 PM, Krzysztof Kozlowski wrote:
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Get rid of this weird indentation in all patches.
On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Get rid of this weird indentation in all patches.
>
> Signed-off-by: Anurup M
> Signed-off-by:
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127