[PATCH v4 1/2] kbuild, x86: Track generated headers with generated-y
Track generated header files which aren't already in genhdr-y, alongside generic-y wrappers in the */include/generated/[uapi/]asm/ directories. Currently only x86 generates extra headers in these directories, for the purposes of enumerating system calls for different ABIs, and xen hypercalls. This will allow the asm-generic wrapper handling code to remove stale wrappers when files are removed from generic-y, without also removing these headers which are generated separately. Reported-by: kbuild test robot <fengguang...@intel.com> Signed-off-by: James Hogan <james.ho...@imgtec.com> Acked-by: Arnd Bergmann <a...@arndb.de> Cc: Michal Marek <mma...@suse.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: Ingo Molnar <mi...@redhat.com> Cc: "H. Peter Anvin" <h...@zytor.com> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-kbu...@vger.kernel.org Cc: x...@kernel.org Cc: linux-doc@vger.kernel.org --- Changes in v4: - None (resend). Changes in v2: - New patch (thanks to kbuild test robot). --- Documentation/kbuild/makefiles.txt | 14 ++ arch/x86/include/asm/Kbuild| 6 ++ 2 files changed, 20 insertions(+) diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt index 13f888a02a3d..385a5ef41c17 100644 --- a/Documentation/kbuild/makefiles.txt +++ b/Documentation/kbuild/makefiles.txt @@ -47,6 +47,7 @@ This document describes the Linux kernel Makefiles. --- 7.2 genhdr-y --- 7.3 destination-y --- 7.4 generic-y + --- 7.5 generated-y === 8 Kbuild Variables === 9 Makefile language @@ -1319,6 +1320,19 @@ See subsequent chapter for the syntax of the Kbuild file. Example: termios.h #include + --- 7.5 generated-y + + If an architecture generates other header files alongside generic-y + wrappers, and not included in genhdr-y, then generated-y specifies + them. + + This prevents them being treated as stale asm-generic wrappers and + removed. + + Example: + #arch/x86/include/asm/Kbuild + generated-y += syscalls_32.h + === 8 Kbuild Variables The top Makefile exports the following variables: diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild index aeac434c9feb..2cfed174e3c9 100644 --- a/arch/x86/include/asm/Kbuild +++ b/arch/x86/include/asm/Kbuild @@ -1,5 +1,11 @@ +generated-y += syscalls_32.h +generated-y += syscalls_64.h +generated-y += unistd_32_ia32.h +generated-y += unistd_64_x32.h +generated-y += xen-hypercalls.h + genhdr-y += unistd_32.h genhdr-y += unistd_64.h genhdr-y += unistd_x32.h -- 2.4.10 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] KVM: MIPS: Implement EXIT_VM hypercall
Implement the MIPS EXIT_VM hypercall used by paravirtual guest kernels. When the guest performs this hypercall, the request is passed to userland in the form of a KVM_EXIT_SYSTEM_EVENT exit reason with system event type KVM_SYSTEM_EVENT_SHUTDOWN. We also document the hypercall along with the others as the documentation was never added. Signed-off-by: James Hogan <james.ho...@imgtec.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: "Radim Krčmář" <rkrc...@redhat.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com> Cc: David Daney <david.da...@cavium.com> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-m...@linux-mips.org Cc: k...@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/virtual/kvm/hypercalls.txt | 6 ++ arch/mips/kvm/hypcall.c | 9 + 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/Documentation/virtual/kvm/hypercalls.txt b/Documentation/virtual/kvm/hypercalls.txt index e9f1c9d3da98..f8108c84c46b 100644 --- a/Documentation/virtual/kvm/hypercalls.txt +++ b/Documentation/virtual/kvm/hypercalls.txt @@ -92,3 +92,9 @@ is used in the hypercall for future use. Architecture: mips Status: active Purpose: Return the frequency of CP0_Count in HZ. + +7. KVM_HC_MIPS_EXIT_VM + +Architecture: mips +Status: active +Purpose: Shut down the virtual machine. diff --git a/arch/mips/kvm/hypcall.c b/arch/mips/kvm/hypcall.c index 7c74ec25f2b9..c3345e5eec02 100644 --- a/arch/mips/kvm/hypcall.c +++ b/arch/mips/kvm/hypcall.c @@ -40,6 +40,15 @@ static int kvm_mips_hypercall(struct kvm_vcpu *vcpu, unsigned long num, *hret = (s32)vcpu->arch.count_hz; break; + case KVM_HC_MIPS_EXIT_VM: + /* Pass shutdown system event to userland */ + memset(>run->system_event, 0, + sizeof(vcpu->run->system_event)); + vcpu->run->system_event.type = KVM_SYSTEM_EVENT_SHUTDOWN; + vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; + ret = RESUME_HOST; + break; + default: /* Report unimplemented hypercall to guest */ *hret = -KVM_ENOSYS; -- git-series 0.8.10 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] KVM: MIPS: Implement HYPCALL emulation
Emulate the HYPCALL instruction added in the VZ ASE and used by the MIPS
paravirtualised guest support that is already merged. The new hypcall.c
handles arguments and the return value, and will handle the individual
hypercalls in upcoming commits.
Non-zero HYPCALL codes are not handled.
We also document the hypercall ABI which asm/kvm_para.h uses.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com>
Cc: David Daney <david.da...@cavium.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/hypercalls.txt | 5 ++-
arch/mips/include/asm/kvm_host.h | 7 +++-
arch/mips/include/uapi/asm/inst.h| 2 +-
arch/mips/kvm/Makefile | 1 +-
arch/mips/kvm/emulate.c | 3 +-
arch/mips/kvm/hypcall.c | 53 +-
arch/mips/kvm/trap_emul.c| 4 ++-
7 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/kvm/hypcall.c
diff --git a/Documentation/virtual/kvm/hypercalls.txt
b/Documentation/virtual/kvm/hypercalls.txt
index c8d040e27046..8f36582ce2b7 100644
--- a/Documentation/virtual/kvm/hypercalls.txt
+++ b/Documentation/virtual/kvm/hypercalls.txt
@@ -28,6 +28,11 @@ S390:
property inside the device tree's /hypervisor node.
For more information refer to Documentation/virtual/kvm/ppc-pv.txt
+MIPS:
+ KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall
+ number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
+ the return value is placed in $2 (v0).
+
KVM Hypercalls Documentation
===
The template for each hypercall is:
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 05e785fc061d..0d308d4f2429 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -229,6 +229,7 @@ enum emulation_result {
EMULATE_WAIT, /* WAIT instruction */
EMULATE_PRIV_FAIL,
EMULATE_EXCEPT, /* A guest exception has been generated */
+ EMULATE_HYPERCALL, /* HYPCALL instruction */
};
#define mips3_paddr_to_tlbpfn(x) \
@@ -832,6 +833,12 @@ unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu
*vcpu);
unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
+/* Hypercalls (hypcall.c) */
+
+enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
+ union mips_instruction inst);
+int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
+
/* Dynamic binary translation */
extern int kvm_mips_trans_cache_index(union mips_instruction inst,
u32 *opc, struct kvm_vcpu *vcpu);
diff --git a/arch/mips/include/uapi/asm/inst.h
b/arch/mips/include/uapi/asm/inst.h
index 77429d1622b3..b5e46ae872d3 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -179,7 +179,7 @@ enum cop0_coi_func {
tlbr_op = 0x01, tlbwi_op = 0x02,
tlbwr_op = 0x06, tlbp_op = 0x08,
rfe_op= 0x10, eret_op = 0x18,
- wait_op = 0x20,
+ wait_op = 0x20, hypcall_op= 0x28
};
/*
diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile
index 847429de780d..e56403c8a3f5 100644
--- a/arch/mips/kvm/Makefile
+++ b/arch/mips/kvm/Makefile
@@ -10,6 +10,7 @@ common-objs-$(CONFIG_CPU_HAS_MSA) += msa.o
kvm-objs := $(common-objs-y) mips.o emulate.o entry.o \
interrupt.o stats.o commpage.o \
dyntrans.o trap_emul.o fpu.o
+kvm-objs += hypcall.o
kvm-objs += mmu.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index d40cfaad4529..637753ea0a00 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -1143,6 +1143,9 @@ enum emulation_result kvm_mips_emulate_CP0(union
mips_instruction inst,
case wait_op:
er = kvm_mips_emul_wait(vcpu);
break;
+ case hypcall_op:
+ er = kvm_mips_emul_hypcall(vcpu, inst);
+ break;
}
} else {
rt = inst.c0r_format.rt;
diff --git a/arch/mips/kvm/hypcall.c b/arch/mips/kvm/hypcall.c
new file mode 100644
index ..83063435195f
--- /dev/null
+++ b/arch/mips/kvm/hypcall.c
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * KVM/MIPS: Hypercall hand
[PATCH 0/4] KVM: MIPS: Hypercalls
This series implements some basic hypercalls for MIPS KVM, as used by the MIPS paravirtual platform support in Linux and provided by Cavium's VZ KVM implementation. - Patch 1 hooks up trap & emulate to some minimal hypercall infrastructure without any hypercalls implemented yet. VZ support when it comes will also hook into the same infrastructure. - Patches 2-3 implement GET_CLOCK_FREQ and EXIT_VM hypercalls. - Patch 4 implements the console output hypercall by using KVM_EXIT_HYPERCALL (i.e. delegating the hypercall to userland). Its unclear if there is a more preferable approach to this, so comments particularly appreciated here. Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: "Radim Krčmář" <rkrc...@redhat.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com> Cc: David Daney <david.da...@cavium.com> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-m...@linux-mips.org Cc: k...@vger.kernel.org Cc: linux-doc@vger.kernel.org James Hogan (4): KVM: MIPS: Implement HYPCALL emulation KVM: MIPS: Implement GET_CLOCK_FREQ hypercall KVM: MIPS: Implement EXIT_VM hypercall KVM: MIPS: Implement console output hypercall Documentation/virtual/kvm/hypercalls.txt | 27 +++- arch/mips/include/asm/kvm_host.h | 11 +++- arch/mips/include/uapi/asm/inst.h| 2 +- arch/mips/kvm/Makefile | 1 +- arch/mips/kvm/emulate.c | 3 +- arch/mips/kvm/hypcall.c | 94 +- arch/mips/kvm/mips.c | 3 +- arch/mips/kvm/trap_emul.c| 4 +- 8 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 arch/mips/kvm/hypcall.c -- git-series 0.8.10 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4] KVM: MIPS: Implement console output hypercall
Implement console output hypercall by exiting back to userland with
KVM_EXIT_HYPERCALL, and setting the return value on next KVM_RUN.
We also document the hypercall along with the others as the
documentation was never added
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com>
Cc: David Daney <david.da...@cavium.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt seems to suggest that
KVM_EXIT_HYPERCALL is obsolete. When it suggests using KVM_EXIT_MMIO,
does it simply mean the guest should use MMIO to some virtio device of
some sort rather than using hypercalls, or that the hypercall should
somehow be munged into the mmio exit information?
---
Documentation/virtual/kvm/hypercalls.txt | 10 ++
arch/mips/include/asm/kvm_host.h | 4
arch/mips/kvm/hypcall.c | 20
arch/mips/kvm/mips.c | 3 +++
4 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/hypercalls.txt
b/Documentation/virtual/kvm/hypercalls.txt
index f8108c84c46b..4e6e57026bfe 100644
--- a/Documentation/virtual/kvm/hypercalls.txt
+++ b/Documentation/virtual/kvm/hypercalls.txt
@@ -98,3 +98,13 @@ Purpose: Return the frequency of CP0_Count in HZ.
Architecture: mips
Status: active
Purpose: Shut down the virtual machine.
+
+8. KVM_HC_MIPS_CONSOLE_OUTPUT
+
+Architecture: mips
+Status: active
+Purpose: Output a string to a console.
+Argument 1 contains the virtual terminal number to write to.
+Argument 2 contains a guest virtual address pointer to the string, which must
+be in an unmapped virtual memory segment (e.g. KSeg0, KSeg1 or XKPhys).
+Argument 3 contains the number of bytes to write.
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 0d308d4f2429..e0f1da0c35e9 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -309,6 +309,9 @@ struct kvm_vcpu_arch {
/* GPR used as IO source/target */
u32 io_gpr;
+ /* Whether a hypercall needs completing */
+ int hypercall_needed;
+
struct hrtimer comparecount_timer;
/* Count timer control KVM register */
u32 count_ctl;
@@ -838,6 +841,7 @@ unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
union mips_instruction inst);
int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
+void kvm_mips_complete_hypercall(struct kvm_vcpu *vcpu, struct kvm_run *run);
/* Dynamic binary translation */
extern int kvm_mips_trans_cache_index(union mips_instruction inst,
diff --git a/arch/mips/kvm/hypcall.c b/arch/mips/kvm/hypcall.c
index c3345e5eec02..9cb8f37ca43a 100644
--- a/arch/mips/kvm/hypcall.c
+++ b/arch/mips/kvm/hypcall.c
@@ -33,6 +33,7 @@ static int kvm_mips_hypercall(struct kvm_vcpu *vcpu, unsigned
long num,
const unsigned long *args, unsigned long *hret)
{
int ret = RESUME_GUEST;
+ int i;
switch (num) {
case KVM_HC_MIPS_GET_CLOCK_FREQ:
@@ -49,6 +50,19 @@ static int kvm_mips_hypercall(struct kvm_vcpu *vcpu,
unsigned long num,
ret = RESUME_HOST;
break;
+ /* Hypercalls passed to userland to handle */
+ case KVM_HC_MIPS_CONSOLE_OUTPUT:
+ /* Pass to userland via KVM_EXIT_HYPERCALL */
+ memset(>run->hypercall, 0, sizeof(vcpu->run->hypercall));
+ vcpu->run->hypercall.nr = num;
+ for (i = 0; i < MAX_HYPCALL_ARGS; ++i)
+ vcpu->run->hypercall.args[i] = args[i];
+ vcpu->run->hypercall.ret = -KVM_ENOSYS; /* default */
+ vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
+ vcpu->arch.hypercall_needed = 1;
+ ret = RESUME_HOST;
+ break;
+
default:
/* Report unimplemented hypercall to guest */
*hret = -KVM_ENOSYS;
@@ -72,3 +86,9 @@ int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu)
return kvm_mips_hypercall(vcpu, num,
args, >arch.gprs[2] /* v0 */);
}
+
+void kvm_mips_complete_hypercall(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ vcpu->arch.gprs[2] = run->hypercall.ret;/* v0 */
+ vcpu->arch.hypercall_needed = 0;
+}
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index 31ee5ee0010b..1c23dc29db5d 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -409,6 +409,9 @@ int
[PATCH 2/4] KVM: MIPS: Implement GET_CLOCK_FREQ hypercall
Implement the MIPS GET_CLOCK_FREQ hypercall used by paravirtual guest
kernels. When the guest performs this hypercall, the value of count_hz
is returned, which is the current rate of the CP0_Count register.
We also document the hypercall along with the others as the
documentation was never added.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com>
Cc: David Daney <david.da...@cavium.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/hypercalls.txt | 6 ++
arch/mips/kvm/hypcall.c | 18 +++---
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/Documentation/virtual/kvm/hypercalls.txt
b/Documentation/virtual/kvm/hypercalls.txt
index 8f36582ce2b7..e9f1c9d3da98 100644
--- a/Documentation/virtual/kvm/hypercalls.txt
+++ b/Documentation/virtual/kvm/hypercalls.txt
@@ -86,3 +86,9 @@ the vcpu to sleep until occurrence of an appropriate event.
Another vcpu of the
same guest can wakeup the sleeping vcpu by issuing KVM_HC_KICK_CPU hypercall,
specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)
is used in the hypercall for future use.
+
+6. KVM_HC_MIPS_GET_CLOCK_FREQ
+
+Architecture: mips
+Status: active
+Purpose: Return the frequency of CP0_Count in HZ.
diff --git a/arch/mips/kvm/hypcall.c b/arch/mips/kvm/hypcall.c
index 83063435195f..7c74ec25f2b9 100644
--- a/arch/mips/kvm/hypcall.c
+++ b/arch/mips/kvm/hypcall.c
@@ -32,9 +32,21 @@ enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu
*vcpu,
static int kvm_mips_hypercall(struct kvm_vcpu *vcpu, unsigned long num,
const unsigned long *args, unsigned long *hret)
{
- /* Report unimplemented hypercall to guest */
- *hret = -KVM_ENOSYS;
- return RESUME_GUEST;
+ int ret = RESUME_GUEST;
+
+ switch (num) {
+ case KVM_HC_MIPS_GET_CLOCK_FREQ:
+ /* Return frequency of count/compare timer */
+ *hret = (s32)vcpu->arch.count_hz;
+ break;
+
+ default:
+ /* Report unimplemented hypercall to guest */
+ *hret = -KVM_ENOSYS;
+ break;
+ };
+
+ return ret;
}
int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu)
--
git-series 0.8.10
--
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Re: [PATCH 4/4] KVM: MIPS: Implement console output hypercall
On Mon, Feb 06, 2017 at 02:25:59PM +0100, Paolo Bonzini wrote: > > > On 06/02/2017 11:46, James Hogan wrote: > > Documentation/virtual/kvm/api.txt seems to suggest that > > KVM_EXIT_HYPERCALL is obsolete. When it suggests using KVM_EXIT_MMIO, > > does it simply mean the guest should use MMIO to some virtio device of > > some sort rather than using hypercalls, or that the hypercall should > > somehow be munged into the mmio exit information? > > The former. Okay, thanks. > > But there are cases when using hypercalls is unavoidable. In that case > the trend is to use other exit reasons than KVM_EXIT_HYPERCALL, such as > KVM_EXIT_PAPR_HCALL in PowerPC. Feel free to add KVM_EXIT_MIPS_CONOUT > or something like that. Okay, that sounds sensible. The existing mips_paravirt_defconfig does contain CONFIG_VIRTIO_CONSOLE=y though, so I'm thinking we may be able to get away without this hypercall and without old paravirt guest kernels becoming unusable. David/Andreas: would you agree, or do you feel strongly that this hypercall API should be kept? (with a different KVM exit reason) > > How would you find the character device to write to in QEMU? I imagine it'd need a custom character device driver in QEMU so it could be wired up to stdio/pty or whatever using QEMU arguments. I've only tested it with a test case in my own MIPS KVM test suite so far though. Cheers James signature.asc Description: Digital signature
[PATCH 23/32] KVM: MIPS: Implement VZ support
Add the main support for the MIPS Virtualization ASE (A.K.A. VZ) to MIPS
KVM. The bulk of this work is in vz.c, with various new state and
definitions elsewhere.
Enough is implemented to be able to run on a minimal VZ core. Further
patches will fill out support for guest features which are optional or
can be disabled.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt |2 +-
arch/mips/include/asm/cpu-info.h |1 +-
arch/mips/include/asm/kvm_host.h | 42 +-
arch/mips/kernel/time.c |1 +-
arch/mips/kvm/interrupt.h |5 +-
arch/mips/kvm/mips.c |6 +-
arch/mips/kvm/mmu.c | 20 +-
arch/mips/kvm/tlb.c |7 +-
arch/mips/kvm/trace.h | 15 +-
arch/mips/kvm/vz.c| 2380 ++-
10 files changed, 2479 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/kvm/vz.c
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index cfe9f8b04b5e..996a388f05c5 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2075,6 +2075,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
MIPS | KVM_REG_MIPS_CP0_USERLOCAL| 64
MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
+ MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN| 32
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
@@ -2094,6 +2095,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_CONFIG4 | 32
MIPS | KVM_REG_MIPS_CP0_CONFIG5 | 32
MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32
+ MIPS | KVM_REG_MIPS_CP0_XCONTEXT | 64
MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH1| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH2| 64
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 4113796e0ef4..be3b4c25f335 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -110,6 +110,7 @@ struct cpuinfo_mips {
struct guest_info guest;
unsigned intgtoffset_mask;
unsigned intguestid_mask;
+ unsigned intguestid_cache;
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 6c1b5bedf7e9..41d8abc1d6fa 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -10,6 +10,7 @@
#ifndef __MIPS_KVM_HOST_H__
#define __MIPS_KVM_HOST_H__
+#include
#include
#include
#include
@@ -73,6 +74,11 @@
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HALT_POLL_NS_DEFAULT 50
+#ifdef CONFIG_KVM_MIPS_VZ
+extern unsigned long GUESTID_MASK;
+extern unsigned long GUESTID_FIRST_VERSION;
+extern unsigned long GUESTID_VERSION_MASK;
+#endif
/*
@@ -167,6 +173,8 @@ struct kvm_arch_memory_slot {
struct kvm_arch {
/* Guest physical mm */
struct mm_struct gpa_mm;
+ /* Mask of CPUs needing GPA ASID flush */
+ cpumask_t asid_flush_mask;
};
#define N_MIPS_COPROC_REGS 32
@@ -224,6 +232,11 @@ struct mips_coproc {
#define MIPS_CP0_CONFIG4_SEL 4
#define MIPS_CP0_CONFIG5_SEL 5
+#define MIPS_CP0_GUESTCTL2 10
+#define MIPS_CP0_GUESTCTL2_SEL 5
+#define MIPS_CP0_GTOFFSET 12
+#define MIPS_CP0_GTOFFSET_SEL 7
+
/* Resume Flags */
#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
@@ -359,7 +372,20 @@ struct kvm_vcpu_arch {
/* Cache some mmu pages needed inside spinlock regions */
struct kvm_mmu_memory_cache mmu_page_cache;
+#ifdef CONFIG_KVM_MIPS_VZ
+ /* vcpu's vzguestid is different on each host cpu in an smp system */
+ u32 vzguestid[NR_CPUS];
+
+ /* wired guest TLB entries */
+ struct kvm_mips_tlb *wired_tlb;
+ unsigned int wired_tlb_limit;
+ unsigned int wired_tlb_used;
+#endif
+
+ /* Last CPU the VCPU state was loaded on */
int last_sched_cpu;
+ /* Last CPU the VCPU actually executed guest code on */
+ int last_exec_cpu;
/* WAIT executed */
int wait;
@@ -663,6 +689,7 @@ __BUILD_KVM_RW_HW(config4,32, MIPS_CP0_CONFIG,
4)
__BUILD_KVM_RW_HW(config5,32, MIPS_CP0_CONFIG, 5)
__BUILD_KVM_RW_HW(config6,32, MIPS_CP0_CONFIG, 6)
__BUILD_KVM_RW_HW(config7,32
[PATCH 27/32] KVM: MIPS/VZ: Support guest segmentation control
Add support for VZ guest CP0_SegCtl0, CP0_SegCtl1, and CP0_SegCtl2
registers, as found on P5600 and P6600 cores. These guest registers need
initialising, context switching, and exposing via the KVM ioctl API when
they are present.
They also require the GVA -> GPA translation code for handling a GVA
root exception to be updated to interpret the segmentation registers and
decode the faulting instruction enough to detect EVA memory access
instructions.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 3 +-
arch/mips/include/asm/kvm_host.h | 6 +-
arch/mips/kvm/vz.c| 242 ++-
3 files changed, 250 insertions(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 04e5c4dae523..1116becf8d6f 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2078,6 +2078,9 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN| 32
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index d3b377dbed36..f986907a7707 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -39,6 +39,9 @@
#define KVM_REG_MIPS_CP0_XCONTEXTCONFIGMIPS_CP0_64(4, 3)
#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2)
+#define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3)
+#define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4)
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
#define KVM_REG_MIPS_CP0_HWRENAMIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
@@ -675,6 +678,9 @@ __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT,
2)
__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
__BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
__BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
+__BUILD_KVM_RW_HW(segctl0,l, MIPS_CP0_TLB_PG_MASK, 2)
+__BUILD_KVM_RW_HW(segctl1,l, MIPS_CP0_TLB_PG_MASK, 3)
+__BUILD_KVM_RW_HW(segctl2,l, MIPS_CP0_TLB_PG_MASK, 4)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR,0)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index b1a7485196a6..373b954a9fd3 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -412,6 +412,117 @@ static void kvm_vz_save_timer(struct kvm_vcpu *vcpu)
}
/**
+ * is_eva_access() - Find whether an instruction is an EVA memory accessor.
+ * @inst: 32-bit instruction encoding.
+ *
+ * Finds whether @inst encodes an EVA memory access instruction, which would
+ * indicate that emulation of it should access the user mode address space
+ * instead of the kernel mode address space. This matters for MUSUK segments
+ * which are TLB mapped for user mode but unmapped for kernel mode.
+ *
+ * Returns:Whether @inst encodes an EVA accessor instruction.
+ */
+static bool is_eva_access(union mips_instruction inst)
+{
+ if (inst.spec3_format.opcode != spec3_op)
+ return false;
+
+ switch (inst.spec3_format.func) {
+ case lwle_op:
+ case lwre_op:
+ case cachee_op:
+ case sbe_op:
+ case she_op:
+ case sce_op:
+ case swe_op:
+ case swle_op:
+ case swre_op:
+ case prefe_op:
+ case lbue_op:
+ case lhue_op:
+ case lbe_op:
+ case lhe_op:
+ case lle_op:
+ case lwe_op:
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * is_eva_am_mapped() - Find whether an access mode is mapped.
+ * @vcpu: KVM VCPU state.
+ * @am:3-bit encoded access mode.
+ * @eu:Segment becomes unmapped and uncached when Status.ERL=1.
+ *
+ * Decode @am to find whether it encodes a mapped segment for the current VCPU
+ * state. Where necessary @eu and the actual instruction causing the fault are
+ * taken into account to make the decision.
+ *
+ * Returns:Whether the VCPU faulted on a TLB mapped address.
+ */
+static bool is_eva_am
[PATCH 30/32] KVM: MIPS/VZ: Emulate MAARs when necessary
Add emulation of Memory Accessibility Attribute Registers (MAARs) when
necessary. We can't actually do anything with whatever the guest
provides, but it may not be possible to clear Guest.Config5.MRP so we
have to emulate at least a pair of MAARs.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 5 +-
arch/mips/include/asm/kvm_host.h | 5 +-
arch/mips/include/uapi/asm/kvm.h | 20 +-
arch/mips/kvm/trace.h | 2 +-
arch/mips/kvm/vz.c| 110 ++-
5 files changed, 137 insertions(+), 5 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index a0430186dbd4..c4e43aeadb10 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2114,6 +2114,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_KSCRATCH4| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH5| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH6| 64
+ MIPS | KVM_REG_MIPS_CP0_MAAR(0..63) | 64
MIPS | KVM_REG_MIPS_COUNT_CTL| 64
MIPS | KVM_REG_MIPS_COUNT_RESUME | 64
MIPS | KVM_REG_MIPS_COUNT_HZ | 64
@@ -2180,6 +2181,10 @@ hardware, host kernel, guest, and whether XPA is present
in the guest, i.e.
with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and
the PFNX field starting at bit 30.
+MIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit
+patterns:
+ 0x7030 0001 01
+
MIPS KVM control registers (see above) have the following id bit patterns:
0x7030 0002
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 6b7d131565cd..3b381b52fd6c 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -67,6 +67,7 @@
#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2)
#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
@@ -391,6 +392,9 @@ struct kvm_vcpu_arch {
struct kvm_mips_tlb *wired_tlb;
unsigned int wired_tlb_limit;
unsigned int wired_tlb_used;
+
+ /* emulated guest MAAR registers */
+ unsigned long maar[6];
#endif
/* Last CPU the VCPU state was loaded on */
@@ -711,6 +715,7 @@ __BUILD_KVM_RW_HW(config4,32, MIPS_CP0_CONFIG,
4)
__BUILD_KVM_RW_HW(config5,32, MIPS_CP0_CONFIG, 5)
__BUILD_KVM_RW_HW(config6,32, MIPS_CP0_CONFIG, 6)
__BUILD_KVM_RW_HW(config7,32, MIPS_CP0_CONFIG, 7)
+__BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2)
__BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0)
__BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0)
__BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2)
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index a8a0199bf760..3107095d7f0a 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -54,9 +54,14 @@ struct kvm_fpu {
* Register set = 0: GP registers from kvm_regs (see definitions below).
*
* Register set = 1: CP0 registers.
- * bits[15..8] - Must be zero.
- * bits[7..3] - Register 'rd' index.
- * bits[2..0] - Register 'sel' index.
+ * bits[15..8] - COP0 register set.
+ *
+ * COP0 register set = 0: Main CP0 registers.
+ * bits[7..3] - Register 'rd' index.
+ * bits[2..0] - Register 'sel' index.
+ *
+ * COP0 register set = 1: MAARs.
+ * bits[7..0] - MAAR index.
*
* Register set = 2: KVM specific registers (see definitions below).
*
@@ -115,6 +120,15 @@ struct kvm_fpu {
/*
+ * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
+ */
+
+#define KVM_REG_MIPS_MAAR (KVM_REG_MIPS_CP0 | (1 << 8))
+#define KVM_REG_MIPS_CP0_MAAR(n) (KVM_REG_MIPS_MAAR | \
+KVM_REG_SIZE_U64 | (n))
+
+
+/*
* KVM_REG_MIPS_KVM - KVM specific control registers.
*/
diff --git a/arch/mips/kvm/trace.h b/arch/mips/kvm/trace.h
index d80d37a1b82e..affde8a2c584 100644
--- a/arch/mips/kvm/trace.h
+++ b/arch/mips/kvm/trace.h
@@ -176,6 +176,8 @@ TRACE_EVENT(kvm_exit,
{ KVM_TRACE_COP0(16, 4),"Config4" },\
{ KVM_TRACE_COP0(16, 5),"Config5" },\
{ KVM_TRACE_COP0(16, 7),
[PATCH 0/32] KVM: MIPS: Add VZ support
This series is based on kvm/next (Linus' 4.11 KVM merge) with my recent
hypercall series (which will likely be revised).
My hope is to take this series via the MIPS KVM tree for 4.12, with a
topic branch containing the MIPS architecture changes (patches 1-6).
This series implements basic support for the MIPS Virtualization Module
(generally known as VZ) in KVM, which adds a new "guest" processor mode
with a partial guest Cop0 state and guest TLB to complement the existing
"root" (host) modes & state, allowing for far fewer traps to the
hypervisor compared to the existing Trap & Emulate implementation of KVM
for MIPS, as well as fully virtualizing the guest virtual memory space
to run unmodified kernels.
The MIPS32 and MIPS64 VZ architecture documentation can be found here:
http://wiki.prplfoundation.org/w/images/f/fd/MD00846-2B-VZMIPS32-AFP-01.06.pdf
http://wiki.prplfoundation.org/w/images/f/fe/MD00847-2B-VZMIPS64-AFP-01.06.pdf
We primarily support the ImgTec P5600, P6600, and I6400 cores so far,
including the following VZ / guest hardware features:
- MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6
- TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III)
- Shared physical root/guest TLB (IMG cores)
- FPU / MSA
- Cop0 timer (up to 1GHz for now due to soft timer limit)
- Segmentation control (EVA)
- Hardware page table walker (HTW) both for root and guest TLB
Limitations:
- Support for Cavium Octeon III will follow shortly in a separate series
- Perf counters and watch registers not exposed to guest in this series
(the patches require some further cleanup)
- Guest microMIPS not supported yet (e.g. M5150)
- Guest XPA not supported yet (e.g. P5600)
We start with some preliminary MIPS changes in patches 1-6, including
some MAAR definition refactoring for XPA and some new guest capabilities
and accessors.
Patches 7-16 make preliminary VZ changes in KVM, including 64-bit MMIO
support, the VZ and 64BIT KVM capabilities, and new implementation
callbacks used by the VZ implementation.
Patches 17-22 get into some meatier KVM changes for VZ, such as
abstracting guest register access and adding VZ entry and TLB management
code.
Patches 23-24 add the bulk of the core VZ support and enable it in the
build system.
Patches 25-30 then go on to implement support for various optional
architectural features, such as segmentation control (EVA) and hardware
page table walkers (HTW). Context switching of the guest state may be
incomplete on certain cores without these patches if the features in
question can't be disabled in the guest context.
Finally patches 31-32 implement support for features that can be easily
disabled at runtime, namely the hardware guest timer (which can be
emulated in software before patch 31) and tracing of guest mode changes
using VZ's CP0_GuestCtl0.MC bit.
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: Paul Burton <paul.bur...@imgtec.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
James Hogan (32):
MIPS: Add defs & probing of UFR
MIPS: Separate MAAR V bit into VL and VH for XPA
MIPS: Probe guest CP0_UserLocal
MIPS: Probe guest MVH
MIPS: Add some missing guest CP0 accessors & defs
MIPS: asm/tlb.h: Add UNIQUE_GUEST_ENTRYHI() macro
KVM: MIPS/Emulate: De-duplicate MMIO emulation
KVM: MIPS/Emulate: Implement 64-bit MMIO emulation
KVM: MIPS: Update kvm_lose_fpu() for VZ
KVM: MIPS: Extend counters & events for VZ GExcCodes
KVM: MIPS: Add VZ capability
KVM: MIPS: Add 64BIT capability
KVM: MIPS: Init timer frequency from callback
KVM: MIPS: Add callback to check extension
KVM: MIPS: Add hardware_{enable,disable} callback
KVM: MIPS: Add guest exit exception callback
KVM: MIPS: Abstract guest CP0 register access for VZ
KVM: MIPS/Entry: Update entry code to support VZ
KVM: MIPS/TLB: Add VZ TLB management
KVM: MIPS/Emulate: Update CP0_Compare emulation for VZ
KVM: MIPS/Emulate: Drop CACHE emulation for VZ
KVM: MIPS: Update exit handler for VZ
KVM: MIPS: Implement VZ support
KVM: MIPS: Add VZ support to build system
KVM: MIPS/VZ: Support guest CP0_BadInstr[P]
KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig
KVM: MIPS/VZ: Support guest segmentation control
KVM: MIPS/VZ: Support guest hardware page table walker
KVM: MIPS/VZ: Support guest load-linked bit
KVM: MIPS/VZ: Emulate MAARs when necessary
KVM: MIPS/VZ: Support hardware guest timer
KVM: MIPS/VZ: Trace guest mode changes
Documentation/virtual/kvm/api.txt| 81 +-
arch/mips/include/asm/cpu-features.h | 10 +-
arch/mips/include/asm/cpu-info.h |2 +-
arch/mips/include/asm/cpu.h |1 +-
arch/mips/include/asm/kvm_host.h |
[PATCH 25/32] KVM: MIPS/VZ: Support guest CP0_BadInstr[P]
Add support for VZ guest CP0_BadInstr and CP0_BadInstrP registers, as
found on most VZ capable cores. These guest registers need context
switching, and exposing via the KVM ioctl API when they are present.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 2 +-
arch/mips/include/asm/kvm_host.h | 4 +++-
arch/mips/kvm/vz.c| 46 -
3 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 996a388f05c5..a654a2133981 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2079,6 +2079,8 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
+ MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32
+ MIPS | KVM_REG_MIPS_CP0_BADINSTRP| 32
MIPS | KVM_REG_MIPS_CP0_COUNT| 32
MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 41d8abc1d6fa..53c92f34475f 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -40,6 +40,8 @@
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
#define KVM_REG_MIPS_CP0_HWRENAMIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1)
+#define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2)
#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
@@ -672,6 +674,8 @@ __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK,
1)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR,0)
+__BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR,1)
+__BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR,2)
__BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT,0)
__BUILD_KVM_RW_HW(entryhi,l, MIPS_CP0_TLB_HI, 0)
__BUILD_KVM_RW_HW(compare,32, MIPS_CP0_COMPARE, 0)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 30c3550926b0..5fd14d35c146 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1220,6 +1220,10 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu
*vcpu)
ret = ARRAY_SIZE(kvm_vz_get_one_regs);
if (cpu_guest_has_userlocal)
++ret;
+ if (cpu_guest_has_badinstr)
+ ++ret;
+ if (cpu_guest_has_badinstrp)
+ ++ret;
ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
return ret;
@@ -1241,6 +1245,18 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu
*vcpu, u64 __user *indices)
return -EFAULT;
++indices;
}
+ if (cpu_guest_has_badinstr) {
+ index = KVM_REG_MIPS_CP0_BADINSTR;
+ if (copy_to_user(indices, , sizeof(index)))
+ return -EFAULT;
+ ++indices;
+ }
+ if (cpu_guest_has_badinstrp) {
+ index = KVM_REG_MIPS_CP0_BADINSTRP;
+ if (copy_to_user(indices, , sizeof(index)))
+ return -EFAULT;
+ ++indices;
+ }
for (i = 0; i < 6; ++i) {
if (!cpu_guest_has_kscr(i + 2))
continue;
@@ -1326,6 +1342,16 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
case KVM_REG_MIPS_CP0_BADVADDR:
*v = (long)read_gc0_badvaddr();
break;
+ case KVM_REG_MIPS_CP0_BADINSTR:
+ if (!cpu_guest_has_badinstr)
+ return -EINVAL;
+ *v = read_gc0_badinstr();
+ break;
+ case KVM_REG_MIPS_CP0_BADINSTRP:
+ if (!cpu_guest_has_badinstrp)
+ return -EINVAL;
+ *v = read_gc0_badinstrp();
+ break;
case KVM_REG_MIPS_CP0_COUNT:
*v = kvm_mips_read_count(vcpu);
break;
@@ -1471,6 +1497,16 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
case KVM_REG_MIPS_CP0_BADVADDR:
write_gc0_badvaddr(v);
break;
+ case KVM_REG_MIPS_CP0_BADINSTR:
+ if (!cpu_guest_has_badinstr)
+ return -EINVAL;
+ write_gc0_badin
[PATCH 12/32] KVM: MIPS: Add 64BIT capability
Add a new KVM_CAP_MIPS_64BIT capability to indicate that 64-bit MIPS
guests are available and supported. In this case it should still be
possible to run 32-bit guest code. If not available it won't be possible
to run 64-bit guest code and the instructions may not be available, or
the kernel may not support full context switching of 64-bit registers.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 25 +
include/uapi/linux/kvm.h | 1 +
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index bd54d7a30e37..cfe9f8b04b5e 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -4179,3 +4179,28 @@ may be incompatible with the MIPS VZ ASE.
1: The MIPS VZ ASE is in use, providing full hardware assisted
virtualization, including standard guest virtual memory segments.
+
+8.4 KVM_CAP_MIPS_64BIT
+
+Architectures: mips
+
+This capability indicates the supported architecture type of the guest, i.e.
the
+supported register and address width.
+
+The values returned when this capability is checked by KVM_CHECK_EXTENSION on a
+kvm VM handle correspond roughly to the CP0_Config.AT register field, and
should
+be checked specifically against known values (see below). All other values are
+reserved.
+
+ 0: MIPS32 or microMIPS32.
+Both registers and addresses are 32-bits wide.
+It will only be possible to run 32-bit guest code.
+
+ 1: MIPS64 or microMIPS64 with access only to 32-bit compatibility segments.
+Registers are 64-bits wide, but addresses are 32-bits wide.
+64-bit guest code may run but cannot access MIPS64 memory segments.
+It will also be possible to run 32-bit guest code.
+
+ 2: MIPS64 or microMIPS64 with access to all address segments.
+Both registers and addresses are 64-bits wide.
+It will be possible to run 64-bit or 32-bit guest code.
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index f4b450d3c14b..6674b0ee1d82 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -889,6 +889,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_PPC_MMU_HASH_V3 135
#define KVM_CAP_IMMEDIATE_EXIT 136
#define KVM_CAP_MIPS_VZ 137
+#define KVM_CAP_MIPS_64BIT 138
#ifdef KVM_CAP_IRQ_ROUTING
--
git-series 0.8.10
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[PATCH 11/32] KVM: MIPS: Add VZ capability
Add a new KVM_CAP_MIPS_VZ capability, and in order to allow MIPS KVM to
support VZ without confusing old users (which expect the trap & emulate
implementation), define and start checking KVM_CREATE_VM type codes.
The codes available are:
- KVM_VM_MIPS_TE = 0
This is the current value expected from the user, and will create a
VM using trap & emulate in user mode, confined to the user mode
address space. This may in future become unavailable if the kernel is
only configured to support VZ, in which case the EINVAL error will be
returned.
- KVM_VM_MIPS_VZ = 1
This can be provided when the KVM_CAP_MIPS_VZ capability is available
to create a VM using VZ, with a fully virtualized guest virtual
address space. If VZ support is unavailable in the kernel, the EINVAL
error will be returned (although old kernels without the
KVM_CAP_MIPS_VZ capability may well succeed and create a trap &
emulate VM).
- KVM_VM_MIPS_DEFAULT = 2
This will provide the best available KVM implementation (even on
older kernels), preferring hardware assisted virtualization over trap
& emulate. The KVM_CAP_MIPS_VZ capability should always be checked
against known values to determine what type of implementation was
chosen.
This is designed to allow the desired implementation (T vs VZ) to be
potentially chosen at runtime rather than being fixed in the kernel
configuration.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 38 +++-
arch/mips/kvm/mips.c | 9 -
include/uapi/linux/kvm.h | 6 +-
3 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 069450938b79..bd54d7a30e37 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -115,12 +115,21 @@ will access the virtual machine's physical address space;
offset zero
corresponds to guest physical address zero. Use of mmap() on a VM fd
is discouraged if userspace memory allocation (KVM_CAP_USER_MEMORY) is
available.
-You most certainly want to use 0 as machine type.
+You probably want to use 0 as machine type.
In order to create user controlled virtual machines on S390, check
KVM_CAP_S390_UCONTROL and use the flag KVM_VM_S390_UCONTROL as
privileged user (CAP_SYS_ADMIN).
+To use hardware assisted virtualization on MIPS (VZ ASE) rather than
+the default trap & emulate implementation (which changes the virtual
+memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
+flag KVM_VM_MIPS_VZ.
+
+To use the best available virtualization type on MIPS, use the flag
+KVM_VM_MIPS_DEFAULT and check KVM_CAP_MIPS_VZ on the VM after creation
+to determine exactly which type was chosen.
+
4.3 KVM_GET_MSR_INDEX_LIST
@@ -4143,3 +4152,30 @@ This capability, if KVM_CHECK_EXTENSION indicates that
it is
available, means that that the kernel can support guests using the
hashed page table MMU defined in Power ISA V3.00 (as implemented in
the POWER9 processor), including in-memory segment tables.
+
+8.5 KVM_CAP_MIPS_VZ
+
+Architectures: mips
+
+This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that
+it is available, means that full hardware assisted virtualization capabilities
+of the hardware are available for use through KVM. An appropriate
+KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which
+utilises it.
+
+If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
+available, it means that the VM is using full hardware assisted virtualization
+capabilities of the hardware. This is useful to check after creating a VM with
+KVM_VM_MIPS_DEFAULT.
+
+The value returned by KVM_CHECK_EXTENSION should be compared against known
+values (see below). All other values are reserved. This is to allow for the
+possibility of other hardware assisted virtualization implementations which
+may be incompatible with the MIPS VZ ASE.
+
+ 0: The trap & emulate implementation is in use to run guest code in user
+mode. Guest virtual memory segments are rearranged to fit the guest in the
+user mode address space.
+
+ 1: The MIPS VZ ASE is in use, providing full hardware assisted
+virtualization, including standard guest virtual memory segments.
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index 2a06015930eb..cd07ea27f336 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -105,6 +105,15 @@ void kvm_arch_check_processor_compat(void *rtn)
int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
{
+ switch (type)
Re: [PATCH 11/32] KVM: MIPS: Add VZ capability
Hi Paolo, On Thu, Mar 02, 2017 at 11:59:28AM +0100, Paolo Bonzini wrote: > On 02/03/2017 10:36, James Hogan wrote: > > - KVM_VM_MIPS_DEFAULT = 2 > > > >This will provide the best available KVM implementation (even on > >older kernels), preferring hardware assisted virtualization over trap > >& emulate. The KVM_CAP_MIPS_VZ capability should always be checked > >against known values to determine what type of implementation was > >chosen. > > > > This is designed to allow the desired implementation (T vs VZ) to be > > potentially chosen at runtime rather than being fixed in the kernel > > configuration. > > Can the same kernel run on both TE and VZ? If not, I'm not sure that > KVM_VM_MIPS_DEFAULT is a good idea. It can't right now, though with relocation of the kernel now implemented in MIPS Linux for KASLR, and hopes for a more generic EVA implementation (which can require the kernel to be linked in a completely different segment) it isn't completely infeasible. Currently the two uses of this I've implemented are: 1) QEMU, which I've implemented using the kvm_type machine callback. This allows the KVM type to be specified with e.g. "-machine malta,accel=kvm,kvm-type=TE" Otherwise it defaults to using KVM_VM_MIPS_DEFAULT. When you try and load a kernel (which happens after kvm_init() has already passed the kvm type into KVM_CREATE_VM) it will check that it supports the current kernel type. 2) My kvm test application, which uses KVM_VM_MIPS_DEFAULT by default and hackily maps itself into the guest physical address space to run C code test cases. Does that justification sound reasonable? Cheers James signature.asc Description: Digital signature
[PATCH v2 28/33] KVM: MIPS/VZ: Support guest segmentation control
Add support for VZ guest CP0_SegCtl0, CP0_SegCtl1, and CP0_SegCtl2
registers, as found on P5600 and P6600 cores. These guest registers need
initialising, context switching, and exposing via the KVM ioctl API when
they are present.
They also require the GVA -> GPA translation code for handling a GVA
root exception to be updated to interpret the segmentation registers and
decode the faulting instruction enough to detect EVA memory access
instructions.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 3 +-
arch/mips/include/asm/kvm_host.h | 6 +-
arch/mips/kvm/vz.c| 242 ++-
3 files changed, 250 insertions(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 5f53bfdc0d84..45194363a160 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2078,6 +2078,9 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN| 32
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64
+ MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 5066d89f2227..b2129c031df7 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -39,6 +39,9 @@
#define KVM_REG_MIPS_CP0_XCONTEXTCONFIGMIPS_CP0_64(4, 3)
#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2)
+#define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3)
+#define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4)
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
#define KVM_REG_MIPS_CP0_HWRENAMIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
@@ -672,6 +675,9 @@ __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT,
2)
__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
__BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
__BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
+__BUILD_KVM_RW_HW(segctl0,l, MIPS_CP0_TLB_PG_MASK, 2)
+__BUILD_KVM_RW_HW(segctl1,l, MIPS_CP0_TLB_PG_MASK, 3)
+__BUILD_KVM_RW_HW(segctl2,l, MIPS_CP0_TLB_PG_MASK, 4)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR,0)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 97e7a788bf4a..f32c1ab3f724 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -412,6 +412,117 @@ static void kvm_vz_save_timer(struct kvm_vcpu *vcpu)
}
/**
+ * is_eva_access() - Find whether an instruction is an EVA memory accessor.
+ * @inst: 32-bit instruction encoding.
+ *
+ * Finds whether @inst encodes an EVA memory access instruction, which would
+ * indicate that emulation of it should access the user mode address space
+ * instead of the kernel mode address space. This matters for MUSUK segments
+ * which are TLB mapped for user mode but unmapped for kernel mode.
+ *
+ * Returns:Whether @inst encodes an EVA accessor instruction.
+ */
+static bool is_eva_access(union mips_instruction inst)
+{
+ if (inst.spec3_format.opcode != spec3_op)
+ return false;
+
+ switch (inst.spec3_format.func) {
+ case lwle_op:
+ case lwre_op:
+ case cachee_op:
+ case sbe_op:
+ case she_op:
+ case sce_op:
+ case swe_op:
+ case swle_op:
+ case swre_op:
+ case prefe_op:
+ case lbue_op:
+ case lhue_op:
+ case lbe_op:
+ case lhe_op:
+ case lle_op:
+ case lwe_op:
+ return true;
+ default:
+ return false;
+ }
+}
+
+/**
+ * is_eva_am_mapped() - Find whether an access mode is mapped.
+ * @vcpu: KVM VCPU state.
+ * @am:3-bit encoded access mode.
+ * @eu:Segment becomes unmapped and uncached when Status.ERL=1.
+ *
+ * Decode @am to find whether it encodes a mapped segment for the current VCPU
+ * state. Where necessary @eu and the actual instruction causing the fault are
+ * taken into account to make the decision.
+ *
+ * Returns:Whether the VCPU faulted on a TLB mapped address.
+ */
+static bool is_eva_am
[PATCH v2 29/33] KVM: MIPS/VZ: Support guest hardware page table walker
Add support for VZ guest CP0_PWBase, CP0_PWField, CP0_PWSize, and
CP0_PWCtl registers for controlling the guest hardware page table walker
(HTW) present on P5600 and P6600 cores. These guest registers need
initialising on R6, context switching, and exposing via the KVM ioctl
API when they are present.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 4 ++-
arch/mips/include/asm/kvm_host.h | 8 +++-
arch/mips/kvm/vz.c| 80 -
3 files changed, 92 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 45194363a160..b108238dc9dc 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2081,7 +2081,11 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64
MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64
MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64
+ MIPS | KVM_REG_MIPS_CP0_PWBASE | 64
+ MIPS | KVM_REG_MIPS_CP0_PWFIELD | 64
+ MIPS | KVM_REG_MIPS_CP0_PWSIZE | 64
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
+ MIPS | KVM_REG_MIPS_CP0_PWCTL| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index b2129c031df7..8d016ab3a8b9 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -42,7 +42,11 @@
#define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2)
#define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3)
#define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4)
+#define KVM_REG_MIPS_CP0_PWBASEMIPS_CP0_64(5, 5)
+#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6)
+#define KVM_REG_MIPS_CP0_PWSIZEMIPS_CP0_64(5, 7)
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6)
#define KVM_REG_MIPS_CP0_HWRENAMIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
#define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1)
@@ -678,7 +682,11 @@ __BUILD_KVM_RW_HW(pagegrain, 32,
MIPS_CP0_TLB_PG_MASK, 1)
__BUILD_KVM_RW_HW(segctl0,l, MIPS_CP0_TLB_PG_MASK, 2)
__BUILD_KVM_RW_HW(segctl1,l, MIPS_CP0_TLB_PG_MASK, 3)
__BUILD_KVM_RW_HW(segctl2,l, MIPS_CP0_TLB_PG_MASK, 4)
+__BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5)
+__BUILD_KVM_RW_HW(pwfield,l, MIPS_CP0_TLB_PG_MASK, 6)
+__BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
+__BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED,6)
__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR,0)
__BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR,1)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index f32c1ab3f724..fb12c5b4a75c 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1392,6 +1392,13 @@ static u64 kvm_vz_get_one_regs_segments[] = {
KVM_REG_MIPS_CP0_SEGCTL2,
};
+static u64 kvm_vz_get_one_regs_htw[] = {
+ KVM_REG_MIPS_CP0_PWBASE,
+ KVM_REG_MIPS_CP0_PWFIELD,
+ KVM_REG_MIPS_CP0_PWSIZE,
+ KVM_REG_MIPS_CP0_PWCTL,
+};
+
static u64 kvm_vz_get_one_regs_kscratch[] = {
KVM_REG_MIPS_CP0_KSCRATCH1,
KVM_REG_MIPS_CP0_KSCRATCH2,
@@ -1416,6 +1423,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu
*vcpu)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
if (cpu_guest_has_segments)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
+ if (cpu_guest_has_htw)
+ ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
return ret;
@@ -1461,6 +1470,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu
*vcpu, u64 __user *indices)
return -EFAULT;
indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
}
+ if (cpu_guest_has_htw) {
+ if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
+sizeof(kvm_vz_get_one_regs_htw)))
+ return -EFAULT;
+ indices += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
+ }
for (i = 0; i < 6; ++i) {
if (!cpu_guest_has_kscr(i + 2))
continue;
@@ -1564,9 +1579,29 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
[PATCH v2 24/33] KVM: MIPS: Implement VZ support
Add the main support for the MIPS Virtualization ASE (A.K.A. VZ) to MIPS
KVM. The bulk of this work is in vz.c, with various new state and
definitions elsewhere.
Enough is implemented to be able to run on a minimal VZ core. Further
patches will fill out support for guest features which are optional or
can be disabled.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Changes in v2:
- Drop KVM_VM_MIPS_DEFAULT (Paolo)
- Make various VZ handler functions static
---
Documentation/virtual/kvm/api.txt |2 +-
arch/mips/include/asm/cpu-info.h |1 +-
arch/mips/include/asm/kvm_host.h | 42 +-
arch/mips/kernel/time.c |1 +-
arch/mips/kvm/interrupt.h |5 +-
arch/mips/kvm/mips.c |5 +-
arch/mips/kvm/mmu.c | 20 +-
arch/mips/kvm/tlb.c |7 +-
arch/mips/kvm/trace.h | 15 +-
arch/mips/kvm/vz.c| 2381 ++-
10 files changed, 2479 insertions(+), 0 deletions(-)
create mode 100644 arch/mips/kvm/vz.c
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 1b8486c094b4..d2827864827f 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2075,6 +2075,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
MIPS | KVM_REG_MIPS_CP0_USERLOCAL| 64
MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
+ MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN| 32
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
@@ -2094,6 +2095,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_CONFIG4 | 32
MIPS | KVM_REG_MIPS_CP0_CONFIG5 | 32
MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32
+ MIPS | KVM_REG_MIPS_CP0_XCONTEXT | 64
MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH1| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH2| 64
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 4113796e0ef4..be3b4c25f335 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -110,6 +110,7 @@ struct cpuinfo_mips {
struct guest_info guest;
unsigned intgtoffset_mask;
unsigned intguestid_mask;
+ unsigned intguestid_cache;
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index b47571850aac..bc3f9dedaac8 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -10,6 +10,7 @@
#ifndef __MIPS_KVM_HOST_H__
#define __MIPS_KVM_HOST_H__
+#include
#include
#include
#include
@@ -73,6 +74,11 @@
#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_HALT_POLL_NS_DEFAULT 50
+#ifdef CONFIG_KVM_MIPS_VZ
+extern unsigned long GUESTID_MASK;
+extern unsigned long GUESTID_FIRST_VERSION;
+extern unsigned long GUESTID_VERSION_MASK;
+#endif
/*
@@ -167,6 +173,8 @@ struct kvm_arch_memory_slot {
struct kvm_arch {
/* Guest physical mm */
struct mm_struct gpa_mm;
+ /* Mask of CPUs needing GPA ASID flush */
+ cpumask_t asid_flush_mask;
};
#define N_MIPS_COPROC_REGS 32
@@ -224,6 +232,11 @@ struct mips_coproc {
#define MIPS_CP0_CONFIG4_SEL 4
#define MIPS_CP0_CONFIG5_SEL 5
+#define MIPS_CP0_GUESTCTL2 10
+#define MIPS_CP0_GUESTCTL2_SEL 5
+#define MIPS_CP0_GTOFFSET 12
+#define MIPS_CP0_GTOFFSET_SEL 7
+
/* Resume Flags */
#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
@@ -356,7 +369,20 @@ struct kvm_vcpu_arch {
/* Cache some mmu pages needed inside spinlock regions */
struct kvm_mmu_memory_cache mmu_page_cache;
+#ifdef CONFIG_KVM_MIPS_VZ
+ /* vcpu's vzguestid is different on each host cpu in an smp system */
+ u32 vzguestid[NR_CPUS];
+
+ /* wired guest TLB entries */
+ struct kvm_mips_tlb *wired_tlb;
+ unsigned int wired_tlb_limit;
+ unsigned int wired_tlb_used;
+#endif
+
+ /* Last CPU the VCPU state was loaded on */
int last_sched_cpu;
+ /* Last CPU the VCPU actually executed guest code on */
+ int last_exec_cpu;
/* WAIT executed */
int wait;
@@ -660,6 +686,7 @@ __BUILD_KVM_RW_HW(config4,32, MIPS_CP0_CONFIG,
4)
__BUILD_KVM_RW_HW(config5,32, MIPS_CP0_CONFIG, 5)
[PATCH v2 13/33] KVM: MIPS: Add 64BIT capability
Add a new KVM_CAP_MIPS_64BIT capability to indicate that 64-bit MIPS
guests are available and supported. In this case it should still be
possible to run 32-bit guest code. If not available it won't be possible
to run 64-bit guest code and the instructions may not be available, or
the kernel may not support full context switching of 64-bit registers.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Changes in v2:
- Fix section number in API documentation, which was accidentally left
unchanged after a rebase on the KVM changes for v4.11.
---
Documentation/virtual/kvm/api.txt | 25 +
include/uapi/linux/kvm.h | 1 +
2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 4b5fa2571efa..1b8486c094b4 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -4192,3 +4192,28 @@ to KVM_CREATE_VM to create a VM which utilises it.
If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
available, it means that the VM is using trap & emulate.
+
+8.7 KVM_CAP_MIPS_64BIT
+
+Architectures: mips
+
+This capability indicates the supported architecture type of the guest, i.e.
the
+supported register and address width.
+
+The values returned when this capability is checked by KVM_CHECK_EXTENSION on a
+kvm VM handle correspond roughly to the CP0_Config.AT register field, and
should
+be checked specifically against known values (see below). All other values are
+reserved.
+
+ 0: MIPS32 or microMIPS32.
+Both registers and addresses are 32-bits wide.
+It will only be possible to run 32-bit guest code.
+
+ 1: MIPS64 or microMIPS64 with access only to 32-bit compatibility segments.
+Registers are 64-bits wide, but addresses are 32-bits wide.
+64-bit guest code may run but cannot access MIPS64 memory segments.
+It will also be possible to run 32-bit guest code.
+
+ 2: MIPS64 or microMIPS64 with access to all address segments.
+Both registers and addresses are 64-bits wide.
+It will be possible to run 64-bit or 32-bit guest code.
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 58ddedce4235..1e1a6c728a18 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -889,6 +889,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_IMMEDIATE_EXIT 136
#define KVM_CAP_MIPS_VZ 137
#define KVM_CAP_MIPS_TE 138
+#define KVM_CAP_MIPS_64BIT 139
#ifdef KVM_CAP_IRQ_ROUTING
--
git-series 0.8.10
--
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[PATCH v2 26/33] KVM: MIPS/VZ: Support guest CP0_BadInstr[P]
Add support for VZ guest CP0_BadInstr and CP0_BadInstrP registers, as
found on most VZ capable cores. These guest registers need context
switching, and exposing via the KVM ioctl API when they are present.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 2 +-
arch/mips/include/asm/kvm_host.h | 4 +++-
arch/mips/kvm/vz.c| 46 -
3 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index d2827864827f..5ef4fa1de7d4 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2079,6 +2079,8 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
+ MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32
+ MIPS | KVM_REG_MIPS_CP0_BADINSTRP| 32
MIPS | KVM_REG_MIPS_CP0_COUNT| 32
MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index bc3f9dedaac8..3a9ca3326315 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -40,6 +40,8 @@
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
#define KVM_REG_MIPS_CP0_HWRENAMIPS_CP0_32(7, 0)
#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1)
+#define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2)
#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
@@ -669,6 +671,8 @@ __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK,
1)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR,0)
+__BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR,1)
+__BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR,2)
__BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT,0)
__BUILD_KVM_RW_HW(entryhi,l, MIPS_CP0_TLB_HI, 0)
__BUILD_KVM_RW_HW(compare,32, MIPS_CP0_COMPARE, 0)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index cfed234be1e3..ec909fcd08ce 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1221,6 +1221,10 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu
*vcpu)
ret = ARRAY_SIZE(kvm_vz_get_one_regs);
if (cpu_guest_has_userlocal)
++ret;
+ if (cpu_guest_has_badinstr)
+ ++ret;
+ if (cpu_guest_has_badinstrp)
+ ++ret;
ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
return ret;
@@ -1242,6 +1246,18 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu
*vcpu, u64 __user *indices)
return -EFAULT;
++indices;
}
+ if (cpu_guest_has_badinstr) {
+ index = KVM_REG_MIPS_CP0_BADINSTR;
+ if (copy_to_user(indices, , sizeof(index)))
+ return -EFAULT;
+ ++indices;
+ }
+ if (cpu_guest_has_badinstrp) {
+ index = KVM_REG_MIPS_CP0_BADINSTRP;
+ if (copy_to_user(indices, , sizeof(index)))
+ return -EFAULT;
+ ++indices;
+ }
for (i = 0; i < 6; ++i) {
if (!cpu_guest_has_kscr(i + 2))
continue;
@@ -1327,6 +1343,16 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
case KVM_REG_MIPS_CP0_BADVADDR:
*v = (long)read_gc0_badvaddr();
break;
+ case KVM_REG_MIPS_CP0_BADINSTR:
+ if (!cpu_guest_has_badinstr)
+ return -EINVAL;
+ *v = read_gc0_badinstr();
+ break;
+ case KVM_REG_MIPS_CP0_BADINSTRP:
+ if (!cpu_guest_has_badinstrp)
+ return -EINVAL;
+ *v = read_gc0_badinstrp();
+ break;
case KVM_REG_MIPS_CP0_COUNT:
*v = kvm_mips_read_count(vcpu);
break;
@@ -1472,6 +1498,16 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
case KVM_REG_MIPS_CP0_BADVADDR:
write_gc0_badvaddr(v);
break;
+ case KVM_REG_MIPS_CP0_BADINSTR:
+ if (!cpu_guest_has_badinstr)
+ return -EINVAL;
+ write_gc0_badin
[PATCH v2 27/33] KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig
Add support for VZ guest CP0_ContextConfig and CP0_XContextConfig
(MIPS64 only) registers, as found on P5600 and P6600 cores. These guest
registers need initialising, context switching, and exposing via the KVM
ioctl API when they are present.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 2 +-
arch/mips/include/asm/kvm_host.h | 4 ++-
arch/mips/kvm/vz.c| 62 ++--
3 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 5ef4fa1de7d4..5f53bfdc0d84 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2073,7 +2073,9 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64
MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64
MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
+ MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32
MIPS | KVM_REG_MIPS_CP0_USERLOCAL| 64
+ MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN| 32
MIPS | KVM_REG_MIPS_CP0_WIRED| 32
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 3a9ca3326315..5066d89f2227 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -34,7 +34,9 @@
#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
+#define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1)
#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
+#define KVM_REG_MIPS_CP0_XCONTEXTCONFIGMIPS_CP0_64(4, 3)
#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
@@ -665,7 +667,9 @@ __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX,
0)
__BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0)
__BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0)
__BUILD_KVM_RW_HW(context,l, MIPS_CP0_TLB_CONTEXT, 0)
+__BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1)
__BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2)
+__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
__BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
__BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED,0)
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index ec909fcd08ce..97e7a788bf4a 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -131,7 +131,7 @@ static inline unsigned int
kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
* Config: M, [MT]
* Config1:M, [MMUSize-1, C2, MD, PC, WR, CA], FP
* Config2:M
- * Config3:M, MSAP, [BPG], ULRI, [DSP2P, DSPP, CTXTC, ITL, LPA, VEIC,
+ * Config3:M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC,
* VInt, SP, CDMM, MT, SM, TL]
* Config4:M, [VTLBSizeExt, MMUSizeExt]
* Config5:[MRP]
@@ -161,7 +161,7 @@ static inline unsigned int
kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu)
static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu)
{
unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M |
- MIPS_CONF3_ULRI;
+ MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC;
/* Permit MSA to be present if MSA is supported */
if (kvm_mips_guest_can_have_msa(>arch))
@@ -1205,6 +1205,13 @@ static u64 kvm_vz_get_one_regs[] = {
KVM_REG_MIPS_COUNT_HZ,
};
+static u64 kvm_vz_get_one_regs_contextconfig[] = {
+ KVM_REG_MIPS_CP0_CONTEXTCONFIG,
+#ifdef CONFIG_64BIT
+ KVM_REG_MIPS_CP0_XCONTEXTCONFIG,
+#endif
+};
+
static u64 kvm_vz_get_one_regs_kscratch[] = {
KVM_REG_MIPS_CP0_KSCRATCH1,
KVM_REG_MIPS_CP0_KSCRATCH2,
@@ -1225,6 +1232,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu
*vcpu)
++ret;
if (cpu_guest_has_badinstrp)
++ret;
+ if (cpu_guest_has_contextconfig)
+ ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
return ret;
@@ -1258,6 +1267,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu
*vcpu, u64 __user *indices)
return -EFAULT;
++indices;
}
+ if (cpu_guest_has_contextconfig) {
+ if (copy_to_user(indices, kvm_vz_get_one_regs_contextconf
[PATCH v2 31/33] KVM: MIPS/VZ: Emulate MAARs when necessary
Add emulation of Memory Accessibility Attribute Registers (MAARs) when
necessary. We can't actually do anything with whatever the guest
provides, but it may not be possible to clear Guest.Config5.MRP so we
have to emulate at least a pair of MAARs.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/virtual/kvm/api.txt | 5 +-
arch/mips/include/asm/kvm_host.h | 5 +-
arch/mips/include/uapi/asm/kvm.h | 20 +-
arch/mips/kvm/trace.h | 2 +-
arch/mips/kvm/vz.c| 110 ++-
5 files changed, 137 insertions(+), 5 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index b108238dc9dc..e601c8f01fd9 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2114,6 +2114,7 @@ registers, find a list below:
MIPS | KVM_REG_MIPS_CP0_KSCRATCH4| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH5| 64
MIPS | KVM_REG_MIPS_CP0_KSCRATCH6| 64
+ MIPS | KVM_REG_MIPS_CP0_MAAR(0..63) | 64
MIPS | KVM_REG_MIPS_COUNT_CTL| 64
MIPS | KVM_REG_MIPS_COUNT_RESUME | 64
MIPS | KVM_REG_MIPS_COUNT_HZ | 64
@@ -2180,6 +2181,10 @@ hardware, host kernel, guest, and whether XPA is present
in the guest, i.e.
with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and
the PFNX field starting at bit 30.
+MIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit
+patterns:
+ 0x7030 0001 01
+
MIPS KVM control registers (see above) have the following id bit patterns:
0x7030 0002
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 8d016ab3a8b9..a662a80152b1 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -67,6 +67,7 @@
#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2)
#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
@@ -388,6 +389,9 @@ struct kvm_vcpu_arch {
struct kvm_mips_tlb *wired_tlb;
unsigned int wired_tlb_limit;
unsigned int wired_tlb_used;
+
+ /* emulated guest MAAR registers */
+ unsigned long maar[6];
#endif
/* Last CPU the VCPU state was loaded on */
@@ -708,6 +712,7 @@ __BUILD_KVM_RW_HW(config4,32, MIPS_CP0_CONFIG,
4)
__BUILD_KVM_RW_HW(config5,32, MIPS_CP0_CONFIG, 5)
__BUILD_KVM_RW_HW(config6,32, MIPS_CP0_CONFIG, 6)
__BUILD_KVM_RW_HW(config7,32, MIPS_CP0_CONFIG, 7)
+__BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2)
__BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0)
__BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0)
__BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2)
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index a8a0199bf760..3107095d7f0a 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -54,9 +54,14 @@ struct kvm_fpu {
* Register set = 0: GP registers from kvm_regs (see definitions below).
*
* Register set = 1: CP0 registers.
- * bits[15..8] - Must be zero.
- * bits[7..3] - Register 'rd' index.
- * bits[2..0] - Register 'sel' index.
+ * bits[15..8] - COP0 register set.
+ *
+ * COP0 register set = 0: Main CP0 registers.
+ * bits[7..3] - Register 'rd' index.
+ * bits[2..0] - Register 'sel' index.
+ *
+ * COP0 register set = 1: MAARs.
+ * bits[7..0] - MAAR index.
*
* Register set = 2: KVM specific registers (see definitions below).
*
@@ -115,6 +120,15 @@ struct kvm_fpu {
/*
+ * KVM_REG_MIPS_CP0 - Coprocessor 0 registers.
+ */
+
+#define KVM_REG_MIPS_MAAR (KVM_REG_MIPS_CP0 | (1 << 8))
+#define KVM_REG_MIPS_CP0_MAAR(n) (KVM_REG_MIPS_MAAR | \
+KVM_REG_SIZE_U64 | (n))
+
+
+/*
* KVM_REG_MIPS_KVM - KVM specific control registers.
*/
diff --git a/arch/mips/kvm/trace.h b/arch/mips/kvm/trace.h
index d80d37a1b82e..affde8a2c584 100644
--- a/arch/mips/kvm/trace.h
+++ b/arch/mips/kvm/trace.h
@@ -176,6 +176,8 @@ TRACE_EVENT(kvm_exit,
{ KVM_TRACE_COP0(16, 4),"Config4" },\
{ KVM_TRACE_COP0(16, 5),"Config5" },\
{ KVM_TRACE_COP0(16, 7),
[PATCH v2 7/33] KVM: MIPS: Implement HYPCALL emulation
Emulate the HYPCALL instruction added in the VZ ASE and used by the MIPS
paravirtualised guest support that is already merged. The new hypcall.c
handles arguments and the return value. No actual hypercalls are yet
supported, but this still allows us to safely step over hypercalls and
set an error code in the return value for forward compatibility.
Non-zero HYPCALL codes are not handled.
We also document the hypercall ABI which asm/kvm_para.h uses.
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com>
Cc: David Daney <david.da...@cavium.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Changes in v2:
- Patch 1 of hypercall series incorporated into VZ series
---
Documentation/virtual/kvm/hypercalls.txt | 5 ++-
arch/mips/include/asm/kvm_host.h | 7 +++-
arch/mips/include/uapi/asm/inst.h| 2 +-
arch/mips/kvm/Makefile | 1 +-
arch/mips/kvm/emulate.c | 3 +-
arch/mips/kvm/hypcall.c | 53 +-
arch/mips/kvm/trap_emul.c| 4 ++-
7 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/kvm/hypcall.c
diff --git a/Documentation/virtual/kvm/hypercalls.txt
b/Documentation/virtual/kvm/hypercalls.txt
index feaaa634f154..a890529c63ed 100644
--- a/Documentation/virtual/kvm/hypercalls.txt
+++ b/Documentation/virtual/kvm/hypercalls.txt
@@ -28,6 +28,11 @@ S390:
property inside the device tree's /hypervisor node.
For more information refer to Documentation/virtual/kvm/ppc-pv.txt
+MIPS:
+ KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall
+ number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
+ the return value is placed in $2 (v0).
+
KVM Hypercalls Documentation
===
The template for each hypercall is:
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 05e785fc061d..0d308d4f2429 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -229,6 +229,7 @@ enum emulation_result {
EMULATE_WAIT, /* WAIT instruction */
EMULATE_PRIV_FAIL,
EMULATE_EXCEPT, /* A guest exception has been generated */
+ EMULATE_HYPERCALL, /* HYPCALL instruction */
};
#define mips3_paddr_to_tlbpfn(x) \
@@ -832,6 +833,12 @@ unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu
*vcpu);
unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
+/* Hypercalls (hypcall.c) */
+
+enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
+ union mips_instruction inst);
+int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
+
/* Dynamic binary translation */
extern int kvm_mips_trans_cache_index(union mips_instruction inst,
u32 *opc, struct kvm_vcpu *vcpu);
diff --git a/arch/mips/include/uapi/asm/inst.h
b/arch/mips/include/uapi/asm/inst.h
index 77429d1622b3..b5e46ae872d3 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -179,7 +179,7 @@ enum cop0_coi_func {
tlbr_op = 0x01, tlbwi_op = 0x02,
tlbwr_op = 0x06, tlbp_op = 0x08,
rfe_op= 0x10, eret_op = 0x18,
- wait_op = 0x20,
+ wait_op = 0x20, hypcall_op= 0x28
};
/*
diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile
index 847429de780d..e56403c8a3f5 100644
--- a/arch/mips/kvm/Makefile
+++ b/arch/mips/kvm/Makefile
@@ -10,6 +10,7 @@ common-objs-$(CONFIG_CPU_HAS_MSA) += msa.o
kvm-objs := $(common-objs-y) mips.o emulate.o entry.o \
interrupt.o stats.o commpage.o \
dyntrans.o trap_emul.o fpu.o
+kvm-objs += hypcall.o
kvm-objs += mmu.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index d40cfaad4529..637753ea0a00 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -1143,6 +1143,9 @@ enum emulation_result kvm_mips_emulate_CP0(union
mips_instruction inst,
case wait_op:
er = kvm_mips_emul_wait(vcpu);
break;
+ case hypcall_op:
+ er = kvm_mips_emul_hypcall(vcpu, inst);
+ break;
}
} else {
rt = inst.c0r_format.rt;
diff --git a/arch/mips/kvm/hypcall.c b/arch/mips/kvm/hypcall.c
new file mode 100644
index ..83063435195f
--- /dev/null
+++ b/arch/mips/kvm/hypcall.c
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions
[PATCH v2 12/33] KVM: MIPS: Add VZ & TE capabilities
Add new KVM_CAP_MIPS_VZ and KVM_CAP_MIPS_TE capabilities, and in order to allow MIPS KVM to support VZ without confusing old users (which expect the trap & emulate implementation), define and start checking KVM_CREATE_VM type codes. The codes available are: - KVM_VM_MIPS_TE = 0 This is the current value expected from the user, and will create a VM using trap & emulate in user mode, confined to the user mode address space. This may in future become unavailable if the kernel is only configured to support VZ, in which case the EINVAL error will be returned and KVM_CAP_MIPS_TE won't be available even though KVM_CAP_MIPS_VZ is. - KVM_VM_MIPS_VZ = 1 This can be provided when the KVM_CAP_MIPS_VZ capability is available to create a VM using VZ, with a fully virtualized guest virtual address space. If VZ support is unavailable in the kernel, the EINVAL error will be returned (although old kernels without the KVM_CAP_MIPS_VZ capability may well succeed and create a trap & emulate VM). This is designed to allow the desired implementation (T vs VZ) to be potentially chosen at runtime rather than being fixed in the kernel configuration. Signed-off-by: James Hogan <james.ho...@imgtec.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: "Radim Krčmář" <rkrc...@redhat.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-m...@linux-mips.org Cc: k...@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Changes in v2: - Drop KVM_VM_MIPS_DEFAULT (Paolo) - Add KVM_CAP_MIPS_TE capability so that userland can determine whether T is available when VZ is also available. --- Documentation/virtual/kvm/api.txt | 47 +++- arch/mips/kvm/mips.c | 9 ++- include/uapi/linux/kvm.h | 6 - 3 files changed, 61 insertions(+), 1 deletion(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 3c248f772ae6..4b5fa2571efa 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -115,12 +115,17 @@ will access the virtual machine's physical address space; offset zero corresponds to guest physical address zero. Use of mmap() on a VM fd is discouraged if userspace memory allocation (KVM_CAP_USER_MEMORY) is available. -You most certainly want to use 0 as machine type. +You probably want to use 0 as machine type. In order to create user controlled virtual machines on S390, check KVM_CAP_S390_UCONTROL and use the flag KVM_VM_S390_UCONTROL as privileged user (CAP_SYS_ADMIN). +To use hardware assisted virtualization on MIPS (VZ ASE) rather than +the default trap & emulate implementation (which changes the virtual +memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the +flag KVM_VM_MIPS_VZ. + 4.3 KVM_GET_MSR_INDEX_LIST @@ -4147,3 +4152,43 @@ This capability, if KVM_CHECK_EXTENSION indicates that it is available, means that that the kernel can support guests using the hashed page table MMU defined in Power ISA V3.00 (as implemented in the POWER9 processor), including in-memory segment tables. + +8.5 KVM_CAP_MIPS_VZ + +Architectures: mips + +This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that +it is available, means that full hardware assisted virtualization capabilities +of the hardware are available for use through KVM. An appropriate +KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which +utilises it. + +If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is +available, it means that the VM is using full hardware assisted virtualization +capabilities of the hardware. This is useful to check after creating a VM with +KVM_VM_MIPS_DEFAULT. + +The value returned by KVM_CHECK_EXTENSION should be compared against known +values (see below). All other values are reserved. This is to allow for the +possibility of other hardware assisted virtualization implementations which +may be incompatible with the MIPS VZ ASE. + + 0: The trap & emulate implementation is in use to run guest code in user +mode. Guest virtual memory segments are rearranged to fit the guest in the +user mode address space. + + 1: The MIPS VZ ASE is in use, providing full hardware assisted +virtualization, including standard guest virtual memory segments. + +8.6 KVM_CAP_MIPS_TE + +Architectures: mips + +This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that +it is available, means that the trap & emulate implementation is available to +run guest code in user mode, even if KVM_CAP_MIPS_VZ indicates that hardware +assisted virtualisation is also available. KVM_VM_MIPS_TE (0) must be passed +to KVM_CREATE_VM to create a VM which utilises it. + +If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is +available, it means that the VM is using trap & emulate. diff --
[PATCH v2 0/33] KVM: MIPS: Add VZ support
This series is based on v4.11-rc2.
My hope is to take this series via the MIPS KVM tree for 4.12, possibly
with a topic branch containing the MIPS architecture changes (patches
1-6).
This series implements basic support for the MIPS Virtualization Module
(generally known as VZ) in KVM, which adds a new "guest" processor mode
with a partial guest Cop0 state and guest TLB to complement the existing
"root" (host) modes & state, allowing for far fewer traps to the
hypervisor compared to the existing Trap & Emulate implementation of KVM
for MIPS, as well as fully virtualizing the guest virtual memory space
to run unmodified kernels.
The MIPS32 and MIPS64 VZ architecture documentation can be found here:
http://wiki.prplfoundation.org/w/images/f/fd/MD00846-2B-VZMIPS32-AFP-01.06.pdf
http://wiki.prplfoundation.org/w/images/f/fe/MD00847-2B-VZMIPS64-AFP-01.06.pdf
We primarily support the ImgTec P5600, P6600, and I6400 cores so far,
including the following VZ / guest hardware features:
- MIPS32 and MIPS64, r5 (VZ requires r5 or later) and r6
- TLBs with GuestID (IMG cores) or Root ASID Dealias (Octeon III)
- Shared physical root/guest TLB (IMG cores)
- FPU / MSA
- Cop0 timer (up to 1GHz for now due to soft timer limit)
- Segmentation control (EVA)
- Hardware page table walker (HTW) both for root and guest TLB
Limitations:
- Support for Cavium Octeon III will follow shortly in a separate series
- Perf counters and watch registers not exposed to guest in this series
(the patches require some further cleanup)
- Guest microMIPS not supported yet (e.g. M5150)
- Guest XPA not supported yet (e.g. P5600)
We start with some preliminary MIPS changes in patches 1-6, including
some MAAR definition refactoring for XPA and some new guest capabilities
and accessors.
Patches 7-17 make preliminary VZ changes in KVM, including 64-bit MMIO
support, the VZ, TE and 64BIT KVM capabilities, and new implementation
callbacks used by the VZ implementation.
Patches 18-23 get into some meatier KVM changes for VZ, such as
abstracting guest register access for common code and adding VZ entry
and TLB management code.
Patches 24-25 add the bulk of the core VZ support and enable it in the
build system.
Patches 26-31 then go on to implement support for various optional
architectural features, such as segmentation control (EVA) and hardware
page table walkers (HTW). Context switching of the guest state may be
incomplete on certain cores without these patches if the features in
question can't be disabled in the guest context.
Finally patches 32-33 implement support for features that can be easily
disabled at runtime, namely the hardware guest timer (which can be
emulated in software before patch 32) and tracing of guest mode changes
using VZ's CP0_GuestCtl0.MC bit.
Changes in v2:
- Drop KVM_VM_MIPS_DEFAULT (Paolo)
- Make various VZ handler functions static
- Add KVM_CAP_MIPS_TE capability so that userland can determine whether
T is available when VZ is also available.
- Fix section number in API documentation for 64BIT capability, which
was accidentally left unchanged after a rebase on the KVM changes for
v4.11.
- Patch 1 of hypercall series incorporated into this series.
Cc: Paolo Bonzini <pbonz...@redhat.com>
Cc: "Radim Krčmář" <rkrc...@redhat.com>
Cc: Ralf Baechle <r...@linux-mips.org>
Cc: Andreas Herrmann <andreas.herrm...@caviumnetworks.com>
Cc: David Daney <david.da...@cavium.com>
Cc: Steven Rostedt <rost...@goodmis.org>
Cc: Ingo Molnar <mi...@redhat.com>
Cc: Paul Burton <paul.bur...@imgtec.com>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-m...@linux-mips.org
Cc: k...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
James Hogan (33):
MIPS: Add defs & probing of UFR
MIPS: Separate MAAR V bit into VL and VH for XPA
MIPS: Probe guest CP0_UserLocal
MIPS: Probe guest MVH
MIPS: Add some missing guest CP0 accessors & defs
MIPS: asm/tlb.h: Add UNIQUE_GUEST_ENTRYHI() macro
KVM: MIPS: Implement HYPCALL emulation
KVM: MIPS/Emulate: De-duplicate MMIO emulation
KVM: MIPS/Emulate: Implement 64-bit MMIO emulation
KVM: MIPS: Update kvm_lose_fpu() for VZ
KVM: MIPS: Extend counters & events for VZ GExcCodes
KVM: MIPS: Add VZ & TE capabilities
KVM: MIPS: Add 64BIT capability
KVM: MIPS: Init timer frequency from callback
KVM: MIPS: Add callback to check extension
KVM: MIPS: Add hardware_{enable,disable} callback
KVM: MIPS: Add guest exit exception callback
KVM: MIPS: Abstract guest CP0 register access for VZ
KVM: MIPS/Entry: Update entry code to support VZ
KVM: MIPS/TLB: Add VZ TLB management
KVM: MIPS/Emulate: Update CP0_Compare emulation for VZ
KVM: MIPS/Emulate: Drop CACHE emulation for VZ
KVM: MIPS: Update exit handler for VZ
KVM: MIPS: Implement VZ support
KVM: MIPS: Add VZ support to build system
KVM: MIPS/VZ: Support guest CP0_BadInstr[P]
KVM: MIPS/VZ: Support guest CP0_[X]Contex
Re: [PATCH 11/32] KVM: MIPS: Add VZ capability
On Thu, Mar 02, 2017 at 01:20:05PM +0100, Paolo Bonzini wrote: > On 02/03/2017 12:39, James Hogan wrote: > > It can't right now, though with relocation of the kernel now implemented > > in MIPS Linux for KASLR, and hopes for a more generic EVA implementation > > (which can require the kernel to be linked in a completely different > > segment) it isn't completely infeasible. > > What about the other way round, sticking a minimal T stub in kernel > space and running the kernel in userspace? Would it be feasible or > would it be as complex as KVM itself? You mean have a fallback in the guest kernel to keep kernel running from userspace addresses in kernel mode so it works in VZ guests and non-virtualized? Interesting idea. I think it would involve a lot of complexity. It could forgo some of the emulation of privileged instructions that KVM T does since its running in kernel mode, but memory management would be more complex, and invasive changes would be required to the kernel. - Memory privilege protection is on the granularity of segments, so with the traditional segment layout all of USeg (0x..0x7FFF) is accessible to user mode, so you'd still need to utilise ASIDs to separate the address spaces of actual user programs running in 0x..0x3FFF from the kernel code running in 0x4000..0x7FFF. - USeg is always TLB mapped. That means any kernel code could trigger TLB exceptions, which breaks existing assumptions (e.g. normally from unmapped kernel segments you can disable interrupts and then manipulate the TLB, but that isn't safe if a TLB refill exception could happen at any time and clobber the TLB registers). If in the future we manage to workaround these issues and map the kernel (for security/protection purposes), then it would be easier, but then we'll likely already have the capability to fully relocate into a different segment. > > 1) QEMU, which I've implemented using the kvm_type machine callback. > > This allows the KVM type to be specified with e.g. > > "-machine malta,accel=kvm,kvm-type=TE" > > Otherwise it defaults to using KVM_VM_MIPS_DEFAULT. > > > > When you try and load a kernel (which happens after kvm_init() has > > already passed the kvm type into KVM_CREATE_VM) it will check that it > > supports the current kernel type. > > > > 2) My kvm test application, which uses KVM_VM_MIPS_DEFAULT by default > > and hackily maps itself into the guest physical address space to run C > > code test cases. > > So this one would work for both TE and VZ because the guest is not a > Linux kernel. Yes, the test code is position independent and careful to avoid direct references to any symbols. The GPA mappings are set up the same, but the virtual addresses (PC, stack pointer etc) are set up slightly differently depending on whether the VZ capability is present. > I don't know... Instinctively I would think that it's easy to get > KVM_VM_MIPS_DEFAULT wrong and place the VZ-and-fall-back-to-TE policy in > userspace, but I can be convinced otherwise if the failure mode is good > enough. Yeh, I think I agree. It isn't really necessary to have that decision making in the kernel, and to use a particular KVM type userspace needs to be aware about it, so it can always figure out from capabilities which one to use prior to KVM_CREATE_VM. I suppose the exception is T It shouldn't assume that just because VZ is available that T isn't (even if that is the case right now). It could always just try KVM_CREATE_VM with kvm type 0 and detect the error I suppose, but capabilities are nicer. Maybe I'll redefine KVM_CAP_MIPS_VZ a bit, such that the value returned + 1 is a bitmask of supported kvm types: has T = !!( (v + 1) & BIT(KVM_VM_MIPS_TE) ) has VZ = !!( (v + 1) & BIT(KVM_VM_MIPS_VZ) ) That way old kernels which return 0 are consistent, and other implementations could be added if really necessary without confusing userland (but fingers crossed it'll never ever be necessary). > For example, what happens if you use KVM_SET_USER_MEMORY_REGION > for a kernel address in TE mode? That deals with physical addresses and user/kernel memory is distinguished by the virtual address, so the KVM mode (T vs VZ) doesn't make a difference here. Cheers James signature.asc Description: Digital signature
Re: [PATCH 11/32] KVM: MIPS: Add VZ capability
On Thu, Mar 02, 2017 at 10:34:07PM +, James Hogan wrote: > I suppose the exception is T It shouldn't assume that just because VZ > is available that T isn't (even if that is the case right now). It > could always just try KVM_CREATE_VM with kvm type 0 and detect the error > I suppose, but capabilities are nicer. > > Maybe I'll redefine KVM_CAP_MIPS_VZ a bit, such that the value returned > + 1 is a bitmask of supported kvm types: > has T = !!( (v + 1) & BIT(KVM_VM_MIPS_TE) ) > has VZ = !!( (v + 1) & BIT(KVM_VM_MIPS_VZ) ) > > That way old kernels which return 0 are consistent, and other > implementations could be added if really necessary without confusing > userland (but fingers crossed it'll never ever be necessary). Actually I think the way I had designed KVM_CAP_MIPS_VZ is fine. I had defined it as an enumeration rather than a mask because it isn't expected you'd have more than one hardware virtualisation type able to run on a particular core. Whether T is still supported is I think better exposed by a new KVM_CAP_MIPS_TE capability, indicating whether T is exposed when KVM_CAP_MIPS_VZ is also set. It would be set to 1 on new kernels whenever T is supported. For compatibility with older kernels, userland would be expected to determine whether T is present by: check(KVM_CAP_MIPS_VZ) == 0 || check(KVM_CAP_MIPS_TE) != 0 Old userland that doesn't check KVM_CAP_MIPS_TE would just hit an EINVAL from KVM_CREATE_VM if T isn't supported. Cheers James signature.asc Description: Digital signature
[PATCH] docs/features: parisc implements tracehook
Since commit 64e2a42bca12 ("parisc: Add ARCH_TRACEHOOK and regset
support") in v4.7, parisc selects HAVE_ARCH_TRACEHOOK, so update its
entry in Documentation/features from TODO to ok.
Fixes: 64e2a42bca12 ("parisc: Add ARCH_TRACEHOOK and regset support")
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Cc: "James E.J. Bottomley" <j...@parisc-linux.org>
Cc: Helge Deller <del...@gmx.de>
Cc: Ingo Molnar <mi...@kernel.org>
Cc: Jonathan Corbet <cor...@lwn.net>
Cc: linux-par...@vger.kernel.org
Cc: linux-doc@vger.kernel.org
---
Documentation/features/core/tracehook/arch-support.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/features/core/tracehook/arch-support.txt
b/Documentation/features/core/tracehook/arch-support.txt
index 5e97a89420ef..dfb638c2f842 100644
--- a/Documentation/features/core/tracehook/arch-support.txt
+++ b/Documentation/features/core/tracehook/arch-support.txt
@@ -25,7 +25,7 @@
| mn10300: | ok |
| nios2: | ok |
|openrisc: | ok |
-| parisc: | TODO |
+| parisc: | ok |
| powerpc: | ok |
|s390: | ok |
| score: | TODO |
--
2.13.2
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Re: [PATCH 03/20] asm-generic: Drop getrlimit and setrlimit syscalls from default list
Hi Yury, On Sun, Jun 04, 2017 at 02:59:52PM +0300, Yury Norov wrote: > The newer prlimit64 syscall provides all the functionality provided by > the getrlimit and setrlimit syscalls and adds the pid of target process, > so future architectures won't need to include getrlimit and setrlimit. > > Therefore drop getrlimit and setrlimit syscalls from the generic syscall > list unless __ARCH_WANT_SET_GET_RLIMIT is defined by the architecture's > unistd.h prior to including asm-generic/unistd.h, and adjust all architectures > using the generic syscall list to define it so that no in-tree architectures > are affected. > > Cc: Arnd Bergmann <a...@arndb.de> > Cc: James Hogan <james.ho...@imgtec.com> > Cc: linux-a...@vger.kernel.org > Cc: linux-snps-...@lists.infradead.org > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Cc: linux-arm-ker...@lists.infradead.org > Cc: Mark Salter <msal...@redhat.com> > Cc: Aurelien Jacquiot <a-jacqu...@ti.com> > Cc: linux-c6x-...@linux-c6x.org > Cc: Richard Kuo <r...@codeaurora.org> > Cc: linux-hexa...@vger.kernel.org > Cc: linux-me...@vger.kernel.org > Cc: Jonas Bonn <jo...@southpole.se> > Cc: li...@lists.openrisc.net > Cc: Chen Liqin <liqin.li...@gmail.com> > Cc: Lennox Wu <lennox...@gmail.com> > Cc: Chris Metcalf <cmetc...@mellanox.com> > Cc: Guan Xuetao <g...@mprc.pku.edu.cn> > Cc: Ley Foon Tan <lf...@altera.com> > Cc: nios2-...@lists.rocketboards.org > Cc: Yoshinori Sato <ys...@users.sourceforge.jp> > Cc: uclinux-h8-de...@lists.sourceforge.jp > Signed-off-by: Yury Norov <yno...@caviumnetworks.com> > Acked-by: Arnd Bergmann <a...@arndb.de> > Acked-by: Mark Salter <msal...@redhat.com> [c6x] > Acked-by: James Hogan <james.ho...@imgtec.com> [metag] > Acked-by: Ley Foon Tan <lf...@altera.com> [nios2] > Acked-by: Stafford Horne <sho...@gmail.com> [openrisc] > Acked-by: Will Deacon <will.dea...@arm.com> [arm64] > Acked-by: Vineet Gupta <vgu...@synopsys.com> #arch/arc bits > --- > arch/arc/include/uapi/asm/unistd.h | 1 + > arch/arm64/include/uapi/asm/unistd.h | 1 + > arch/c6x/include/uapi/asm/unistd.h | 1 + > arch/h8300/include/uapi/asm/unistd.h | 1 + > arch/hexagon/include/uapi/asm/unistd.h | 1 + > arch/metag/include/uapi/asm/unistd.h | 1 + > arch/nios2/include/uapi/asm/unistd.h | 1 + > arch/openrisc/include/uapi/asm/unistd.h | 1 + > arch/score/include/uapi/asm/unistd.h | 1 + > arch/tile/include/uapi/asm/unistd.h | 1 + > arch/unicore32/include/uapi/asm/unistd.h | 1 + > include/uapi/asm-generic/unistd.h| 5 + Don't forget to add __IGNORE_getrlimit and __IGNORE_setrlimit to scripts/checksyscalls.sh, or you'll get warnings about missing syscalls. Cheers James signature.asc Description: Digital signature
Re: [PATCH v2] MIPS: Add nonxstack=on|off kernel parameter
On Thu, Nov 30, 2017 at 09:34:15AM +, Miodrag Dinic wrote:
> Hi David,
>
> Sorry for a late response, please find answers in-lined:
>
> > > If this parameter is omitted, kernel behavior remains the same as it
> > > was before this patch is applied.
> >
> > Do other architectures have a similar hack?
> >
> > If arm{,64} and x86 don't need this, what would make MIPS so special
> > that we have to carry this around?
>
> Yes, there are similar workarounds. Just a couple lines above
> nonxstack description in the documentation there are :
> noexec [IA-64]
>
> noexec [X86]
> On X86-32 available only on PAE configured kernels.
> noexec=on: enable non-executable mappings (default)
> noexec=off: disable non-executable mappings
> ...
>
> noexec32[X86-64]
> This affects only 32-bit executables.
> noexec32=on: enable non-executable mappings (default)
> read doesn't imply executable mappings
> noexec32=off: disable non-executable mappings
> read implies executable mappings
>
> > >
> > > This functionality is convenient during debugging and is especially
> > > useful for Android development where non-exec stack is required.
> >
> > Why not just set the PT_GNU_STACK flags correctly in the first place?
>
> We do have PT_GNU_STACK flags set correctly, this feature is required to
> workaround CPU revisions which do not have RIXI support.
RIXI support can be discovered programatically from CP0_Config3.RXI
(cpu_has_rixi in asm/cpu-features.h), so I don't follow why CPUs without
RIXI would require a kernel parameter.
Cheers
James
>
> Kind regards,
> Miodrag
>
> From: David Daney [dda...@caviumnetworks.com]
> Sent: Tuesday, November 21, 2017 9:53 PM
> To: Aleksandar Markovic; linux-m...@linux-mips.org
> Cc: Miodrag Dinic; Aleksandar Markovic; Andrew Morton; DengCheng Zhu; Ding
> Tianhong; Douglas Leung; Frederic Weisbecker; Goran Ferenc; Ingo Molnar;
> James Cowgill; James Hogan; Jonathan Corbet; linux-doc@vger.kernel.org;
> linux-ker...@vger.kernel.org; Marc Zyngier; Matt Redfearn; Mimi Zohar; Paul
> Burton; Paul E. McKenney; Petar Jovanovic; Raghu Gandham; Ralf Baechle;
> Thomas Gleixner; Tom Saeger
> Subject: Re: [PATCH v2] MIPS: Add nonxstack=on|off kernel parameter
>
> On 11/21/2017 05:56 AM, Aleksandar Markovic wrote:
> > From: Miodrag Dinic <miodrag.di...@mips.com>
> >
> > Add a new kernel parameter to override the default behavior related
> > to the decision whether to set up stack as non-executable in function
> > mips_elf_read_implies_exec().
> >
> > The new parameter is used to control non executable stack and heap,
> > regardless of PT_GNU_STACK entry. This does apply to both stack and
> > heap, despite the name.
> >
> > Allowed values:
> >
> > nonxstack=on Force non-exec stack & heap
> > nonxstack=off Force executable stack & heap
> >
> > If this parameter is omitted, kernel behavior remains the same as it
> > was before this patch is applied.
>
> Do other architectures have a similar hack?
>
> If arm{,64} and x86 don't need this, what would make MIPS so special
> that we have to carry this around?
>
>
> >
> > This functionality is convenient during debugging and is especially
> > useful for Android development where non-exec stack is required.
>
> Why not just set the PT_GNU_STACK flags correctly in the first place?
>
> >
> > Signed-off-by: Miodrag Dinic <miodrag.di...@mips.com>
> > Signed-off-by: Aleksandar Markovic <aleksandar.marko...@mips.com>
> > ---
> > Documentation/admin-guide/kernel-parameters.txt | 11 +++
> > arch/mips/kernel/elf.c | 39
> > +
> > 2 files changed, 50 insertions(+)
> >
> > diff --git a/Documentation/admin-guide/kernel-parameters.txt
> > b/Documentation/admin-guide/kernel-parameters.txt
> > index b74e133..99464ee 100644
> > --- a/Documentation/admin-guide/kernel-parameters.txt
> > +++ b/Documentation/admin-guide/kernel-parameters.txt
> > @@ -2614,6 +2614,17 @@
> > noexec32=off: disable non-executable mappings
> > read implies executable mappings
> >
> > + nonxstack [MIPS]
> > + Force setting up stack and heap as non-executable
Re: [PATCH v2] MIPS: Add nonxstack=on|off kernel parameter
Hi,
On Thu, Dec 07, 2017 at 11:33:47AM +, Miodrag Dinic wrote:
> > On Wed, Dec 06, 2017 at 05:50:52PM +, Maciej W. Rozycki wrote:
> > > What problem are you trying to solve anyway? Is it not something that
> > > can be handled with the `execstack' utility?
> >
> > The commit message states that for Android "non-exec stack is required".
> > Is Android checking that then Aleksandar? If so, how?
>
> Android is using SELinux configured to disallow NX mappings by handling
> the following sepolicy rules :
> * Executable stack (execstack)
> * Executable heap (execheap)
> * File-based executable code which has been modified (execmod)
> * All other executable memory (execmem)
...
> The effect of not having some workaround like this in the kernel, would
> be to run Android only in SELinux permissive mode.
So you want to override the lack of RIXI so that SELinux sees an
RX->RW->RX transition as execmod instead of execmem (since without RIXI
its effectively RX->RWX->RX which is execmem)?
Looking at file_map_prot_check(), it does the execmem check on this
condition:
if (default_noexec &&
(prot & PROT_EXEC) && (!file || IS_PRIVATE(file_inode(file)) ||
(!shared && (prot & PROT_WRITE {
/*
* We are making executable an anonymous mapping or a
* private file mapping that will also be writable.
* This has an additional check.
*/
default_noexec is set if VM_DATA_DEFAULT_FLAGS doesn't have the exec
flag set, and that flag depends on current->personality &
READ_IMPLIES_EXEC, which depends on elf_read_implies_exec(), i.e.
mips_elf_read_implies_exec(), and that should already return 1 if RIXI
is unavailable.
I.e.
mips_elf_read_implies_exec() == 1
elf_read_implies_exec() == 1
READ_IMPLIES_EXEC will be set in current->personality
VM_DATA_DEFAULT_FLAGS will have VM_EXEC set
default_noexec will be set to 0 in selinux_init()
none of the execmem, execheap, execstack, execmod permission
checks should take place.
So whats the problem exactly? Perhaps I misinterpreted something.
Cheers
James
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[PATCH 02/13] docs: Remove metag docs
Now that arch/metag/ has been removed, remove Meta architecture specific documentation from the Documentation/ directory. Signed-off-by: James Hogan <jho...@kernel.org> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-me...@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/00-INDEX | 2 - Documentation/admin-guide/kernel-parameters.txt | 4 - Documentation/devicetree/bindings/metag/meta.txt | 30 --- Documentation/metag/00-INDEX | 4 - Documentation/metag/kernel-ABI.txt | 256 --- 5 files changed, 296 deletions(-) delete mode 100644 Documentation/devicetree/bindings/metag/meta.txt delete mode 100644 Documentation/metag/00-INDEX delete mode 100644 Documentation/metag/kernel-ABI.txt diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 7f3a0728ccf2..eae1e7193f50 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -276,8 +276,6 @@ memory-hotplug.txt - Hotpluggable memory support, how to use and current status. men-chameleon-bus.txt - info on MEN chameleon bus. -metag/ - - directory with info about Linux on Meta architecture. mic/ - Intel Many Integrated Core (MIC) architecture device driver. mips/ diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 1d1d53f85ddd..30a8d0635898 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1347,10 +1347,6 @@ If specified, z/VM IUCV HVC accepts connections from listed z/VM user IDs only. - hwthread_map= [METAG] Comma-separated list of Linux cpu id to - hardware thread id mappings. - Format: : - keep_bootcon[KNL] Do not unregister boot console at start. This is only useful for debugging when something happens in the window diff --git a/Documentation/devicetree/bindings/metag/meta.txt b/Documentation/devicetree/bindings/metag/meta.txt deleted file mode 100644 index f4457f57ab08.. diff --git a/Documentation/metag/00-INDEX b/Documentation/metag/00-INDEX deleted file mode 100644 index db11c513bd5c.. diff --git a/Documentation/metag/kernel-ABI.txt b/Documentation/metag/kernel-ABI.txt deleted file mode 100644 index 628216603198.. -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/13] docs: Remove remaining references to metag
Remove any remaining references to the Meta architecture in Documentation/, primarily from Documentation/features/. Signed-off-by: James Hogan <jho...@kernel.org> Cc: Jonathan Corbet <cor...@lwn.net> Cc: linux-me...@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/dev-tools/kmemleak.rst | 2 +- Documentation/features/core/BPF-JIT/arch-support.txt | 1 - Documentation/features/core/generic-idle-thread/arch-support.txt | 1 - Documentation/features/core/jump-labels/arch-support.txt | 1 - Documentation/features/core/tracehook/arch-support.txt | 1 - Documentation/features/debug/KASAN/arch-support.txt| 1 - Documentation/features/debug/gcov-profile-all/arch-support.txt | 1 - Documentation/features/debug/kgdb/arch-support.txt | 1 - Documentation/features/debug/kprobes-on-ftrace/arch-support.txt| 1 - Documentation/features/debug/kprobes/arch-support.txt | 1 - Documentation/features/debug/kretprobes/arch-support.txt | 1 - Documentation/features/debug/optprobes/arch-support.txt| 1 - Documentation/features/debug/stackprotector/arch-support.txt | 1 - Documentation/features/debug/uprobes/arch-support.txt | 1 - Documentation/features/debug/user-ret-profiler/arch-support.txt| 1 - Documentation/features/io/dma-api-debug/arch-support.txt | 1 - Documentation/features/io/dma-contiguous/arch-support.txt | 1 - Documentation/features/io/sg-chain/arch-support.txt| 1 - Documentation/features/lib/strncasecmp/arch-support.txt| 1 - Documentation/features/locking/cmpxchg-local/arch-support.txt | 1 - Documentation/features/locking/lockdep/arch-support.txt| 1 - Documentation/features/locking/queued-rwlocks/arch-support.txt | 1 - Documentation/features/locking/queued-spinlocks/arch-support.txt | 1 - Documentation/features/locking/rwsem-optimized/arch-support.txt| 1 - Documentation/features/perf/kprobes-event/arch-support.txt | 1 - Documentation/features/perf/perf-regs/arch-support.txt | 1 - Documentation/features/perf/perf-stackdump/arch-support.txt| 1 - Documentation/features/sched/membarrier-sync-core/arch-support.txt | 1 - Documentation/features/sched/numa-balancing/arch-support.txt | 1 - Documentation/features/seccomp/seccomp-filter/arch-support.txt | 1 - Documentation/features/time/arch-tick-broadcast/arch-support.txt | 1 - Documentation/features/time/clockevents/arch-support.txt | 1 - Documentation/features/time/context-tracking/arch-support.txt | 1 - Documentation/features/time/irq-time-acct/arch-support.txt | 1 - Documentation/features/time/modern-timekeeping/arch-support.txt| 1 - Documentation/features/time/virt-cpuacct/arch-support.txt | 1 - Documentation/features/vm/ELF-ASLR/arch-support.txt| 1 - Documentation/features/vm/PG_uncached/arch-support.txt | 1 - Documentation/features/vm/THP/arch-support.txt | 1 - Documentation/features/vm/TLB/arch-support.txt | 1 - Documentation/features/vm/huge-vmap/arch-support.txt | 1 - Documentation/features/vm/ioremap_prot/arch-support.txt| 1 - Documentation/features/vm/numa-memblock/arch-support.txt | 1 - Documentation/features/vm/pte_special/arch-support.txt | 1 - 44 files changed, 1 insertion(+), 44 deletions(-) diff --git a/Documentation/dev-tools/kmemleak.rst b/Documentation/dev-tools/kmemleak.rst index cb8862659178..e6f51260ff32 100644 --- a/Documentation/dev-tools/kmemleak.rst +++ b/Documentation/dev-tools/kmemleak.rst @@ -8,7 +8,7 @@ with the difference that the orphan objects are not freed but only reported via /sys/kernel/debug/kmemleak. A similar method is used by the Valgrind tool (``memcheck --leak-check``) to detect the memory leaks in user-space applications. -Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390, metag and tile. +Kmemleak is supported on x86, arm, powerpc, sparc, sh, microblaze, ppc, mips, s390 and tile. Usage - diff --git a/Documentation/features/core/BPF-JIT/arch-support.txt b/Documentation/features/core/BPF-JIT/arch-support.txt index 5575d2d09625..b0634ec01881 100644 --- a/Documentation/features/core/BPF-JIT/arch-support.txt +++ b/Documentation/features/core/BPF-JIT/arch-support.txt @@ -19,7 +19,6 @@ |ia64: | TODO | |m32r: | TODO | |m68k: | TODO | -| metag: | TODO | | microblaze: | TODO | |mips: | ok | | mn10300: | TODO | diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt index abb5f271a792..e2a1a385efd3 100644 --- a/Documentation/features/core/
Re: [PATCH 00/13] Remove metag architecture
On Thu, Feb 22, 2018 at 10:26:54AM +0100, Peter Zijlstra wrote: > On Wed, Feb 21, 2018 at 11:38:12PM +0000, James Hogan wrote: > > So lets call it a day and drop the Meta architecture port from the > > kernel. RIP Meta. > > So long, and thanks for all the fish! > > Nice cleanup though, most welcome :-) I thought you might like it ;-) > Acked-by: Peter Zijlstra (Intel) <pet...@infradead.org> Thanks James signature.asc Description: Digital signature
Re: [PATCH 00/13] Remove metag architecture
On Fri, Feb 23, 2018 at 11:26:58AM +0100, Arnd Bergmann wrote: > On Thu, Feb 22, 2018 at 12:38 AM, James Hogan <jho...@kernel.org> wrote: > > So lets call it a day and drop the Meta architecture port from the > > kernel. RIP Meta. > > Since I brought up the architecture removal independently, I could > pick this up into a git tree that also has the removal of some of the > other architectures. > > I see your tree is part of linux-next, so you could also just put it > in there and send a pull request at the merge window if you prefer. > > The only real reason I see for a shared git tree would be to avoid > conflicts when we touch the same Kconfig files or #ifdefs in driver, > but Meta only appears in > > config FRAME_POINTER > bool "Compile the kernel with frame pointers" > depends on DEBUG_KERNEL && \ > (CRIS || M68K || FRV || UML || \ > SUPERH || BLACKFIN || MN10300 || METAG) || \ > ARCH_WANT_FRAME_POINTERS > > and > > include/trace/events/mmflags.h:#elif defined(CONFIG_PARISC) || > defined(CONFIG_METAG) || defined(CONFIG_IA64) > > so there is little risk. I'm happy to put v2 in linux-next now (only patch 4 has changed, I just sent an updated version), and send you a pull request early next week so you can take it from there. The patches can't be directly applied with git-am anyway thanks to the -D option to make them more concise. Sound okay? Thanks James signature.asc Description: Digital signature
[GIT PULL] Remove metag architecture
Hi Arnd, On Fri, Feb 23, 2018 at 01:26:09PM +0100, Arnd Bergmann wrote: > On Fri, Feb 23, 2018 at 12:02 PM, James Hogan <jho...@kernel.org> wrote: > > I'm happy to put v2 in linux-next now (only patch 4 has changed, I just > > sent an updated version), and send you a pull request early next week so > > you can take it from there. The patches can't be directly applied with > > git-am anyway thanks to the -D option to make them more concise. > > > > Sound okay? > > Yes, sounds good, thanks! As discussed, here is a tagged branch to remove arch/metag and dependent drivers. Its basically v2 with some acks added. Cheers James The following changes since commit 91ab883eb21325ad80f3473633f794c78ac87f51: Linux 4.16-rc2 (2018-02-18 17:29:42 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git tags/metag_remove for you to fetch changes up to ef9fb83815db7d7e03da9a0904b4ef352e633922: i2c: img-scb: Drop METAG dependency (2018-02-26 14:58:09 +) Remove metag architecture These patches remove the metag architecture and tightly dependent drivers from the kernel. With the 4.16 kernel the ancient gcc 4.2.4 based metag toolchain we have been using is hitting compiler bugs, so now seems a good time to drop it altogether. -------- James Hogan (13): metag: Remove arch/metag/ docs: Remove metag docs docs: Remove remaining references to metag Drop a bunch of metag references irqchip: Remove metag irqchip drivers clocksource: Remove metag generic timer driver tty: Remove metag DA TTY and console driver MAINTAINERS/CREDITS: Drop METAG ARCHITECTURE pinctrl: Drop TZ1090 drivers gpio: Drop TZ1090 drivers watchdog: imgpdc: Drop METAG dependency media: img-ir: Drop METAG dependency i2c: img-scb: Drop METAG dependency CREDITS|5 + Documentation/00-INDEX |2 - Documentation/admin-guide/kernel-parameters.txt|4 - Documentation/dev-tools/kmemleak.rst |2 +- .../devicetree/bindings/gpio/gpio-tz1090-pdc.txt | 45 - .../devicetree/bindings/gpio/gpio-tz1090.txt | 88 - Documentation/devicetree/bindings/metag/meta.txt | 30 - .../bindings/pinctrl/img,tz1090-pdc-pinctrl.txt| 127 -- .../bindings/pinctrl/img,tz1090-pinctrl.txt| 227 --- .../features/core/BPF-JIT/arch-support.txt |1 - .../core/generic-idle-thread/arch-support.txt |1 - .../features/core/jump-labels/arch-support.txt |1 - .../features/core/tracehook/arch-support.txt |1 - .../features/debug/KASAN/arch-support.txt |1 - .../debug/gcov-profile-all/arch-support.txt|1 - Documentation/features/debug/kgdb/arch-support.txt |1 - .../debug/kprobes-on-ftrace/arch-support.txt |1 - .../features/debug/kprobes/arch-support.txt|1 - .../features/debug/kretprobes/arch-support.txt |1 - .../features/debug/optprobes/arch-support.txt |1 - .../features/debug/stackprotector/arch-support.txt |1 - .../features/debug/uprobes/arch-support.txt|1 - .../debug/user-ret-profiler/arch-support.txt |1 - .../features/io/dma-api-debug/arch-support.txt |1 - .../features/io/dma-contiguous/arch-support.txt|1 - .../features/io/sg-chain/arch-support.txt |1 - .../features/lib/strncasecmp/arch-support.txt |1 - .../locking/cmpxchg-local/arch-support.txt |1 - .../features/locking/lockdep/arch-support.txt |1 - .../locking/queued-rwlocks/arch-support.txt|1 - .../locking/queued-spinlocks/arch-support.txt |1 - .../locking/rwsem-optimized/arch-support.txt |1 - .../features/perf/kprobes-event/arch-support.txt |1 - .../features/perf/perf-regs/arch-support.txt |1 - .../features/perf/perf-stackdump/arch-support.txt |1 - .../sched/membarrier-sync-core/arch-support.txt|1 - .../features/sched/numa-balancing/arch-support.txt |1 - .../seccomp/seccomp-filter/arch-support.txt|1 - .../time/arch-tick-broadcast/arch-support.txt |1 - .../features/time/clockevents/arch-support.txt |1 - .../time/context-tracking/arch-support.txt |1 - .../features/time/irq-time-acct/arch-support.txt |1 - .../time/modern-timekeeping/arch-support.txt |1 - .../features/time/virt-cpuacct/arch-support.txt|1 - .../features/vm/ELF-ASLR/arch-support.txt |1 - .../features/vm/PG_uncached/arch-support.txt |1 - Documentation/features/vm/THP/arch-support.txt |1 - Documentation/features/vm/TLB/arch-support.txt |1 - .../fe
