On Sun, Aug 04, 2019 at 06:20:18PM +0800, Wu Hao wrote:
> This patch makes uinit callback of sub features optional. With
> this change, people don't need to prepare any empty uinit callback.
>
> Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl.c |
Hi,
On Mon, Aug 12, 2019 at 10:49:56AM +0800, Wu Hao wrote:
> This patch makes init callback of sub features optional. With
> this change, people don't need to prepare any empty init callback.
>
> Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl
gned-off-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-fme-main.c | 29 ++---
> 1 file changed, 2 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index f033f1c..bf8114d 100644
&g
> Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
> ---
> drivers/fpga/dfl-afu-main.c | 69
> +++--
> 1 file changed, 36 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
> i
Hi Greg,
can you please take the following patches. They're mostly new features
and some cleanup of the DFL internals.
They've been on the mailing list and have been reviewed.
Note: I've seen that Mauro touched Documentation/fpga/dfl.rst in linux-next
commit c220a1fae6c5d ("docs: fpga: con
-by: Alan Tull
Signed-off-by: Moritz Fischer
---
.../ABI/testing/sysfs-platform-dfl-port | 39 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-afu-error.c | 225 ++
drivers/fpga/dfl-afu-main.c | 4 +
drivers
Acked-by: Moritz Fischer
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-pci.c | 40
drivers/fpga/dfl.c | 41 +
drivers/fpga/dfl.h | 1 +
3 files changed, 82 insertions(+)
diff --git a/drivers/fpga/dfl
From: Wu Hao
This patch removes copy_to_user() code in partial reconfiguration
ioctl, as it's useless as user never needs to read the data
structure after ioctl.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Moritz Fi
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
Documentation/fpga/dfl.rst | 100 +
1 file changed, 100 insertions(+)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 2f125abd777f..be9929dd7251 100644
--- a
Acked-by: Moritz Fischer
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-pr.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 6ec0f09e5994..3c71dc3faaf5 100644
--- a/drivers/fpga/dfl-fme-pr.c
rance reporting).
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
.../ABI/testing/sysfs-platform-dfl-port | 30
drivers/fpga/dfl-afu-main.c | 140 ++
drivers/fpga/
From: Wu Hao
This patch adds id_table for each dfl private feature driver,
it allows to reuse same private feature driver to match and support
multiple dfl private features.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Moritz
From: Wu Hao
As these two functions are used by other private features. e.g.
in error reporting private feature, it requires to check port status
and reset port for error clearing.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by
From: Wu Hao
This patch adds 3 read-only sysfs interfaces for FPGA Management Engine
(FME) block for capabilities including cache_size, fabric_version and
socket_id.
Signed-off-by: Luwei Kang
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
which is only used in integrated
solution that AVX512 is always supported. This revision 2
hardware doesn't support 32bit PR.
Signed-off-by: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-main.c
Fischer
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-afu-main.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c
index bcf6e285a854..8241aced2d5d 100644
--- a/drivers/fpga
revision sysfs interface
is exposed to userspace application for this purpose too.
Signed-off-by: Ananda Ravuri
Signed-off-by: Russ Weight
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
.../ABI/testing/sysfs-platform-dfl-port | 35
: Ananda Ravuri
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
---
.../ABI/testing/sysfs-platform-dfl-fme| 75
drivers/fpga/Makefile | 2 +-
drivers/fpga/dfl-fme-error.c | 385
related userspace interfaces on PF.
Signed-off-by: Zhang Yi Z
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl-fme-main.c | 54 +
drivers/fpga/dfl.c| 107
From: Wu Hao
FME_PR_INTFC_ID is used as compat_id for fpga manager and region,
but high 64 bits and low 64 bits of the compat_id are swapped by
mistake. This patch fixes this problem by fixing register address.
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by
Hi Alan,
couple of nits inline and some comments on ordering the patches ;-)
On Mon, Oct 17, 2016 at 6:09 PM, Alan Tull wrote:
> This patch adds a minor change in the FPGA Mangager API
s/Mangager/Manager/
> to hold information that is specific to an FPGA image
> file. This change is expected
On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote:
> Add low level driver to support reprogramming FPGAs for Altera
> SoCFPGA Arria10.
>
> Signed-off-by: Alan Tull
Reviewed-by: Moritz Fischer
> ---
> v19: Added to this patchset as has been changed to use
>f
eeded. Callers can just "region->dev.groups = groups;"
after calling fpga_region_create.
Update the drivers that call fpga_region_register with the new API.
Signed-off-by: Alan Tull
Signed-off-by: Moritz Fischer
---
Documentation/fpga/fpga-region.txt | 3 +-
drivers/fpga/fpga-reg
fpga_manager *mgr);
Update the drivers that call fpga_mgr_register with the new API.
Signed-off-by: Alan Tull
[Moritz: Fixup whitespace issue]
Reported-by: Jiuyue Ma
Signed-off-by: Moritz Fischer
---
Documentation/fpga/fpga-mgr.txt | 35 ++
drivers/fpga/altera-cvp.c| 19
Hi Greg,
Here's Alan's reworked patchset changing the API
for creating and registering FPGA Managers, Bridges and
Regions following your suggestions on the API.
These go on top of Paolo and Alan's patches that you
queued up the other day.
Thanks,
Moritz
Alan Tull (4):
fpga: region: don't use
has to create an extra device for each child region to hold
drvdata.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
Signed-off-by: Moritz Fischer
---
drivers/fpga/fpga-region.c| 1 -
drivers/fpga/of-fpga-region.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
fpga_bridge_unregister(struct fpga_bridge *br);
Update the drivers that call fpga_bridge_register with the new API.
Signed-off-by: Alan Tull
Reported-by: Jiuyue Ma
Signed-off-by: Moritz Fischer
---
drivers/fpga/altera-fpga2sdram.c| 21 ++---
drivers/fpga/altera-freeze-bridge.c | 22 +++--
drivers/fpga
On Thu, May 24, 2018 at 11:33:13AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add a device tree binding for the Intel Stratix10 service layer driver
>
> Signed-off-by: Richard Gong
> Signed-off-by: Alan Tull
> Reviewed-by: Rob Herring
Ack
Hi Richard,
On Thu, May 24, 2018 at 11:33:14AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add Intel Stratix10 service layer to the device tree
>
> Signed-off-by: Richard Gong
> Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
> ---
> v2: Cha
Hi Alan,
On Mon, Oct 15, 2018 at 7:55 AM Alan Tull wrote:
>
> On Wed, Sep 26, 2018 at 11:12 AM Alan Tull wrote:
>
> Any other comments on this patchset?
Looks good to me, Sorry for the delay
Acked-by: Moritz Fischer
Cheers,
Moritz
for
> programming FPGAs.
>
> Signed-off-by: Alan Tull
> Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
> ---
> v2: Add suggested-by
> s/a FPGA/an FPGA/
> document freeing the fpga_mgr_info on success path
> minor formatting fixes and suggested edits
&
On Wed, Sep 26, 2018 at 9:12 AM Alan Tull wrote:
>
> Add devm_fpga_region_create() which is the
> managed version of fpga_region_create().
>
> Change current region drivers to use
> devm_fpga_region_create().
>
> Signed-off-by: Alan Tull
> Suggested-by: Federico Vaga
Hi Richard,
On Tue, Nov 06, 2018 at 10:52:52AM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend Intel Stratix10 service layer to support the second service layer
> client, Remote Status Update (RSU).
>
> RSU is used to provide our customers with protection against load
Hi Richard,
On Tue, Nov 06, 2018 at 10:52:48AM -0600, richard.g...@linux.intel.com wrote:
> From: Alan Tull
>
> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
>
> Signed-off-by: Alan Tull
> Signed-off-by: Richard Gong
> Reviewed-by: Rob Herring
Ack
Hi Alan,
On Thu, Feb 11, 2016 at 2:17 PM, atull wrote:
>> > > I looked into it further and now I've got a solution for this issue
>> > > that I can post soon. I can stop using the DT overlay configfs
>> > > interface and add a sysfs file for applying an overlay to an FPGA
>> > > region. The FP
Hi Alan,
On Wed, Jan 20, 2016 at 8:24 PM, wrote:
> From: Alan Tull
>
> For v15, I'm not using the FPGA Manager as the bus. I'm adding a FPGA Bus;
> the FPGA Manager and bridges go below it.
>
> I've gotten enough feedback that my proposals are Altera specific that I am
> going with that and ch
On Thu, Jan 21, 2016 at 1:17 PM, Måns Rullgård wrote:
> I don't see a patch in this email.
So it's not just me :-)
Cheers,
Moritz
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Hi Alan,
minor nits inline:
On Wed, Jan 20, 2016 at 8:24 PM, wrote:
> v15: Add altr,fpga-bus implementation
> Change compatible string "fpga-area" -> "altr,fpga-area"
Doesn't look that way down there. Or am I reading the code wrong?
> +static const struct of_device_id fpga_area_of_match
Hi Alan,
I tried getting a simple example to work with overlays, however so far
I failed getting
the child nodes to probe drivers, maybe you have an idea? The fpga
image is loaded just fine.
in dts:
fpga_bus@0 {
compatible = "altr,fpga-bus", "simple-bus";
Hi Alan,
On Thu, Jan 21, 2016 at 6:21 PM, atull wrote:
> target-path = "/amba/fpga_bus@0/devcfg@f8007000";
derp ... building in the driver helps ... all good on your side ;-)
Cheers,
Moritz
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Hi Alan,
On Thu, Jan 21, 2016 at 5:42 PM, atull wrote:
> If you want to send me a Xilinx example of usage for me to include in that
> document, that would be useful also. I think you might have sent me
> something a while ago, but I can't find it now.
Will do. I'll clean up some of my examples
Alan,
On Wed, Jan 20, 2016 at 8:24 PM, wrote:
> +static int fpga_area_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct fpga_area *area;
> + int ret;
> +
> + area = devm_kzalloc(dev,
On Fri, Jan 22, 2016 at 5:37 PM, atull wrote:
> On Fri, 22 Jan 2016, Moritz Fischer wrote:
>
>> Alan,
>>
>> On Wed, Jan 20, 2016 at 8:24 PM, wrote:
>>
>> > +static int fpga_area_probe(struct platform_device *pdev)
>> > +{
>> > +
Hi,
On Wed, Jan 27, 2016 at 9:24 PM, atull wrote:
>> I think I said this before, but you should not need simple-bus. Having
>> it is wrong if the bus requires some configuration before enumerating
>> the child nodes. The way you have it, the bridge driver could probe
>> before the FPGA manager o
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