On Mon, 8 Apr 2019 at 11:20, Vladimir Murzin wrote:
>
> On 4/7/19 7:19 PM, Ard Biesheuvel wrote:
> > Actually, the CP15 ISB is not usable here, and using the v7 ISB breaks
> > v6. Would reading back SCTLR suffice?
>
>
> I think instr_sync macro should do the trick.
>
This code should run on v7
On 4/7/19 7:19 PM, Ard Biesheuvel wrote:
> Actually, the CP15 ISB is not usable here, and using the v7 ISB breaks
> v6. Would reading back SCTLR suffice?
I think instr_sync macro should do the trick.
Cheers
Vladimir
On 07/04/2019 19:19, Ard Biesheuvel wrote:
> On Sun, 31 Mar 2019 at 10:47, Marc Zyngier wrote:
>>
>> On Sat, 30 Mar 2019 13:10:58 +,
>> Ard Biesheuvel wrote:
>>>
>>> On Sat, 30 Mar 2019 at 10:50, Marc Zyngier wrote:
Hi Ard,
On Fri, 29 Mar 2019 18:24:18 +,
Ard
On Sun, 31 Mar 2019 at 10:47, Marc Zyngier wrote:
>
> On Sat, 30 Mar 2019 13:10:58 +,
> Ard Biesheuvel wrote:
> >
> > On Sat, 30 Mar 2019 at 10:50, Marc Zyngier wrote:
> > >
> > > Hi Ard,
> > >
> > > On Fri, 29 Mar 2019 18:24:18 +,
> > > Ard Biesheuvel wrote:
> > > >
> > > > The EFI
On Sat, 30 Mar 2019 13:10:58 +,
Ard Biesheuvel wrote:
>
> On Sat, 30 Mar 2019 at 10:50, Marc Zyngier wrote:
> >
> > Hi Ard,
> >
> > On Fri, 29 Mar 2019 18:24:18 +,
> > Ard Biesheuvel wrote:
> > >
> > > The EFI stub is entered with the caches and MMU enabled by the
> > > firmware, and
On Sat, 30 Mar 2019 at 10:50, Marc Zyngier wrote:
>
> Hi Ard,
>
> On Fri, 29 Mar 2019 18:24:18 +,
> Ard Biesheuvel wrote:
> >
> > The EFI stub is entered with the caches and MMU enabled by the
> > firmware, and once the stub is ready to hand over to the decompressor,
> > we clean and disable
Hi Ard,
On Fri, 29 Mar 2019 18:24:18 +,
Ard Biesheuvel wrote:
>
> The EFI stub is entered with the caches and MMU enabled by the
> firmware, and once the stub is ready to hand over to the decompressor,
> we clean and disable the caches.
>
> The cache clean routines use CP15 barrier
The EFI stub is entered with the caches and MMU enabled by the
firmware, and once the stub is ready to hand over to the decompressor,
we clean and disable the caches.
The cache clean routines use CP15 barrier instructions, which can be
disabled via SCTLR. Normally, when using the provided cache
