On Wed, Jun 25, 2025 at 06:29:17PM +0200, Maxime MERE wrote:
> Regarding robustness and maintenance, ST ensures regular updates of its
> drivers and can fix any reported bugs. We have conducted internal tests with
> dm-crypt that demonstrate the proper functioning of these drivers for this
> type o
On Wed, Jun 25, 2025 at 06:29:26PM +0200, Maxime MERE wrote:
> Hi,
>
> On 6/25/25 08:32, Eric Biggers wrote:
> > That was the synchronous throughput. However, submitting multiple requests
> > asynchronously (which again, fscrypt doesn't actually do) barely helps.
> > Apparently the STM32 crypto e
On Wed, Jun 25, 2025 at 06:29:17PM +0200, Maxime MERE wrote:
>
>
> On 6/13/25 16:42, Eric Biggers wrote:
> > Honestly, the responses to this thread so far have made it even more clear
> > that
> > this patch is the right decision.
>
> The chaining system I previously presented is just an exampl
On Wed, Jun 25, 2025 at 08:44:45AM -0400, Theodore Ts'o wrote:
> On Tue, Jun 24, 2025 at 11:32:52PM -0700, Eric Biggers wrote:
> >
> > That was the synchronous throughput. However, submitting multiple requests
> > asynchronously (which again, fscrypt doesn't actually do) barely helps.
> > Apparen
Hi,
On 6/25/25 08:32, Eric Biggers wrote:
That was the synchronous throughput. However, submitting multiple requests
asynchronously (which again, fscrypt doesn't actually do) barely helps.
Apparently the STM32 crypto engine has only one hardware queue.
I already strongly suspected that these n
On 6/13/25 16:42, Eric Biggers wrote:
Honestly, the responses to this thread so far have made it even more clear that
this patch is the right decision.
The chaining system I previously presented is just an example intended
to demonstrate the value of hardware drivers in the context of ST pla
On Tue, Jun 24, 2025 at 11:32:52PM -0700, Eric Biggers wrote:
>
> That was the synchronous throughput. However, submitting multiple requests
> asynchronously (which again, fscrypt doesn't actually do) barely helps.
> Apparently the STM32 crypto engine has only one hardware queue.
>
> I already s
On Wed, Jun 11, 2025 at 11:25:21PM -0700, Eric Biggers wrote:
> On Thu, Jun 12, 2025 at 12:59:14AM +, Eric Biggers wrote:
> > On Thu, Jun 12, 2025 at 09:21:26AM +0900, Simon Richter wrote:
> > > Hi,
> > >
> > > On 6/12/25 05:58, Eric Biggers wrote:
> > >
> > > > But
> > > > otherwise this sty
On Fri, Jun 13, 2025 at 11:01:03AM +0200, Maxime MERE wrote:
> Hello,
>
> On 6/11/25 22:58, Eric Biggers wrote:
> > To protect users from these buggy and seemingly unhelpful drivers that I
> > have no way of testing, let's make fscrypt not use them. Unfortunately
> > there is no direct support fo
On Fri, Jun 13, 2025 at 01:23:57AM +, Eric Biggers wrote:
> On Thu, Jun 12, 2025 at 03:57:43PM +, Eric Biggers wrote:
> > On Thu, Jun 12, 2025 at 09:50:26AM +0100, Giovanni Cabiddu wrote:
> > > On Wed, Jun 11, 2025 at 11:25:21PM -0700, Eric Biggers wrote:
> > >
> > > ...
> > >
> > > > FWI
Hello,
On 6/11/25 22:58, Eric Biggers wrote:
To protect users from these buggy and seemingly unhelpful drivers that I
have no way of testing, let's make fscrypt not use them. Unfortunately
there is no direct support for doing so in the Crypto API, but we can
achieve something very close to it b
On Thu, Jun 12, 2025 at 03:57:43PM +, Eric Biggers wrote:
> On Thu, Jun 12, 2025 at 09:50:26AM +0100, Giovanni Cabiddu wrote:
> > On Wed, Jun 11, 2025 at 11:25:21PM -0700, Eric Biggers wrote:
> >
> > ...
> >
> > > FWIW, here's what happens if you try to use the Intel QAT driver with
> > > dm
On Thu, Jun 12, 2025 at 09:50:26AM +0100, Giovanni Cabiddu wrote:
> On Wed, Jun 11, 2025 at 11:25:21PM -0700, Eric Biggers wrote:
>
> ...
>
> > FWIW, here's what happens if you try to use the Intel QAT driver with
> > dm-crypt:
> > https://lore.kernel.org/r/cacsavz+mt3cfdxv0_yjh7d50trcgcrz12j3n6
On Wed, Jun 11, 2025 at 11:25:21PM -0700, Eric Biggers wrote:
...
> FWIW, here's what happens if you try to use the Intel QAT driver with
> dm-crypt:
> https://lore.kernel.org/r/cacsavz+mt3cfdxv0_yjh7d50trcgcrz12j3n6-hox2cz3+n...@mail.gmail.com/
/s/happens/happened/
... and it got fixed
https:
On Thu, Jun 12, 2025 at 12:59:14AM +, Eric Biggers wrote:
> On Thu, Jun 12, 2025 at 09:21:26AM +0900, Simon Richter wrote:
> > Hi,
> >
> > On 6/12/25 05:58, Eric Biggers wrote:
> >
> > > But
> > > otherwise this style of hardware offload is basically obsolete and has
> > > been superseded by
On Thu, Jun 12, 2025 at 09:21:26AM +0900, Simon Richter wrote:
> Hi,
>
> On 6/12/25 05:58, Eric Biggers wrote:
>
> > But
> > otherwise this style of hardware offload is basically obsolete and has
> > been superseded by hardware-accelerated crypto instructions directly on
> > the CPU as well as in
Hi,
On 6/12/25 05:58, Eric Biggers wrote:
But
otherwise this style of hardware offload is basically obsolete and has
been superseded by hardware-accelerated crypto instructions directly on
the CPU as well as inline storage encryption (UFS/eMMC).
For desktop, yes, but embedded still has quite
From: Eric Biggers
fscrypt has never properly supported the old-school Crypto API hardware
offload drivers, as it processes each request synchronously. There was
one report of someone successfully using such a driver 8 years ago. But
otherwise this style of hardware offload is basically obsolet
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