Hi Fabian
On 03/16/2015 08:59 PM, Fabian Frederick wrote:
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick f...@skynet.be
---
...
drivers/pinctrl/pinctrl-st.c| 2 +-
For this driver
Acked-by:
On Fri, Mar 6, 2015 at 3:04 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
series.
It will use new way to control the GPIO level, direction
and edge
On Mon, Mar 9, 2015 at 9:55 PM, Andreas Bofjall andr...@gazonk.org wrote:
The company is called Fintek, not Fintech. Fix it.
Signed-off-by: Andreas Bofjall andr...@gazonk.org
Reviewed-by: Alexandre Courbot acour...@nvidia.com
Patch applied.
Yours,
Linus Walleij
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2015-03-13 15:19 GMT+01:00 Andy Shevchenko andy.shevche...@gmail.com:
On Thu, Mar 12, 2015 at 11:55 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
From: Maxime Coquelin mcoquelin.st...@gmail.com
This drivers adds support to the STM32 USART controller, which is a
standard serial driver.
Hi Philipp,
2015-03-13 9:50 GMT+01:00 Philipp Zabel p.za...@pengutronix.de:
Hi Maxime,
Am Donnerstag, den 12.03.2015, 22:55 +0100 schrieb Maxime Coquelin:
From: Maxime Coquelin mcoquelin.st...@gmail.com
This adds documentation of device tree bindings for the
STM32 reset controller.
On Tue, Mar 17, 2015 at 7:32 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
2015-03-13 15:19 GMT+01:00 Andy Shevchenko andy.shevche...@gmail.com:
+static void stm32_set_termios(struct uart_port *port, struct ktermios
*termios,
+ struct ktermios *old)
+{
+
On Mon, Mar 9, 2015 at 9:55 PM, Andreas Bofjall andr...@gazonk.org wrote:
Add support for the GPIOs found on the Fintek SuperI/O chip F71869, such
as the one found on the Jetway NF96u-525 motherboard, to the f7188x gpio
driver.
Signed-off-by: Andreas Bofjall andr...@gazonk.org
Tested-by:
On Tue, Mar 17, 2015 at 5:16 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Mar 6, 2015 at 7:51 PM, Andrew Bresticker abres...@chromium.org
wrote:
On Fri, Mar 6, 2015 at 3:55 AM, Linus Walleij linus.wall...@linaro.org
wrote:
+static inline void gpio_writel(struct
On Tue, Mar 10, 2015 at 9:34 AM, Nicolas Ferre nicolas.fe...@atmel.com wrote:
Le 09/03/2015 17:14, Linus Walleij a écrit :
On Sun, Feb 8, 2015 at 7:23 PM, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
The gpiochip_lock_as_irq call can fail and return an error, while the
On Thu, Mar 12, 2015 at 11:09 AM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
As register and field widths and offsets are in the range 1..32, use
unsigned int (mostly replacing unsigned long) to store them in local
variables and for passing them around.
Move to one variable per line,
On Thu, Mar 12, 2015 at 11:09 AM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
All other loops over sh_pfc_soc_info.data_regs[] use
pinmux_data_reg.regwidth as the sentinel, which is safer as zero is
never a valid regwidth value (reg could be zero if we start using it to
store an
On Tue, Mar 10, 2015 at 12:14 PM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
The r8a7790 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven
On Tue, Mar 10, 2015 at 11:08 PM, Rafael J. Wysocki r...@rjwysocki.net wrote:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
If dev is NULL in __gpiod_get_index() and both ACPI and OF are
enabled, it will be checked twice before the code decides to give
up with DT/ACPI lookup, so avoid
On Tue, Mar 10, 2015 at 11:10 PM, Rafael J. Wysocki r...@rjwysocki.net wrote:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
In acpi_gpiochip_request_interrupts() the handle local
variable already contains the value that we want to pass
to acpi_walk_resources(), so it is better to use
On Thu, Mar 12, 2015 at 11:09 AM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.
This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs
On Thu, Mar 12, 2015 at 11:09 AM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
Currently all PFC registers lie in low 32-bit address space. Hence use
u32 instead of unsigned long to store PFC register addresses in pinctrl
tables. All calculations of virtual addresses use a phys_addr_t
On Wed, Mar 18, 2015 at 10:04 AM, Linus Walleij
linus.wall...@linaro.org wrote:
These functions do not belong in asm-generic/gpio.h since the
split into separate GPIO headers under linux/gpio/*. Move them
to linux/gpio/driver.h as is apropriate.
Acked-by: Alexandre Courbot acour...@nvidia.com
On Tuesday, March 10, 2015 11:07:36 PM Rafael J. Wysocki wrote:
Hi,
As per the subject, avoid evaluating ACPI_HANDLE() if we can as that one is
rather costly.
Linus, Alexandre, any objections to this series?
If not, would there be any problem if I took these to my tree? I'll probably
have
On Tue, Mar 10, 2015 at 12:14 PM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
The emev2 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven
On Wed, Mar 18, 2015 at 10:37 AM, Rafael J. Wysocki r...@rjwysocki.net wrote:
On Tuesday, March 10, 2015 11:07:36 PM Rafael J. Wysocki wrote:
Hi,
As per the subject, avoid evaluating ACPI_HANDLE() if we can as that one is
rather costly.
Linus, Alexandre, any objections to this series?
If
On Tue, Mar 10, 2015 at 4:08 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 20 February 2015 19:01:10 Maxime Coquelin wrote:
+/* Pull-Up/Down */
+#define NO_PULL0
+#define PULL_UP1
+#define PULL_DOWN 2
+
+/* Type */
+#define PUSH_PULL (0 2)
On Wed, Mar 18, 2015 at 2:10 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Tue, Mar 10, 2015 at 12:06 PM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.
On Tue, Mar 10, 2015 at 7:33 PM, Nishanth Menon n...@ti.com wrote:
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
Yes except I'd make use of some kind of #pinctrl-cells here just like
interrupt controller has #interrupt-cells. Then you can have the values
seprate and the controller knows what
On Wed, Mar 11, 2015 at 10:15 AM, Linus Walleij
linus.wall...@linaro.org wrote:
On Tue, Mar 10, 2015 at 6:57 PM, Ray Jui r...@broadcom.com wrote:
On 3/10/2015 3:20 AM, Linus Walleij wrote:
On Mon, Mar 9, 2015 at 9:45 PM, Ray Jui r...@broadcom.com wrote:
This adds the initial support of the
* Linus Walleij linus.wall...@linaro.org [150317 18:31]:
On Tue, Mar 10, 2015 at 7:33 PM, Nishanth Menon n...@ti.com wrote:
On 03/10/2015 12:31 PM, Tony Lindgren wrote:
Yes except I'd make use of some kind of #pinctrl-cells here just like
interrupt controller has #interrupt-cells. Then
On Mon, Mar 9, 2015 at 9:56 PM, Alexey Brodkin
alexey.brod...@synopsys.com wrote:
On Mon, 2015-03-09 at 14:59 +0100, Linus Walleij wrote:
On Tue, Mar 3, 2015 at 9:47 AM, Alexey Brodkin
alexey.brod...@synopsys.com wrote:
Interestingly what I observed in my testing that if both
Hi Chanwoo,
2015-03-13 1:09 GMT+01:00 Chanwoo Choi cw00.c...@samsung.com:
Hi Maxime,
On 03/13/2015 06:55 AM, Maxime Coquelin wrote:
From: Maxime Coquelin mcoquelin.st...@gmail.com
This adds documentation of device tree bindings for the
STM32 reset controller.
Signed-off-by: Maxime
2015-03-13 9:54 GMT+01:00 Philipp Zabel p.za...@pengutronix.de:
Am Donnerstag, den 12.03.2015, 22:55 +0100 schrieb Maxime Coquelin:
From: Maxime Coquelin mcoquelin.st...@gmail.com
The STM32 MCUs family IP can be reset by accessing some shared registers.
The specificity is that some reset
On Fri, Mar 6, 2015 at 7:51 PM, Andrew Bresticker abres...@chromium.org wrote:
On Fri, Mar 6, 2015 at 3:55 AM, Linus Walleij linus.wall...@linaro.org
wrote:
+static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
+ u32 reg)
+{
+
On Tue, 2015-03-17 at 13:20 +0100, Linus Walleij wrote:
On Thu, Mar 5, 2015 at 5:46 PM, Andy Shevchenko
andriy.shevche...@linux.intel.com wrote:
The Intel Quark SoC contains the DW GPIO on board. While fixing the build
error
the commit 1972c97db5b0 (gpio: dwapb: fix compile errors)
On Thu, Feb 26, 2015 at 10:34 AM, Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com wrote:
+For each peripheral/bank we will descibe in a u32 if a pin can be
+configured in it by putting 1 to the pin bit (1 pin)
This seems to be describing driver intrinsics in the device tree, like
how
On Mon, Mar 9, 2015 at 7:04 PM, Dmitry Torokhov
dmitry.torok...@gmail.com wrote:
Even if bus is not hot-pluggable, the devices can be unbound from the
driver via sysfs, so we should not be using __exit annotations on
remove() methods. The only exception is drivers registered with
On Mon, Mar 9, 2015 at 6:20 PM, Baruch Siach bar...@tkos.co.il wrote:
The callback function signature has changed in commit a5818a8bd0 (pinctrl:
get_group_pins() const fixes)
Fixes: a5818a8bd0 ('pinctrl: get_group_pins() const fixes')
Cc: Stephen Warren swar...@nvidia.com
Signed-off-by:
On Tue, 2015-03-17 at 14:28 +0200, Andy Shevchenko wrote:
On Tue, 2015-03-17 at 13:20 +0100, Linus Walleij wrote:
On Thu, Mar 5, 2015 at 5:46 PM, Andy Shevchenko
andriy.shevche...@linux.intel.com wrote:
The Intel Quark SoC contains the DW GPIO on board. While fixing the build
error
The Intel Quark SoC contains the DW GPIO on board. While fixing the build error
the commit 1972c97db5b0 (gpio: dwapb: fix compile errors) disables the
possibility to build the driver on X86, i.e. Intel Quark.
The patch reenables it for Intel Quark as well.
Since we have Intel Quark SoC
On Thu, Mar 5, 2015 at 5:46 PM, Andy Shevchenko
andriy.shevche...@linux.intel.com wrote:
The Intel Quark SoC contains the DW GPIO on board. While fixing the build
error
the commit 1972c97db5b0 (gpio: dwapb: fix compile errors) disables the
possibility to build the driver on X86, i.e. Intel
On Tue, Mar 17, 2015 at 5:25 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Mar 6, 2015 at 3:04 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
On Mon, Mar 9, 2015 at 8:56 PM, Baruch Siach bar...@tkos.co.il wrote:
Signed-off-by: Baruch Siach bar...@tkos.co.il
Patch applied.
Yours,
Linus Walleij
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On Mon, Mar 9, 2015 at 9:22 PM, Michael Welling mwell...@ieee.org wrote:
On Mon, Mar 09, 2015 at 04:52:26PM +0100, Linus Walleij wrote:
Whoever comes up with a cleaner sysfs or a clean device interface
will win the argument and lock the path for the other approach.
It's like a forking path
On Tue, Mar 17, 2015 at 05:39:01PM +0100, Linus Walleij wrote:
On Mon, Mar 9, 2015 at 9:22 PM, Michael Welling mwell...@ieee.org wrote:
On Mon, Mar 09, 2015 at 04:52:26PM +0100, Linus Walleij wrote:
Whoever comes up with a cleaner sysfs or a clean device interface
will win the argument
At 2015-03-17 18:25:24, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Mar 6, 2015 at 3:04 AM, Chao Xie chao@marvell.com wrote:
Signed-off-by: Chao Xie chao@marvell.com
First can some of the MMP people comment on this driver please?
(Eric/Haojian)
So this driver duplicates
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