SCIF0 on R-Car E2 does not have an SCK pin.
SCIF_CLK is the (H)SCIF baud rate generation clock pin, which is not
yet supported.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 18 --
1 file changed, 18 deletions(-)
diff --git
* Grygorii Strashko grygorii.stras...@ti.com [150825 04:44]:
On 08/21/2015 11:13 AM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150818 23:42]:
Hi,
* Grygorii Strashko grygorii.stras...@ti.com [150818 04:14]:
Hi,
This patch series contains set of trivial fixes and
Hi,
This series contains (H)SCIF-related updates for the R-Car H3 (r8a7795)
pin function controller driver:
- Fixes and updates for SCIF pindata (incl. a DTS update),
- Addition of HSCIF support.
This is against [PATCH] pinctrl: sh-pfc: Add R8A7795 PFC support and
the current state
Correct SCIF5 data pin numbers.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index
Add missing alternative data pins.
Note that this renames scif2_data to scif2_data_a, and thus requires
a DTS update.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff
- Fix SCIF0 SCK pin and mux: SCIF_CLK_B is not an alternative SCK
pin, but the alternative (H)SCIF baud rate generation clock pin,
which is not yet supported,
- Add missing SCIF0 ctrl pins.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
Cfr. pinctrl: sh-pfc: r8a7795: Extend SCIF2 pin data, which renamed
scif2_data to scif2_data_a.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 256 ++-
1 file changed, 255 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index
On 2015-08-26 05:47, Linus Walleij wrote:
On Sat, Aug 22, 2015 at 12:56 AM, Stefan Agner ste...@agner.ch wrote:
The GPIO IRQ controller is able to generate level triggered
interrupts, however, these were handled by handle_simple_irq so far
which did not take care of IRQ masking. This lead to
Hello.
On 08/25/2015 03:30 PM, Geert Uytterhoeven wrote:
Hi (Tovaritsj?) Sergei,
Tovarishch. :-)
Matsuoka-san,
From: Koji Matsuoka koji.matsuoka...@renesas.com
Add VIN0/1 pin groups to R8A7794 PFC driver.
Signed-off-by: Koji Matsuoka koji.matsuoka...@renesas.com
[Sergei: rebased,
On Mon, Aug 17, 2015 at 8:59 AM, Alexandre Courbot gnu...@gmail.com wrote:
So I'd say it makes sense to propagate errors returned by the driver's
get() hook. This might contradict some of our earlier statements about
simplifying the GPIO API, but is preferrable to having to make a
decision as
On Mon, Aug 17, 2015 at 2:35 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
Add missed description for GPIO irqchip fields in struct gpio_chip.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
Changes in v2:
- New patch.
Patch applied. Thanks for writing docs, it's very
On Tue, Aug 18, 2015 at 1:10 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
According to TRMs:
Required input line stable =
(the value of the GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) × 31,
where the value of the GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME bit field
is from 0 to 255.
On Tue, Aug 18, 2015 at 1:10 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
The bank-chip.irqdomain is uninitialized at the moment when
irq_domain_remove() is called, so remove this call.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
Obviously correct, patch applied.
On Tue, Aug 18, 2015 at 1:10 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
As per CCF documentation (clk.txt) the clk_prepare/unprepare APIs
are not allowed in atomic context. But now OMAP GPIO driver
uses them while applying debounce settings and as part
of PM runtime irqsafe
On Mon, Aug 17, 2015 at 3:03 PM, Mika Westerberg
mika.westerb...@linux.intel.com wrote:
The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc-lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the
On Mon, Aug 17, 2015 at 3:13 PM, Mika Westerberg
mika.westerb...@linux.intel.com wrote:
When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:
BUG: sleeping function called from invalid context at
On Tue, Aug 18, 2015 at 1:10 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
The access to HW registers has to be be protected in
omap_gpio_irq_handler(), as it may race with code executed on
another CPUs.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
Patch applied.
On Thu, Aug 20, 2015 at 5:49 AM, Axel Lin axel@ingics.com wrote:
2015-08-20 11:38 GMT+08:00 Hongzhou Yang hongzhou.y...@mediatek.com:
Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure
On Wed, Aug 26, 2015 at 2:32 AM, Hongzhou Yang
hongzhou.y...@mediatek.com wrote:
Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure should
be used two times.
But pinctrl_desc use global
On Thu, Aug 20, 2015 at 11:24 AM, Kuninori Morimoto
kuninori.morimoto...@renesas.com wrote:
From: Takeshi Kihara takeshi.kihara...@renesas.com
Add PFC support for the R8A7795 SoC including pin groups.
It is including EthernetAVB, DU, HDMI, MSOIF, SDHI, USB2.0, USB3.0
Signed-off-by: Takeshi
On Fri, Aug 14, 2015 at 10:38 AM, maoguang.m...@mediatek.com wrote:
From: Maoguang Meng maoguang.m...@mediatek.com
This patch implement irq_set_wake to get who is wakeup source and
setup on suspend resume.
Signed-off-by: Maoguang Meng maoguang.m...@mediatek.com
---
changes since v3:
On Wed, Aug 19, 2015 at 12:18 PM, Markus Pargmann m...@pengutronix.de wrote:
From: Markus Pargmann m...@devmp.org
This functions adds a way to initialize a GPIO without hogging it.
Signed-off-by: Markus Pargmann m...@devmp.org
---
Documentation/devicetree/bindings/gpio/gpio.txt | 29
On Sat, Aug 22, 2015 at 12:56 AM, Stefan Agner ste...@agner.ch wrote:
The GPIO IRQ controller is able to generate level triggered
interrupts, however, these were handled by handle_simple_irq so far
which did not take care of IRQ masking. This lead to nobody cared
(try booting with the irqpoll
On Wed, Aug 19, 2015 at 12:26 AM, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
From: Shinobu Uehara shinobu.uehara...@renesas.com
Add USB0/1 pin groups to R8A7794 PFC driver.
Signed-off-by: Shinobu Uehara shinobu.uehara...@renesas.com
[Sergei: rebased, renamed, added
On Sun, Aug 23, 2015 at 2:11 AM, Julia Lawall julia.law...@lip6.fr wrote:
Return a negative error code on failure.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// smpl
@@
identifier ret; expression e1,e2;
@@
(
if (\(ret
On Tue, Aug 18, 2015 at 1:10 PM, Grygorii Strashko
grygorii.stras...@ti.com wrote:
Switch OMAP GPIO driver to use platform_get_irq(), because
it is not recommened to use platform_get_resource(pdev, IORESOURCE_IRQ, ..)
for requesting IRQ resources any more, as they can be not ready yet
in case
On 26 August 2015 at 10:40, Chaotian Jing chaotian.j...@mediatek.com wrote:
On Tue, 2015-08-25 at 14:07 +0200, Ulf Hansson wrote:
On 17 August 2015 at 14:01, Chaotian Jing chaotian.j...@mediatek.com wrote:
Hi Ulf,
Thanks, please see my comment:
On Mon, 2015-08-17 at 13:31 +0200, Ulf
Hi Linus, Laurent
From: Takeshi Kihara takeshi.kihara...@renesas.com
Add PFC support for the R8A7795 SoC including pin groups.
It is including EthernetAVB, DU, HDMI, MSOIF, SDHI, USB2.0, USB3.0
Signed-off-by: Takeshi Kihara takeshi.kihara...@renesas.com
Signed-off-by: Kuninori
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
Split acpi_get_gpiod_by_index() into three smaller routines to
allow the subsequent change of the generic firmware node properties
code to be more strarightforward.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
Tested-by: Mika
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
Modify is_acpi_node() to return true for ACPI data-only subnodes as
well as for ACPI device objects and change the name of to_acpi_node()
to to_acpi_device_node() so it is clear that it covers ACPI device
objects only. Accordingly, introduce
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
Add infrastructure needed to expose data-only subnodes of ACPI
device objects introduced previously via sysfs.
Each data-only subnode is represented as a sysfs directory under
the directory corresponding to its parent object (a device or a
Hi Everyone,
This has been in the works for some time, but the official document it is
based on was not quite ready before the last week. It now is available at
http://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.pdf
The issue at hand is that we need to
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
In some cases, the information expressed via device properties is
hierarchical by nature. For example, the properties of a composite
device consisting of multiple semi-dependent components may need
to be represented in the form of a tree of
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
Move the extraction of _DSD properties from acpi_init_properties()
to a separate routine called acpi_extract_properties() to make the
subsequent changes more straightforward.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
Tested-by:
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