Re: [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates

2015-05-17 Thread Maxime Ripard
Hi Jens, On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote: Some newer sunxi SoCs (A83T, H3) don't have individual registers for AHB1, APB1 and APB2 gates anymore, but one big bus gates area where each gate can have a different parent. The current clock driver sets the same parent

Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

2015-05-17 Thread Maxime Ripard
On Fri, May 15, 2015 at 06:38:53PM +0200, Jens Kuske wrote: Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit

Re: [FYI] tux3: Core changes

2015-05-17 Thread Boaz Harrosh
On 05/14/2015 03:59 PM, Rik van Riel wrote: On 05/14/2015 04:26 AM, Daniel Phillips wrote: Hi Rik, The issue is that things like ptrace, AIO, infiniband RDMA, and other direct memory access subsystems can take a reference to page A, which Tux3 clones into a new page B when the process

Re: [PATCH] coccinelle: api: add vma_pages.cocci

2015-05-17 Thread Julia Lawall
On Sun, 17 May 2015, Dmitry Kalinkin wrote: This semantic patch replaces explicit computations of vma page count with explicit function call. Thanks! Signed-off-by: Dmitry Kalinkin dmitry.kalin...@gmail.com --- scripts/coccinelle/api/vma_pages.cocci | 66

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