On 2015년 10월 21일 03:20, Sergei Shtylyov wrote:
> Hello.
>
> On 12/18/2014 12:58 AM, Sergei Shtylyov wrote:
>
MAX3355E chip integrates a charge pump and comparators to enable a system
with
an integrated USB OTG dual-role transceiver to function as a USB OTG
dual-role
Braces not needed for single statement block
Signed-off-by: Nilesh Kokane
---
drivers/staging/lustre/lnet/klnds/socklnd/socklnd.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/staging/lustre/lnet/klnds/socklnd/socklnd.c
Kristen Accardi writes:
> On Oct 22, 2015 7:04 PM, "Neil Brown" wrote:
>>
>> Darren Hart writes:
>>
>> >
>> > Is there a good description of what is expected of a TAB member? How
> much time
>> > is involved? What makes a great TAB member?
>> >
>> > I've found:
>
This patch adds the device tree bindings for RT5033 flash LEDs.
Signed-off-by: Ingi Kim
Acked-by: Rob Herring
---
.../devicetree/bindings/leds/leds-rt5033.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644
This patch adds device driver of Richtek RT5033 PMIC.
The driver supports a current regulated output to drive
white LEDs for camera flash.
Signed-off-by: Ingi Kim
---
drivers/leds/Kconfig | 8 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-rt5033.c | 314
On Fri, 2015-10-23 at 07:43AM +0200, Mike Looijmans wrote:
> On 23-10-15 07:31, Mike Looijmans wrote:
> >On 22-10-15 18:07, Sören Brinkmann wrote:
> >>Hi Mike,
> >>
> >>On Thu, 2015-10-22 at 01:30PM +0200, Mike Looijmans wrote:
> >>>Supplying pinmux configuration for e.g. gpio pins leads to
This patch adds rt5033-led sub device to support it.
Signed-off-by: Ingi Kim
Acked-by: Lee Jones
---
drivers/mfd/rt5033.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c
index d60f916..035421c 100644
--- a/drivers/mfd/rt5033.c
+++
This patch supports flash led of RT5033 PMIC.
Changes since v3:
- Use mutex and work queue
- Split brightness set func (sync / async)
- Add flash API (flash_brightness_set)
- Move struct(rt5033_led_config_data) to local area
- Code clean
Changes since v2:
- Split MFC code from rt5033 flash
On Fri, 2015-10-23 at 07:31AM +0200, Mike Looijmans wrote:
> On 22-10-15 18:07, Sören Brinkmann wrote:
> >Hi Mike,
> >
> >On Thu, 2015-10-22 at 01:30PM +0200, Mike Looijmans wrote:
> >>Supplying pinmux configuration for e.g. gpio pins leads to deferred
> >>probes because the pinctrl device is
On 23-10-15 07:31, Mike Looijmans wrote:
On 22-10-15 18:07, Sören Brinkmann wrote:
Hi Mike,
On Thu, 2015-10-22 at 01:30PM +0200, Mike Looijmans wrote:
Supplying pinmux configuration for e.g. gpio pins leads to deferred
probes because the pinctrl device is probed much later than gpio.
Move
Hello,
On Fri, Oct 23, 2015 at 10:01:35AM +0530, Vinayak Kale wrote:
> > It looks like it'd work given that it's forcing qc->tag into
> > tf->nsect. What's the use case tho?
>
> We need to issue NCQ commands with priority bit from user space application.
>
> BTW, Sergei Shtylyov raised concern
On Thu, Oct 22, 2015 at 02:47:42PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2015-10-21 at 18:27 -0700, David Miller wrote:
> > From: Yinghai Lu
> > Date: Wed, 21 Oct 2015 11:16:53 -0700
> >
> > > otherwise we need to compare res with pbm->mem_space or pbm
> > ->mem64_space
> > > to get
Instead of enabling/disabling clocks at several locations in the driver,
Use the runtime_pm framework. This consolidates the actions for runtime PM
In the appropriate callbacks and makes the driver more readable and mantainable.
Signed-off-by: Kedareswara rao Appana
---
Changes for v7:
-
On Wed, 2015-10-21 at 13:46 +0300, Mika Westerberg wrote:
> You are saying that the original commit a445900c906092 ("i2c:
> designware: Add support for AMD I2C controller") actually never worked
> because it failed to register the clock with clkdev? In that case it is
> not even a regression ;-)
The patch reverts commit a445900c9060 (i2c: designware: Add support for
AMD I2C controller)
Since kernel starts to support APD(drivers/acpi/acpi_apd.c), there is
no need to get freq from id->driver_data for AMD0010. clkdev is supposed
to be already registered in APD.
So, revert old design and
Return function in void function is not needed.
Signed-off-by: Nilesh Kokane
---
drivers/staging/lustre/lnet/klnds/socklnd/socklnd.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/lustre/lnet/klnds/socklnd/socklnd.c
b/drivers/staging/lustre/lnet/klnds/socklnd/socklnd.c
Hi Ley,
On Thu, Oct 22, 2015 at 05:27:28PM +0800, Ley Foon Tan wrote:
> This patch adds the Altera PCIe host controller driver.
> +static void altera_pcie_fixups(struct pci_bus *bus)
> +{
> + struct pci_dev *dev;
> +
> + list_for_each_entry(dev, >devices, bus_list) {
> +
On 22-10-15 18:07, Sören Brinkmann wrote:
Hi Mike,
On Thu, 2015-10-22 at 01:30PM +0200, Mike Looijmans wrote:
Supplying pinmux configuration for e.g. gpio pins leads to deferred
probes because the pinctrl device is probed much later than gpio.
Move the init call to a much earlier stage so it
It dose not work when we want to use the usb-to-serial port based
on one usb gadget as a console. Thus this patch adds the console
initialization to support this request.
Signed-off-by: Baolin Wang
---
drivers/usb/gadget/Kconfig |6 +
drivers/usb/gadget/function/u_serial.c |
Hi Soren,
> -Original Message-
> From: Sören Brinkmann [mailto:soren.brinkm...@xilinx.com]
> Sent: Thursday, October 22, 2015 10:03 PM
> To: Appana Durga Kedareswara Rao
> Cc: Anirudha Sarangi; w...@grandegger.com; m...@pengutronix.de; Michal
> Simek; Appana Durga Kedareswara Rao;
Confirmation Batch No. GDFS-25-30-29-3-26,
Contact Person:Juan De la Silva
EMAIL: freelot...@gmail.com
TELL:+34-603-307-989
Reference Nr.XKHL-37-14-29-13),
Batch No. GDFS-25-30-29-3-26,
Serial No.PMSQ021542311,
Ticket No.11-48-19-15-14,
lucky No.4-19-26-27-30-3-8,
You have won( ONE MILLION
Previously ALC2 register is set as a volatile register, declare
it as one of ALC Coefficients register together with other non-volatile
registers will cause issue, in case wm8962 has enter suspend mode,
and cache_only flag is set, any attempt to read from ALC2 will fail.
Because the 5 status bits
Hi Soren,
> -Original Message-
> From: Sören Brinkmann [mailto:soren.brinkm...@xilinx.com]
> Sent: Friday, October 23, 2015 3:43 AM
> To: Appana Durga Kedareswara Rao
> Cc: Anirudha Sarangi; w...@grandegger.com; m...@pengutronix.de; Michal
> Simek; linux-...@vger.kernel.org;
The NAND controller on NS2 SoC is compatible with existing
BRCM IPROC NAND driver so let's enable it in NS2 DT and
NS2 SVK DT.
This patch also fixes use of node labels in ns2-svk.dts.
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
Just like other NAND controllers, the NAND READID command only works
in 8bit mode for all versions of BRCMNAND controller.
This patch forces 8bit mode for each NAND CS in brcmnand_init_cs()
before doing nand_scan_ident() to ensure that BRCMNAND controller
is in 8bit mode when NAND READID command
We enable NAND support for Broadcom NS2 SoC by reusing existing
BRCMNAND driver.
This patchset applies on-top of "arm64: Simple additions to
NS2 DT" v1 patchset and is available in ns2_nand_v3 branch of
https://github.com/Broadcom/arm64-linux.git.
The patchset is tested on NS2 SVK.
Changes
On Fri, Oct 23, 2015 at 10:00:03AM +0530, Nilesh Kokane wrote:
> Fixed- Return of an errno should typically be negative (ie: return -EAGAIN)
>
The changelog needs to describe the use visible effects of this change.
regards,
dan carpenter
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To unsubscribe from this list: send the line
We don't have fraglist support in TAP_FEATURES. This will lead
software segmentation of gro skb with frag list. Fixes by having
frag list support in TAP_FEATURES.
With this patch single session of netperf receiving were restored from
about 5Gb/s to about 12Gb/s on mlx4.
Fixes a567dd6252
The driver does not have any real architecture dependencies. To avoid
listing each architecture that might use this driver on some
FPGA-enabled platform, drop these dependencies.
Signed-off-by: Soren Brinkmann
Acked-by: Moritz Fischer
---
v2:
- rebased
---
drivers/gpio/Kconfig | 2 +-
1 file
On Thu, Oct 22, 2015 at 08:00:20PM -0700, Kristen Accardi wrote:
> On Oct 22, 2015 7:04 PM, "Neil Brown" wrote:
> >
> > Darren Hart writes:
> >
> > >
> > > Is there a good description of what is expected of a TAB member? How
> much time
> > > is involved? What makes a great TAB member?
> > >
> >
On 2015/10/17 18:48, Wang Nan wrote:
[SNIP]
event_bpf_file:
-PE_BPF_OBJECT
+PE_BPF_OBJECT event_bpf_config
{
struct parse_events_evlist *data = _data;
struct parse_events_error *error = data->error;
struct list_head *list;
ALLOC_LIST(list);
-
Fixed- Return of an errno should typically be negative (ie: return -EAGAIN)
Signed-off-by: Nilesh Kokane
---
drivers/staging/lustre/lnet/lnet/lib-move.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/lustre/lnet/lnet/lib-move.c
Hello,
So, something like the following. Just compile tested but this is
essentially partial revert of 3270476a6c0c ("workqueue: reimplement
WQ_HIGHPRI using a separate worker_pool") - resurrecting the old
WQ_HIGHPRI implementation under WQ_IMMEDIATE, so we know this works.
If for some reason,
On (10/22/15 13:21), a...@linux-foundation.org wrote:
[..]
> --
> From: Sergey Senozhatsky
> Subject: Doc/slub: document slabinfo-gnuplot.sh script
>
> Add documentation on how to use slabinfo-gnuplot.sh script.
>
> Signed-off-by: Sergey
Update the documentation about:
1. Usage of PMU_SPARE2 register.
Bootloaders on Exynos542x-based boards often use the register
PMU_SPARE2 (0x908) in the same way as on Exynos3250: as a indicator
the secondary CPU was booted on. The bootloader will set this value
to non-zero, after
J. Bruce Fields wrote:
> On Fri, Oct 16, 2015 at 02:28:10AM +, Kosuke Tatsukawa wrote:
>> Tatsukawa Kosuke wrote:
>> > J. Bruce Fields wrote:
>> >> On Thu, Oct 15, 2015 at 11:44:20AM +, Kosuke Tatsukawa wrote:
>> >>> Tatsukawa Kosuke wrote:
>> >>> > J. Bruce Fields wrote:
>> >>> >> Thanks
Caesar,
On Thu, Oct 22, 2015 at 9:54 PM, Caesar Wang wrote:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the
> default tshut polarity is high.
>
On Fri, Oct 23, 2015 at 11:23:26AM +0800, Hillf Danton wrote:
> > > > + if (cnt_hmm_entry) {
> > > > + int ret;
> > > > +
> > > > + ret = hmm_mm_fork(src_mm, dst_mm, dst_vma,
> > > > + dst_pmd, start, end);
> > >
> > > Given start,
From: Karsten Merker
The MSI Primo81 is an A31s based tablet, with 1G RAM, 16G NAND,
768x1024 IPS LCD display, mono speaker, 0.3 MP front camera, 2.0 MP
rear camera, 3500 mAh battery, gt911 touchscreen, mma8452 accelerometer
and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons
Hi everyone,
This is v4 of the simplefb regulator support series. This series adds
regulator claiming and enabling support for simplefb.
Changes since v4:
- Fixed inverted logic when testing the property name.
- Fixed regulator supply name string copy length off by 1.
- Added real world
The physical display tied to the framebuffer may have regulators
providing power to it, such as power for LCDs or interface conversion
chips.
The number of regulators in use may vary, but the regulator supply
binding can not be a list. Instead just support any named regulator
supply properties
Some boards, such as tablets, have regulators providing power to parts
of the display pipeline, like signal converters and LCD panels.
Add labels to the simplefb device nodes so that we can reference them
in the board dts files to add regulator supply properties.
Signed-off-by: Chen-Yu Tsai
---
This claims and enables regulators listed in the simple framebuffer dt
node. This is needed so that regulators powering the display pipeline
and external hardware, described in the device node and known by the
kernel code, will remain properly enabled.
Signed-off-by: Chen-Yu Tsai
Acked-by: Mark
On 2015/10/23 8:10, Alexei Starovoitov wrote:
Fix safety checks for bpf_perf_event_read():
- only non-inherited events can be added to perf_event_array map
(do this check statically at map insertion time)
- dynamically check that event is local and !pmu->count
Otherwise buggy bpf program
On 2015/10/22 20:08, Ulf Hansson wrote:
On 22 October 2015 at 11:06, Shawn Lin wrote:
This patch add runtime_suspend and runtime_resume for
sdhci-of-arasan. Currently we also power-off phy at
runtime_suspend for power-saving.
Signed-off-by: Shawn Lin
Serise-changes: 4
- remove ifdef for PM
On 2015/10/15 21:32, Taku Izumi wrote:
> Xeon E7 v3 based systems supports Address Range Mirroring
> and UEFI BIOS complied with UEFI spec 2.5 can notify which
> ranges are reliable (mirrored) via EFI memory map.
> Now Linux kernel utilize its information and allocates
> boot time memory from
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> Simplify csum_add(a, b) in case a or b is constant 0
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/include/asm/checksum.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/checksum.h
Hi Linus,
Please pull some more powerpc fixes for 4.3:
The following changes since commit abb39bc792aa8e9143e78a39ec13d7de1391f4b4:
selftests/powerpc: Fix build failure of load_unaligned_zeropad test
(2015-10-13 15:08:37 +1100)
are available in the git repository at:
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> csum_partial is often called for small fixed length packets
> for which it is suboptimal to use the generic csum_partial()
> function.
>
> For instance, in my configuration, I got:
> * One place calling it with constant len 4
> * Seven
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> r5 does contain the value to be updated, so lets use r5 all way long
> for that. It makes the code more readable.
>
> To avoid confusion, it is better to use adde instead of addc
>
> The first addition is useless. Its only purpose is
On Fri, Oct 23, 2015 at 9:31 AM, Chen-Yu Tsai wrote:
> This claims and enables regulators listed in the simple framebuffer dt
> node. This is needed so that regulators powering the display pipeline
> and external hardware, described in the device node and known by the
> kernel code, will remain
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
> The powerpc64 checksum wrapper functions adds csum_and_copy_to_user()
> which otherwise is implemented in include/net/checksum.h by using
> csum_partial() then copy_to_user()
>
> Those two wrapper fonctions are also applicable to
> > > This is a multi-stage process, first we save and replace page table
> > > entry with special HMM entry, also flushing tlb in the process. If
> > > we run into non allocated entry we either use the zero page or we
> > > allocate new page. For swaped entry we try to swap them in.
> > >
> >
> > > + if (cnt_hmm_entry) {
> > > + int ret;
> > > +
> > > + ret = hmm_mm_fork(src_mm, dst_mm, dst_vma,
> > > + dst_pmd, start, end);
> >
> > Given start, s/end/addr/, no?
>
> No, end is the right upper limit here.
>
Then in the first loop, hmm_mm_fork
On Wed, Oct 14, 2015 at 03:16:08PM +0800, Zhao Qiang wrote:
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
> index 01626be7..c9541a5 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -272,25 +272,6 @@ config TAU_AVERAGE
>
>
On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> diff --git a/arch/powerpc/sysdev/qe_lib/qe.c >
> b/arch/powerpc/sysdev/qe_lib/qe.c
> index c2518cd..3f9f596 100644
> --- a/arch/powerpc/sysdev/qe_lib/qe.c
> +++ b/arch/powerpc/sysdev/qe_lib/qe.c
> @@ -671,6 +671,21 @@ unsigned int
On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> QE and CPM have the same muram, they use the same management
> functions. Now QE support both ARM and PowerPC, it is necessary
> to move QE to "driver/soc", so move the muram management functions
> from cpm_common to qe_common for preparing to
Hi Steve,
Thanks for pointing the link, I have not seen that driver before; I was mainly
looking at driver/edac/xgene_edac.c and some other arm edac drivers. My first
attempt was to do AMD specific edac driver to log correctable L1/L2 error but
based on feedback I worked on v2 generic driver
On Wed, 2015-10-14 at 15:16 +0800, Zhao Qiang wrote:
> Use genalloc to manage CPM/QE muram instead of rheap.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v9:
> - splitted from patch 3/5, modify cpm muram management functions.
> Changes for v10:
> - modify cpm muram first, then
Nicolas Parpandet writes:
> Hello,
>
> I did some more investigations, (wireshark)
>
> The unlink of /tmp/crontab.vYPoHR/crontab is tranlated into a rename
> nfs call ? (.nfs file)
That happens if the file is still open.
>
> NFS 670 V3 READDIRPLUS Reply (Call In 731) crontab .. .
> NFS
Hi,
I am testing Linux v4.3-rc6 on a laptop with Intel 'Skylake' integrated
graphics. The integrated display works, but I noticed several warnings in the
kernel log, and a VGA monitor attached to the HDMI input via a VGA->HDMI adapter
did not work. Furthermore, the system hung for several
On Thu, Oct 22, 2015 at 04:31:44PM -0400, Chris Metcalf wrote:
> On 10/21/2015 08:39 AM, Peter Zijlstra wrote:
> >Can you *please* start a new thread with each posting?
> >
> >This is absolutely unmanageable.
>
> I've been explicitly threading the multiple patch series on purpose
> due to this
On 10/22/15 7:21 PM, Wangnan (F) wrote:
+if (attr->inherit)
+goto err;
+
Since Peter suggest it is pointless for a system-wide perf_event
has inherit bit set [1], I think it should be safe to enable
system-wide perf_event pass this check?
here we don't know whether it's system
On 2015/10/23 8:10, Alexei Starovoitov wrote:
Fix safety checks for bpf_perf_event_read():
- only non-inherited events can be added to perf_event_array map
(do this check statically at map insertion time)
- dynamically check that event is local and !pmu->count
Otherwise buggy bpf program
Add Freescale Queue Direct Memory Access(qDMA) controller support.
This module can be found on LS-1 and LS-2 SoCs.
This add the legacy mode support for qDMA.
Signed-off-by: Yuan Yao
---
arch/arm/boot/dts/ls1021a.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git
On 22-10-15, 14:40, Yunhong Jiang wrote:
> A naive question is, why it's sure a tick will happen when the tickless
> processor is in idle?
How do you get this impression? I don't think anyone has said that.
We are talking about deferrable timers, which by design are only
required if the target
Add Binding document for Freescale Queue Direct Memory Access(qDMA)
controller.
This module can be found on LS-1 and LS-2 SoCs.
Signed-off-by: Yuan Yao
---
Documentation/devicetree/bindings/dma/fsl-qdma.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Add Freescale Queue Direct Memory Access(qDMA) controller support.
This module can be found on LS-1 and LS-2 SoCs.
This add the legacy mode support for qDMA.
Signed-off-by: Yuan Yao
---
Changes since v1:
1. Separate Binding.
2. Remove dead code.
3. Add depend on for QDMA.
---
MAINTAINERS
Darren Hart writes:
>
> Is there a good description of what is expected of a TAB member? How much time
> is involved? What makes a great TAB member?
>
> I've found: http://www.linuxfoundation.org/programs/advisory-councils/tab
>
> I've read the charter and scanned some of the minutes, but I'd
On 2015/10/22 0:23, Bjorn Helgaas wrote:
> On Fri, Oct 09, 2015 at 12:23:34PM +0200, Joerg Roedel wrote:
>> From: Joerg Roedel
>>
>> The pcibios-irq and MSI both use dev->irq to store the IRQ
>> number. While the MSI code checks for that and frees the
>> pcibios-irq before overwriting dev->irq,
From: Vivien Didelot
Date: Thu, 22 Oct 2015 16:54:31 -0400
> It is preferable to have a common debugfs interface for DSA or switchdev
> instead of a driver specific one. Thus remove the mv88e6xxx debug code.
>
> Signed-off-by: Vivien Didelot
Applied, thanks.
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To unsubscribe from this list:
Thank you all for providing inputs and comments on previous versions of
this patchset.
Especially thanks to the (Doug, Rob).
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" and "sleep" pinctrl as the OTP gpio state, since we need
switch the pin to gpio state before the TSADC controller is reset.
AFAIK, the TSADC controller is reset, the tshut
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree, the
default tshut polarity is high.
If T > 80C, the OTP output the high signal.
If T < 80C, the OTP output
Add the "init" anf "sleep" pinctrl as the OTP gpio state.
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
"init" pinctrl property is defined by Doug's Patch[0].
Patch[0]:
https://patchwork.kernel.org/patch/7454311/
On Fri, Oct 23, 2015 at 6:13 AM, Bjorn Helgaas wrote:
> On Thu, Oct 22, 2015 at 05:27:27PM +0800, Ley Foon Tan wrote:
>> Signed-off-by: Ley Foon Tan
>> ---
>> include/linux/pci_ids.h | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
On Thu, 22 Oct 2015, Ian Kent wrote:
> On Wed, 2015-10-21 at 12:56 -0700, Hugh Dickins wrote:
> > On Wed, 21 Oct 2015, Ian Kent wrote:
>
> Thanks for taking the time to reply Hugh.
>
> >
> > > Hi all,
> > >
> > > I've been looking through some of the page reclaim code and at
> > >
Hi Alexandre,
Sorry for late answer.
> -Original Message-
> From: Alexandre Belloni [mailto:alexandre.bell...@free-electrons.com]
> Sent: 2015年10月15日 21:22
> To: Yang, Wenyou
> Cc: Ferre, Nicolas; Jean-Christophe Plagniol-Villard; Russell King; Stephen
> Boyd;
> Michael Turquette;
>>> +++ b/drivers/edac/cortex_arm64_edac.c
>>> @@ -0,0 +1,457 @@
>>> +/*
>>> + * Cortex ARM64 EDAC
>>> + *
>>> + * Copyright (c) 2015, Advanced Micro Devices
>>> + * Author: Brijesh Singh
>>> + *
Hi Brijesh,
Your ARM64 EDAC driver seems rather similar to the existing driver that
is linked
First part of each memory controller. I have two memory controllers on each node
Sent from my iPhone
> On Oct 22, 2015, at 18:01, Izumi, Taku wrote:
>
> Dear Tony,
>
>> -Original Message-
>> From: Luck, Tony [mailto:tony.l...@intel.com]
>> Sent: Friday, October 23, 2015 8:27 AM
>> To:
Hi Brijesh,
On 2015/10/22 22:46, Brijesh Singh wrote:
> Hi Andre,
>
> On 10/21/2015 06:52 PM, Andre Przywara wrote:
>> On 21/10/15 21:41, Brijesh Singh wrote:
>>> Add support for Cortex A57 and A53 EDAC driver.
>> Hi Brijesh,
>>
>> thanks for the quick update! Some comments below.
>>
>>>
You can not use R4K CP0_count in SMP (multicore) without core-specific
adjustment.
After first power-saving with core clock off or core down the values in
CP0_count
in different cores are absolutely different.
Until you include in system a patch like
On 2015/10/21 17:35, Borislav Petkov wrote:
> On Wed, Oct 21, 2015 at 09:55:43AM +0800, Hanjun Guo wrote:
>> So I think the meaning of those error register is the same, but the way
>> of handle it may different from SoCs, for single bit error:
>>
>> - SoC may trigger a interrupt;
>> - SoC may
Exynos SoC Device Tree bindings are spread over arm/exynos/ and
arm/samsung/ directories. There is no need for that separation and it
actually confuses. Put power domain bindings under power/ and
remaining samsung-boards.txt under arm/samsung/.
Signed-off-by: Krzysztof Kozlowski
Cc: Kukjin Kim
Document compatibles used on other Exynos-based boards (non-Samsung):
FriendlyARM, Google, Hardkernel and Insignal.
Signed-off-by: Krzysztof Kozlowski
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Cc: Hakjoo Kim
Reviewed-by: Javier Martinez Canillas
---
Changes since v2:
1. None
Changes
SRAM bindings for various SoCs, using the mmio-sram genalloc
API, are spread over different places - per SoC vendor. Since all of
these are quite similar (they depend on mmio-sram) move them to a common
place.
Signed-off-by: Krzysztof Kozlowski
Cc: Heiko Stuebner
Cc: Maxime Ripard
Cc: Chen-Yu
On Fri, Oct 23, 2015 at 7:46 AM, Vishnu Patekar
wrote:
> Allwinner A83T is octa-core cortex-a7 based SoC.
> It's clock control unit and prcm, pinmux are different from previous sun8i
> series.
> Its processor cores are arragned in two clusters 4 cores each,
> similar to A80.
>
> Signed-off-by:
On 2015년 10월 22일 21:23, Arnd Bergmann wrote:
On Wednesday 21 October 2015 19:06:52 glen lee wrote:
Hi arnd,
Thanks for the all the patches.
About the patch ( use proper naming for global symbols ),
We are planning to use this driver not only for wilc1000 but also for
other atmel wireless
Hi everyone,
This is v3 of the simplefb regulator support series. This series adds
regulator claiming and enabling support for simplefb.
Changes since v3:
- Dropped extra "if" which is always true, leftover from v1.
- Updated commit message of patch 1
Sometimes the simplefb display output
The physical display tied to the framebuffer may have regulators
providing power to it, such as power for LCDs or interface conversion
chips.
The number of regulators in use may vary, but the regulator supply
binding can not be a list. Instead just support any named regulator
supply properties
This claims and enables regulators listed in the simple framebuffer dt
node. This is needed so that regulators powering the display pipeline
and external hardware, described in the device node and known by the
kernel code, will remain properly enabled.
Signed-off-by: Chen-Yu Tsai
Reviewed-by:
On Tue, Oct 20, 2015 at 01:44:05PM -0500, Felipe Balbi wrote:
> Hi Greg,
>
> Here's the large gadget pull request for v4.4. All patches have been
> in next for a while and should be safe to apply.
>
> Let me know if you want any changes to this pull request.
>
> cheers
>
> The following
>From 10d158783de74ad28454ff54556abf89bd85c756 Mon Sep 17 00:00:00 2001
From: Tejun Heo
Date: Fri, 23 Oct 2015 10:13:35 +0900
Now that cgroup v2 is almost out of the door, replace the development
documentation unified-hierarchy.txt with Documentation/cgroup.txt
which is a superset of
Hello,
On Thu, Oct 22, 2015 at 11:36:05PM +0900, Tejun Heo wrote:
> It works with ext2 and 4 and btrfs. Will document it. Thanks.
Updated to include all writeback information from
blkio-controller.txt.
5-3-2. Writeback
Page cache is dirtied through buffered writes and shared mmaps and
On 10/22/2015 06:07 PM, Brian Norris wrote:
+ Han
On Wed, Oct 21, 2015 at 07:31:46AM -0700, Guenter Roeck wrote:
Attempts to build fsl-quadspi on SPARC fail with
drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error:
'LUT_0'
Darren Hart writes:
>
> Is there a good description of what is expected of a TAB member? How much time
> is involved? What makes a great TAB member?
>
> I've found: http://www.linuxfoundation.org/programs/advisory-councils/tab
>
> I've read the charter and scanned some of the minutes, but I'd
+ Han
On Wed, Oct 21, 2015 at 07:31:46AM -0700, Guenter Roeck wrote:
> Attempts to build fsl-quadspi on SPARC fail with
>
> drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
> drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error:
> 'LUT_0' undeclared (first use in this
Dear Tony,
> -Original Message-
> From: Luck, Tony [mailto:tony.l...@intel.com]
> Sent: Friday, October 23, 2015 8:27 AM
> To: Kamezawa, Hiroyuki/亀澤 寛之; Izumi, Taku/泉 拓; linux-kernel@vger.kernel.org;
> linux...@kvack.org
> Cc: qiuxi...@huawei.com; m...@csn.ul.ie;
On Thu, Oct 22, 2015 at 5:15 PM, jason wrote:
>
>
> On Thursday, October 22, 2015 04:47 PM, Tejun Heo wrote:
>>
>> Hello,
>>
>> On Mon, Oct 19, 2015 at 07:40:13AM -0700, Zhangqing Luo wrote:
>>
>> > So every time blk_mq_freeze_queue_start, it runs in this way
>> >
>> >
On 10/22/2015 03:25 PM, Jerome Glisse wrote:
> On Thu, Oct 22, 2015 at 02:23:08PM -0700, Dave Hansen wrote:
...
>> Can you give an example of where a process might be doing a gup and it
>> is completely separate from the CPU context that it's being executed under?
>
> In
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