Re: [PATCH v9 3/8] scsi: ufs-qcom: update configuration option of SCSI_UFS_QCOM component

On 10/28/2015 12:15 PM, Yaniv Gardi wrote: > This change is required in order to be able to build the component > as a module. > > Reviewed-by: Akinobu Mita > Reviewed-by: Subhash Jadavani > Reviewed-by: Gilad Broner > Signed-off-by: Yaniv Gardi > > --- > drivers/scsi/ufs/Kconfig | 2 +- >

[RESEND PATCH 3/4] ARM: dts: rockchip: Add Crypto drivers for rk3288

Add Crypto drivers for rk3288 including crypto controller and dma clk. Signed-off-by: Zain Wang --- arch/arm/boot/dts/rk3288.dtsi | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 6a79c9c..1706706 100644 ---

Re: [PATCH V1 00/11] MMCONFIG refactoring and ARM64 PCI hostbridge init based on ACPI

On 10/30/2015 05:07 AM, Jon Masters wrote: Hi Tomasz, Thanks for posting this series. On 10/27/2015 12:38 PM, Tomasz Nowicki wrote: From the functionality point of view this series might be split into two logic parts: 1. Making MMCONFIG code arch-agnostic which allows all architectures to

[PATCH] [DCCP]: Use 64-bit timekeeping

This patch changes the use of struct timespec in dccp_probe to use struct timespec64 instead. timespec uses a 32-bit seconds field which will overflow in the year 2038 and beyond. timespec64 uses a 64-bit seconds field. Note that the correctness of the code isn't changed, since the original code

[RESEND PATCH 0/4] Crypto: add crypto accelerator support for rk3288

This commit support three cipher(AES/DES/DES3) and two chainmode(ecb/cbc), and the more algorithms or new hash drivers will be added later on. Zain Wang (4): Crypto: Crypto driver support aes/des/des3 for rk3288 clk: rockchip: set an id for crypto clk ARM: dts: rockchip: Add Crypto drivers

[RESEND PATCH 2/4] clk: rockchip: set an id for crypto clk

set an id for crypto clk, so that it can be called in other part. Signed-off-by: Zain Wang --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 9040878..d74bd5d

[RESEND PATCH 4/4] crypto: rk_crypto - add DT bindings documentation

Add DT bindings documentation for the rk3288 crypto drivers. Signed-off-by: Zain Wang --- .../devicetree/bindings/crypto/rk-crypto.txt | 31 ++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/rk-crypto.txt diff --git

Re: [PATCH 1/2] mm, kasan: Added GFP flags to KASAN API

On 10/28/2015 07:39 PM, Alexander Potapenko wrote: > Add GFP flags to KASAN hooks for future patches to use. Really? These flags are still not used in the next patch (unless I missed something). > This is the first part of the "mm: kasan: unified support for SLUB and > SLAB allocators" patch

Re: [RFC 1/3] mm, oom: refactor oom detection

On Fri 30-10-15 14:23:59, KAMEZAWA Hiroyuki wrote: > On 2015/10/30 0:17, mho...@kernel.org wrote: [...] > > @@ -3135,13 +3145,56 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int > > order, > > if (gfp_mask & __GFP_NORETRY) > > goto noretry; > > > > - /* Keep reclaiming

Re: [lkp] [mm, page_alloc] 43993977ba: +88% OOM possibility

Michal Hocko writes: > On Wed 28-10-15 13:36:02, kernel test robot wrote: >> FYI, we noticed the below changes on >> >> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master >> commit 43993977baecd838d66ccabc7f682342fc6ff635 ("mm, page_alloc: >> distinguish between being

RE: [PATCH 3/3][v2] Thermal: do thermal zone update after a cooling device registered

Hi, Javi, thanks for your review, will send a version 3 out soon. > -Original Message- > From: Javi Merino [mailto:javi.mer...@arm.com] > Sent: Wednesday, October 28, 2015 6:40 PM > To: Chen, Yu C > Cc: Zhang, Rui; edubez...@gmail.com; linux...@vger.kernel.org; linux- >

Re: [PATCH v2 3/5] crypto: AF_ALG -- add setpubkey setsockopt call

Hi Stephan, > For supporting asymmetric ciphers, user space must be able to set the > public key. The patch adds a new setsockopt call for setting the public > key. > > Signed-off-by: Stephan Mueller > --- > crypto/af_alg.c | 14 +++--- > include/crypto/if_alg.h | 1 + > 2 files

Re: [PATCH] usb: dwc2: host: Fix ahbcfg for rk3066

On 10/21/2015 07:33 AM, Douglas Anderson wrote: The comment for ahbcfg for rk3066 parameters (also used for rk3288) claimed that ahbcfg was INCR16, but it wasn't. Since the bits weren't shifted properly, the 0x7 ended up being masked and we ended up programming 0x3 for the HBstLen. Let's set

Re: [PATCH v4 3/6] pinctrl: sunxi: Add H3 PIO controller support

Hi, On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: > The H3 uses the same pin controller as previous SoC's from Allwinner. > Add support for the pins controlled by the main PIO controller. > > Signed-off-by: Jens Kuske > Acked-by: Maxime Ripard > --- >

Re: [PATCH 2/2] dma: add Qualcomm Technologies HIDMA channel driver

Hi Sinan, [auto build test ERROR on lwn/docs-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-management-driver/20151030-111408 config: i386

Re: [PATCH 1/3] dmaengine: ti-dma-crossbar: dra7: Use bitops instead of idr

For the record... On 10/29/2015 10:28 AM, Peter Ujfalusi wrote: > The use of idr was nice, but it was a bit heavy and we did not need the > features it provides. Using simple bitmap to track allocated DMA channels > is adequate here and it will be easier to add support for reserving > channels

Re: [PATCH 2/2] dma: add Qualcomm Technologies HIDMA channel driver

Hi Sinan, [auto build test ERROR on lwn/docs-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-management-driver/20151030-111408 config: i386

[PATCH v2 2/3] dmaengine: ti-dma-crossbar: dra7: Support for reserving DMA event ranges

In eDMA the events are directly mapped to a DMA channel (for example DMA event 14 can only be handled by DMA channel 14). If the memcpy is enabled on the eDMA, there is a possibility that the crossbar driver would assign DMA event number already allocated in eDMA for memcpy. Furthermore the eDMA

[PATCH v2 3/3] dmaengine: ti-dma-crossbar: dra7: Support for eDMA with new bindings

Allow the crossbar driver to be used with the eDMA node with non legacy binding. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti-dma-crossbar.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c index dac7ae06cc58..e107779b1a2e

[PATCH v2 1/3] dmaengine: ti-dma-crossbar: dra7: Use bitops instead of idr

The use of idr was nice, but it was a bit heavy and we did not need the features it provides. Using simple bitmap to track allocated DMA channels is adequate here and it will be easier to add support for reserving channels later on. Signed-off-by: Peter Ujfalusi ---

[PATCH v2 0/3] dmaengine: ti-dma-crossbar: channel reserving and edma3-tpcc support

Hi, Changes since v1: - Fixed issue introduced by the bitops patch: wrong error check, also switch to use find_first_zero_bit() instead of find_next_zero_bit() Cover letter: This series depends on the eDMA work I have done, which has been now applied: https://lkml.org/lkml/2015/10/16/64 DRA7

[PATCH v3 1/3] ARM: DTS: dra7: Fix McASP3 node regarding to clocks

McASP node needs to list all mandatory clocks: gfclk and ahclkx Signed-off-by: Peter Ujfalusi --- arch/arm/boot/dts/dra7.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index bc672fb91466..fe99231cbde5 100644

[PATCH v3 0/3] ARM: OMAP2+ McASP(3) support for DRA7xx family

Hi Paul, Tony, Changes since v2: - DTS patch added which is needed because of the clock handling changes Felip Balbi reported that linux-next is broken right now since the DTS part of the earlier series has been applied, but we do not have the mcasp hwmod in the kernel: ... [0.181029]

[PATCH v3 3/3] ARM: OMAP: DRA7: hwmod: Add data for McASP3

McASP3 is used by default on DRA7x based boards for audio. Signed-off-by: Peter Ujfalusi --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 56 +++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

[PATCH v3 2/3] ARM: OMAP2+: hwmod: Add hwmod flag for HWMOD_OPT_CLKS_NEEDED

Some module needs more than one functional clock in order to be accessible, like the McASPs found in DRA7xx family. This flag will indicate that the opt_clks need to be handled at the same time as the main_clk for the given hwmod, ensuring that all needed clocks are enabled before we try to access

[PATCH] pinctrl:Convert the composition of devm_request_mem_region and devm_ioremap to a single call

Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because this value is alreadytaken care by devm_ioremap_resource() Signed-off-by: Sanjeev Sharma --- drivers/pinctrl/pinctrl-single.c | 21 +++-- 1

[PATCH] mfd: sec-core: Remove unused s2mpu02-rtc and s2mpu02-clk children

The commit 54e8827d5f0e ("mfd: sec-core: Add support for S2MPU02 device") added new MFD child devices for S2MPU02: RTC and clock provider (the clock provider with new compatible). However support for these devices was not added to existing drivers (rtc-s5m, clk-s2mps11). New drivers were not

Re: [PATCH 1/3] staging: lustre: checkpatch cleanups for nidstring.c

On Thu, Oct 29, 2015 at 07:28:21PM -0400, James Simmons wrote: > With nidstring now having the latest fixes we can > now clean up all the remaining checkpatch errors > for nidstring.c. > > Signed-off-by: James Simmons > --- You are doing different types of changes in this patch. Please split

Re: [PATCH V2 3/3] perf/powerpc :add support for sampling intr machine state

On Monday 26 October 2015 06:14 PM, Anju T wrote: > The registers to sample are passed through the sample_regs_intr bitmask. > The name and bit position for each register is defined in asm/perf_regs.h. > This feature can be enabled by using -I option with perf record command. > To display the

Re: [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: > Currently, the sunxi clock driver gets the name for the base factor clock > of divs clocks from the name field in factors_data. This prevents reusing > of the factor clock for clocks with same properties, but different name. > > This commit

Re: [PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

On 30.10.2015 15:25, Alim Akhtar wrote: > From: Thomas Abraham > > Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device > is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. > This also supports RTC and three 32.768KHz clock outputs. > > Cc:

Re: [PATCH v2] pwm-backlight: fix the panel power sequence

Hi Hpilipp, On Thu, 2015-10-29 at 16:40 +0100, Philipp Zabel wrote: > Hi YH, > > Am Donnerstag, den 22.10.2015, 23:12 +0800 schrieb YH Huang: > > In the case of the panel disabled by the bootloader, > > your patch still has the following code and always enables the backlight > > in the probe

[PATCH] i2c: designware: Don't mask TX_EMPTY if write is in progress

Currently when i2c_msg index search is completed, TX_EMPTY interrupt will be masked. But if the size of i2c_msg data is longer than the size of the tx buffer, we still need TX_EMPTY interrupt, otherwise we will get "controller timed out" error. This patch fixes this issue by only masking TX_EMPTY

Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

Hi, On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > > Signed-off-by: Jens Kuske > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 482 > > 1

Re: [PATCH 2/2] drivers:staging:gdm724x Fill all alignment should match open parentheses

On Thu, Oct 29, 2015 at 09:15:01PM +0100, Bogicevic Sasa wrote: > This fixes all errors about alignment with open parentheses as well as > one spacing needed around "-" sign since the patch would not be valid if > I left it there 1) That becomes two different type of change. 2) This has already

[PATCH] KVM: x86: removing unused variable

removing unused variables, found by coccinelle Signed-off-by: Saurabh Sengar --- arch/x86/kvm/x86.c | 16 +--- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9a9a198..ec15294 100644 --- a/arch/x86/kvm/x86.c +++

RE: [PATCH 0/4] PCI: rcar: Add support for ARM64 and multiple instances

Hi Bjorn, On 30 October 2015 07:19, Phil wrote > On 29 October 2015 23:03, Bjorn wrote: > > On Thu, Oct 29, 2015 at 07:48:00PM +0100, Wolfram Sang wrote: > > > On Thu, Oct 29, 2015 at 04:44:06PM +, Phil Edworthy wrote: > > > > Hi Wolfram, > > > > > > > > On 29 October 2015 16:40, Wolfram

Re: [PATCH v4 1/4] Documentation: dt-bindings: Describe SROMc configuration

On 30.10.2015 15:58, Pavel Fedin wrote: > Hello! > >>> Add documentation for new subnode properties, allowing bank configuration. >>> Based on u-boot implementation, but heavily reworked. >> >> Please, carefully look at: >> Documentation/devicetree/bindings/net/gpmc-eth.txt >>

Re: [PATCH 0/3] dmaengine: ti-dma-crossbar: channel reserving and edma3-tcc support

Vinod, On 10/29/2015 10:28 AM, Peter Ujfalusi wrote: > Hi, > > This series depends on the eDMA work I have done, which has been now applied: > https://lkml.org/lkml/2015/10/16/64 > > DRA7 family of chips have both sDMA and eDMA. Currently only sDMA can be used > becasue the old driver stack for

RE: [PATCH 0/4] PCI: rcar: Add support for ARM64 and multiple instances

Hi Bjorn, On 29 October 2015 23:03, Bjorn wrote: > On Thu, Oct 29, 2015 at 07:48:00PM +0100, Wolfram Sang wrote: > > On Thu, Oct 29, 2015 at 04:44:06PM +, Phil Edworthy wrote: > > > Hi Wolfram, > > > > > > On 29 October 2015 16:40, Wolfram wrote: > > > > > Ouch, my bad. I have been working

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[PATCH] net: smsc911x: Reset PHY during initialization

On certain hardware after software reboot the chip may get stuck and fail to reinitialize during reset. This can be fixed by ensuring that PHY is reset too. Old PHY resetting method required operational MDIO interface, therefore the chip should have been already set up. In order to be able to

[PATCH 0/8] MADV_FREE support

MADV_FREE is on linux-next so long time. The reason was two, I think. 1. MADV_FREE code on reclaim path was really mess. 2. Andrew really want to see voice of userland people who want to use the syscall. A few month ago, Daniel Micay(jemalloc active contributor) requested me to make progress

[PATCH 1/8] mm: support madvise(MADV_FREE)

Linux doesn't have an ability to free pages lazy while other OS already have been supported that named by madvise(MADV_FREE). The gain is clear that kernel can discard freed pages rather than swapping out or OOM if memory pressure happens. Without memory pressure, freed pages would be reused by

Re: kernel oops on mmotm-2015-10-15-15-20

On Thu, Oct 29, 2015 at 11:52:06AM +0200, Kirill A. Shutemov wrote: > On Thu, Oct 29, 2015 at 04:58:29PM +0900, Minchan Kim wrote: > > On Thu, Oct 29, 2015 at 02:25:24AM +0200, Kirill A. Shutemov wrote: > > > On Thu, Oct 22, 2015 at 06:00:51PM +0900, Minchan Kim wrote: > > > > On Thu, Oct 22, 2015

[PATCH 7/8] mm: clear PG_dirty to mark page freeable

Basically, MADV_FREE relies on dirty bit in page table entry to decide whether VM allows to discard the page or not. IOW, if page table entry includes marked dirty bit, VM shouldn't discard the page. However, as a example, if swap-in by read fault happens, page table entry doesn't have dirty bit

[PATCH 3/8] arch: uapi: asm: mman.h: Let MADV_FREE have same value for all architectures

From: Chen Gang For uapi, need try to let all macros have same value, and MADV_FREE is added into main branch recently, so need redefine MADV_FREE for it. At present, '8' can be shared with all architectures, so redefine it to '8'. Cc: r...@twiddle.net , Cc: i...@jurassic.park.msu.ru Cc:

[PATCH 6/8] mm: lru_deactivate_fn should clear PG_referenced

deactivate_page aims for accelerate for reclaiming through moving pages from active list to inactive list so we should clear PG_referenced for the goal. Acked-by: Hugh Dickins Suggested-by: Andrew Morton Signed-off-by: Minchan Kim --- mm/swap.c | 1 + 1 file changed, 1 insertion(+) diff

[PATCH 8/8] mm: mark stable page dirty in KSM

The MADV_FREE patchset changes page reclaim to simply free a clean anonymous page with no dirty ptes, instead of swapping it out; but KSM uses clean write-protected ptes to reference the stable ksm page. So be sure to mark that page dirty, so it's never mistakenly discarded. [hughd: adjusted

[PATCH 4/8] mm: free swp_entry in madvise_free

When I test below piece of code with 12 processes(ie, 512M * 12 = 6G consume) on my (3G ram + 12 cpu + 8G swap, the madvise_free is siginficat slower (ie, 2x times) than madvise_dontneed. loop = 5; mmap(512M); while (loop--) { memset(512M); madvise(MADV_FREE or MADV_DONTNEED); }

[PATCH 5/8] mm: move lazily freed pages to inactive list

MADV_FREE is a hint that it's okay to discard pages if there is memory pressure and we use reclaimers(ie, kswapd and direct reclaim) to free them so there is no value keeping them in the active anonymous LRU so this patch moves them to inactive LRU list's head. This means that MADV_FREE-ed pages

[PATCH 2/8] mm: define MADV_FREE for some arches

Most architectures use asm-generic, but alpha, mips, parisc, xtensa need their own definitions. This patch defines MADV_FREE for them so it should fix build break for their architectures. Maybe, I should split and feed piecies to arch maintainers but included here for mmotm convenience. Cc:

[PATCH v5 3/3] arm64: dts: Add BRCM IPROC NAND DT node for NS2

The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Brian Norris ---

[PATCH v5 2/3] mtd: brcmnand: Force 8bit mode before doing nand_scan_ident()

Just like other NAND controllers, the NAND READID command only works in 8bit mode for all versions of BRCMNAND controller. This patch forces 8bit mode for each NAND CS in brcmnand_init_cs() before doing nand_scan_ident() to ensure that BRCMNAND controller is in 8bit mode when NAND READID command

[PATCH v5 1/3] mtd: brcmnand: factor out CFG and CFG_EXT bitfields

From: Brian Norris Use enum instead of magic numbers for CFG and CFG_EXT bitfields. Signed-off-by: Brian Norris Tested-by: Anup Patel --- drivers/mtd/nand/brcmnand/brcmnand.c | 38 +--- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git

[PATCH v5 0/3] NAND support for Broadcom NS2 SoC

We enable NAND support for Broadcom NS2 SoC by reusing existing BRCMNAND driver. This patchset applies on-top of "arm64: Simple additions to NS2 DT" v1 patchset and is available in ns2_nand_v5 branch of https://github.com/Broadcom/arm64-linux.git. The patchset is tested on NS2 SVK. Changes

RE: [PATCH v4 2/3] mtd: brcmnand: Force 8bit mode before doing nand_scan_ident()

> -Original Message- > From: Anup Patel [mailto:anup.pa...@broadcom.com] > Sent: 30 October 2015 11:49 > To: David Woodhouse; Brian Norris; Linux MTD > Cc: Rob Herring; Pawel Moll; Mark Rutland; Catalin Marinas; Will Deacon; > Sudeep Holla; Ian Campbell; Kumar Gala; Ray Jui; Scott

RE: [PATCH v4 0/3] NAND support for Broadcom NS2 SoC

Hi All, Please disregard this patchset. There is an accidental typo in patch2. We should use ~CFG_BUS_WIDTH instead of CFG_BUS_WIDTH in patch2. I will quickly send v5 patchset to fix this. Sorry, for the noise. Regards, Anup -- To unsubscribe from this list: send the line "unsubscribe

RE: [PATCH v4 1/4] Documentation: dt-bindings: Describe SROMc configuration

Hello! > > Add documentation for new subnode properties, allowing bank configuration. > > Based on u-boot implementation, but heavily reworked. > > Please, carefully look at: > Documentation/devicetree/bindings/net/gpmc-eth.txt > Documentation/devicetree/bindings/bus/ti-gpmc.txt Thank you

RE: [PATCH v4 0/4] [PATCH v4 0/4] Exynos SROMc configuration and Ethernet support for SMDK5410

Hello! > > .../bindings/arm/samsung/exynos-srom.txt | 50 ++- > > arch/arm/boot/dts/exynos5410-smdk5410.dts | 41 +++ > > arch/arm/boot/dts/exynos5410.dtsi | 15 ++ > > arch/arm/mach-exynos/Kconfig | 2 +-

RE: [PATCH v4 2/4] ARM: dts: Add SROMc to Exynos 5410

Hello! > -Original Message- > From: linux-samsung-soc-ow...@vger.kernel.org > [mailto:linux-samsung-soc-ow...@vger.kernel.org] > On Behalf Of Pankaj Dubey > Sent: Thursday, October 29, 2015 8:28 PM > To: Pavel Fedin > Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;

[PATCH 4/4] crypto: rk_crypto - add DT bindings documentation

Add DT bindings documentation for the rk3288 crypto drivers. Signed-off-by: Zain Wang --- .../devicetree/bindings/crypto/rk-crypto.txt | 31 ++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/rk-crypto.txt diff --git

[PATCH 2/4] clk: rockchip: set an id for crypto clk

set an id for crypto clk, so that it can be called in other part. Signed-off-by: Zain Wang --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 9040878..d74bd5d

[PATCH 3/4] ARM: dts: rockchip: Add Crypto drivers for rk3288

Add Crypto drivers for rk3288 including crypto controller and dma clk. Signed-off-by: Zain Wang --- arch/arm/boot/dts/rk3288.dtsi | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 6a79c9c..1706706 100644 ---

[PATCH 0/4] Crypto: add crypto accelerator support for rk3288

This commit support three cipher(AES/DES/DES3) and two chainmode(ecb/cbc), and the more algorithms or new hash drivers will be added later on. Zain Wang (4): Crypto: Crypto driver support aes/des/des3 for rk3288 clk: rockchip: set an id for crypto clk ARM: dts: rockchip: Add Crypto drivers

[PATCH 1/4] Crypto: Crypto driver support aes/des/des3 for rk3288

Crypto driver support cbc/ecb two chainmode, and aes/des/des3 three cipher mode. The names registered are: ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede) You can alloc tags above in your case. And other algorithms and platforms will be added later on. Signed-off-by: Zain

Re: [PATCH v4 1/4] Documentation: dt-bindings: Describe SROMc configuration

On 29.10.2015 21:42, Pavel Fedin wrote: > Add documentation for new subnode properties, allowing bank configuration. > Based on u-boot implementation, but heavily reworked. Please, carefully look at: Documentation/devicetree/bindings/net/gpmc-eth.txt

Re: [RFC PATCH] VFIO: Add a parameter to force nonthread IRQ

On Thu, Oct 29, 2015 at 10:45:44AM +0100, Paolo Bonzini wrote: > > > On 29/10/2015 04:11, Alex Williamson wrote: > > > The irqfd is already able to schedule a work item, because it runs with > > > interrupts disabled, so I think we can always return IRQ_HANDLED. > > > > I'm confused by this.

[PATCH v5 3/4] regulator: s2mps11: add support for S2MPS15 regulators

From: Thomas Abraham The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains 27 LDO and 10 Buck regulators and allows programming these regulators via a I2C interface. This patch adds initial support for LDO/Buck regulators of S2MPS15 PMIC. Signed-off-by: Thomas Abraham

[PATCH v5 2/4] mfd: sec: Add support for S2MPS15 PMIC

From: Thomas Abraham Add support for S2MPS15 PMIC which is similar to S2MPS11 PMIC. The S2MPS15 PMIC supports 27 LDO regulators, 10 buck regulators, RTC, three 32.768KHz clock outputs and battery charger. This patch adds initial support for LDO and buck regulators of S2MPS15 device.

[PATCH v5 4/4] drivers/rtc/rtc-s5m.c: add support for S2MPS15 RTC

RTC found in s2mps15 is almost same as one found on s2mps13 with few differences in RTC_UPDATE register fields, like: 1> Bit[4] and Bit[1] are reversed - On s2mps13 WUDR -> bit[4], AUDR -> bit[1] - On s2mps15 WUDR -> bit[1], AUDR -> bit[4] 2> In case of s2mps13, for alarm

[PATCH v5 1/4] dt-bindings: mfd: s2mps11: add documentation for s2mps15 PMIC

From: Thomas Abraham Add dt-binding documentation for s2mps15 PMIC device. The s2mps15 device is similar to s2mps11/14 PMIC device and has 27 LDO and 10 buck regulators. This also supports RTC and three 32.768KHz clock outputs. Cc: devicet...@vger.kernel.org Signed-off-by: Thomas Abraham

[PATCH v5 0/4] mfd: sec: add S2MPS15 PMIC support

Samsung's S2MPS15 PMIC is targetted to be used with Samsung's Exynos7 SoC. The S2MPS15 PMIC is similar in functionality to S2MPS11/14 PMIC. It contains 27 LDO and 10 Buck regulators, RTC, three 32.768 KHz clock outputs and allows programming these blocks via a I2C interface. This patch series adds

Re: [RFC] perf: fix building for ARCv1

On Saturday 17 October 2015 07:06 PM, Alexey Brodkin wrote: > Perf uses atomic options and so it is required to have atomics enabled > in toolchain. > > In case of ARC atomics are enabled by default for ARCv2 but disabled for > ARCv1. Now we explicitly enable atomics for either ARC achitecture >

Re: [RFC] perf: fix building for ARCv1

On Thursday 29 October 2015 09:28 PM, Alexey Brodkin wrote: > Hi Vineet, > > On Tue, 2015-10-20 at 10:45 +, Vineet Gupta wrote: >> On Tuesday 20 October 2015 03:41 PM, Peter Zijlstra wrote: > Can we use existing syscall(s) - again this is what our good old pthread > library > code

[PATCH v4 3/3] arm64: dts: Add BRCM IPROC NAND DT node for NS2

The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Brian Norris ---

[PATCH] net: rds: chnaging the return type from int to void

as return type of function rds_iw_flush_mr_pool no where checked, chnaging its return type from int to void. also removing the unused variable rc as there is nothing to return. Signed-off-by: Saurabh Sengar --- net/rds/iw_rdma.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff

Re: [PATCH] mm: Introduce kernelcore=reliable option

On 2015/10/23 10:44, Luck, Tony wrote: > First part of each memory controller. I have two memory controllers on each > node > If each memory controller has the same distance/latency, you (your firmware) don't need to allocate reliable memory per each memory controller. If distance is problem,

[PATCH v4 1/3] mtd: brcmnand: factor out CFG and CFG_EXT bitfields

From: Brian Norris Use enum instead of magic numbers for CFG and CFG_EXT bitfields. Signed-off-by: Brian Norris Tested-by: Anup Patel --- drivers/mtd/nand/brcmnand/brcmnand.c | 38 +--- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git

[PATCH v4 2/3] mtd: brcmnand: Force 8bit mode before doing nand_scan_ident()

Just like other NAND controllers, the NAND READID command only works in 8bit mode for all versions of BRCMNAND controller. This patch forces 8bit mode for each NAND CS in brcmnand_init_cs() before doing nand_scan_ident() to ensure that BRCMNAND controller is in 8bit mode when NAND READID command

[PATCH v4 0/3] NAND support for Broadcom NS2 SoC

We enable NAND support for Broadcom NS2 SoC by reusing existing BRCMNAND driver. This patchset applies on-top of "arm64: Simple additions to NS2 DT" v1 patchset and is available in ns2_nand_v4 branch of https://github.com/Broadcom/arm64-linux.git. The patchset is tested on NS2 SVK. Changes

Re: [for-next][PATCH 4/5] tracing: Check all tasks on each CPU when filtering pids

On Thu, Oct 29, 2015 at 03:07:58AM -0400, Steven Rostedt wrote: > static ssize_t > ftrace_event_pid_write(struct file *filp, const char __user *ubuf, > size_t cnt, loff_t *ppos) > @@ -1711,6 +1727,12 @@ ftrace_event_pid_write(struct file *filp, const char > __user *ubuf, >

Re: [PATCH 6/7] clocksource/drivers/pxa_timer: Add the COMPILE_TEST option

Hi Daniel, [auto build test ERROR on tip/timers/core -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Daniel-Lezcano/time-Define-dummy-functions-for-the-generic-sched-clock/20151030-065823 config: parisc

Re: [PATCH] recordmcount: arm64: replace the ignored mcount call into nop

在 2015/10/29 23:09, Will Deacon 写道: > On Thu, Oct 29, 2015 at 09:35:42PM +0800, kbuild test robot wrote: >> [auto build test ERROR on arm64/for-next/core -- if it's inappropriate base, >> please suggest rules for selecting the more suitable base] >> >> url: >>

Re: [PATCH v2 5/7] PCI: Wait 1 second between disabling VFs and clearing NumVFs

Wei, On 2015/10/30 13:14, Wei Yang wrote: On Thu, Oct 29, 2015 at 05:23:22PM -0500, Bjorn Helgaas wrote: From: Alexander Duyck Per sec 3.3.3.1 of the SR-IOV spec, r1.1, we must allow 1.0s after clearing VF Enable before reading any field in the SR-IOV Extended Capability. Wait 1 second

Re: [PATCH v2 5/7] PCI: Wait 1 second between disabling VFs and clearing NumVFs

Wei, On 2015/10/30 13:14, Wei Yang wrote: On Thu, Oct 29, 2015 at 05:23:22PM -0500, Bjorn Helgaas wrote: From: Alexander Duyck Per sec 3.3.3.1 of the SR-IOV spec, r1.1, we must allow 1.0s after clearing VF Enable before reading any field in the SR-IOV Extended

Re: [RFC] perf: fix building for ARCv1

On Thursday 29 October 2015 09:28 PM, Alexey Brodkin wrote: > Hi Vineet, > > On Tue, 2015-10-20 at 10:45 +, Vineet Gupta wrote: >> On Tuesday 20 October 2015 03:41 PM, Peter Zijlstra wrote: > Can we use existing syscall(s) - again this is what our good old pthread > library > code

Re: [RFC] perf: fix building for ARCv1

On Saturday 17 October 2015 07:06 PM, Alexey Brodkin wrote: > Perf uses atomic options and so it is required to have atomics enabled > in toolchain. > > In case of ARC atomics are enabled by default for ARCv2 but disabled for > ARCv1. Now we explicitly enable atomics for either ARC achitecture >

RE: [PATCH v4 0/4] [PATCH v4 0/4] Exynos SROMc configuration and Ethernet support for SMDK5410

Hello! > > .../bindings/arm/samsung/exynos-srom.txt | 50 ++- > > arch/arm/boot/dts/exynos5410-smdk5410.dts | 41 +++ > > arch/arm/boot/dts/exynos5410.dtsi | 15 ++ > > arch/arm/mach-exynos/Kconfig | 2 +-

[PATCH 7/8] mm: clear PG_dirty to mark page freeable

Basically, MADV_FREE relies on dirty bit in page table entry to decide whether VM allows to discard the page or not. IOW, if page table entry includes marked dirty bit, VM shouldn't discard the page. However, as a example, if swap-in by read fault happens, page table entry doesn't have dirty bit

[PATCH 3/8] arch: uapi: asm: mman.h: Let MADV_FREE have same value for all architectures

From: Chen Gang For uapi, need try to let all macros have same value, and MADV_FREE is added into main branch recently, so need redefine MADV_FREE for it. At present, '8' can be shared with all architectures, so redefine it to '8'. Cc: r...@twiddle.net

[PATCH 8/8] mm: mark stable page dirty in KSM

The MADV_FREE patchset changes page reclaim to simply free a clean anonymous page with no dirty ptes, instead of swapping it out; but KSM uses clean write-protected ptes to reference the stable ksm page. So be sure to mark that page dirty, so it's never mistakenly discarded. [hughd: adjusted

Re: kernel oops on mmotm-2015-10-15-15-20

On Thu, Oct 29, 2015 at 11:52:06AM +0200, Kirill A. Shutemov wrote: > On Thu, Oct 29, 2015 at 04:58:29PM +0900, Minchan Kim wrote: > > On Thu, Oct 29, 2015 at 02:25:24AM +0200, Kirill A. Shutemov wrote: > > > On Thu, Oct 22, 2015 at 06:00:51PM +0900, Minchan Kim wrote: > > > > On Thu, Oct 22, 2015

[PATCH 4/8] mm: free swp_entry in madvise_free

When I test below piece of code with 12 processes(ie, 512M * 12 = 6G consume) on my (3G ram + 12 cpu + 8G swap, the madvise_free is siginficat slower (ie, 2x times) than madvise_dontneed. loop = 5; mmap(512M); while (loop--) { memset(512M); madvise(MADV_FREE or MADV_DONTNEED); }

[PATCH 5/8] mm: move lazily freed pages to inactive list

MADV_FREE is a hint that it's okay to discard pages if there is memory pressure and we use reclaimers(ie, kswapd and direct reclaim) to free them so there is no value keeping them in the active anonymous LRU so this patch moves them to inactive LRU list's head. This means that MADV_FREE-ed pages

[PATCH 6/8] mm: lru_deactivate_fn should clear PG_referenced

deactivate_page aims for accelerate for reclaiming through moving pages from active list to inactive list so we should clear PG_referenced for the goal. Acked-by: Hugh Dickins Suggested-by: Andrew Morton Signed-off-by: Minchan Kim

Re: [PATCH 0/3] dmaengine: ti-dma-crossbar: channel reserving and edma3-tcc support

Vinod, On 10/29/2015 10:28 AM, Peter Ujfalusi wrote: > Hi, > > This series depends on the eDMA work I have done, which has been now applied: > https://lkml.org/lkml/2015/10/16/64 > > DRA7 family of chips have both sDMA and eDMA. Currently only sDMA can be used > becasue the old driver stack for

Re: [PATCH 2/2] drivers:staging:gdm724x Fill all alignment should match open parentheses

On Thu, Oct 29, 2015 at 09:15:01PM +0100, Bogicevic Sasa wrote: > This fixes all errors about alignment with open parentheses as well as > one spacing needed around "-" sign since the patch would not be valid if > I left it there 1) That becomes two different type of change. 2) This has already

Re: [PATCH v2] pwm-backlight: fix the panel power sequence

Hi Hpilipp, On Thu, 2015-10-29 at 16:40 +0100, Philipp Zabel wrote: > Hi YH, > > Am Donnerstag, den 22.10.2015, 23:12 +0800 schrieb YH Huang: > > In the case of the panel disabled by the bootloader, > > your patch still has the following code and always enables the backlight > > in the probe

[PATCH] i2c: designware: Don't mask TX_EMPTY if write is in progress

Currently when i2c_msg index search is completed, TX_EMPTY interrupt will be masked. But if the size of i2c_msg data is longer than the size of the tx buffer, we still need TX_EMPTY interrupt, otherwise we will get "controller timed out" error. This patch fixes this issue by only masking TX_EMPTY

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