The correct DT property for specifying a GPIO used for reset
is "reset-gpios", the driver now accepts this name use this here.
Signed-off-by: Andrew F. Davis
---
Changes from v1:
- Remove "fix" from commit message
arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 2 +-
1 file changed, 1 insertion(+),
The correct DT property for specifying a GPIO used for reset
is "reset-gpios", the driver now accepts this name use this here.
Signed-off-by: Andrew F. Davis
---
Changes from v1:
- Remove "fix" from commit message
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++--
1 file changed, 2
On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> Then I need to get the DW_AT_location stuff parsed in pahole, so
> that with those offsets (second column, ending with :) with hits (first
> column, there its local period, but we can ask for some specific metric
>
On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> Then I need to get the DW_AT_location stuff parsed in pahole, so
> that with those offsets (second column, ending with :) with hits (first
> column, there its local period, but we can ask for some specific metric
>
On Fri, Aug 31, 2018 at 06:57:48PM +0530, Manish Narani wrote:
> Add information of ZynqMP DDRC which reports the single bit errors that
> are corrected and the double bit errors that are detected.
>
> Signed-off-by: Manish Narani
> ---
> .../bindings/memory-controllers/synopsys.txt | 27
On Fri, Aug 31, 2018 at 06:57:48PM +0530, Manish Narani wrote:
> Add information of ZynqMP DDRC which reports the single bit errors that
> are corrected and the double bit errors that are detected.
>
> Signed-off-by: Manish Narani
> ---
> .../bindings/memory-controllers/synopsys.txt | 27
From: Colin Ian King
Don't populate the array mclk_name on the stack but instead make it
static. Makes the object code smaller by 23 bytes:
Before:
textdata bss dec hex filename
38050 11604 64 49718c236 linux/drivers/mfd/arizona-core.o
After:
textdata
From: Colin Ian King
Don't populate the array mclk_name on the stack but instead make it
static. Makes the object code smaller by 23 bytes:
Before:
textdata bss dec hex filename
38050 11604 64 49718c236 linux/drivers/mfd/arizona-core.o
After:
textdata
The adxl372 is designed to communicate in either SPI or I2C protocol.
This patch adds the documentation of device tree bindings for adxl372
I2C.
Signed-off-by: Stefan Popa
---
Documentation/devicetree/bindings/iio/accel/adxl372.txt | 15 +--
1 file changed, 13 insertions(+), 2
The adxl372 is designed to communicate in either SPI or I2C protocol.
This patch adds the documentation of device tree bindings for adxl372
I2C.
Signed-off-by: Stefan Popa
---
Documentation/devicetree/bindings/iio/accel/adxl372.txt | 15 +--
1 file changed, 13 insertions(+), 2
The adxl372 is designed to communicate in either SPI or I2C protocol. It
autodetects the format being used, requiring no configuration control to
select the format.
Signed-off-by: Stefan Popa
---
MAINTAINERS | 1 +
drivers/iio/accel/Kconfig | 11
The adxl372 is designed to communicate in either SPI or I2C protocol. It
autodetects the format being used, requiring no configuration control to
select the format.
Signed-off-by: Stefan Popa
---
MAINTAINERS | 1 +
drivers/iio/accel/Kconfig | 11
On Fri, Aug 10, 2018 at 09:09:39PM +0530, Bharat Kumar Gogada wrote:
> Platforms may have dedicated IRQ lines for PCIe services like
> AER/PME etc., check for such IRQ lines.
> Check mask and fill legacy irq line for services other than
Capitalize "IRQ" consistently in English text like this.
On Fri, Aug 10, 2018 at 09:09:39PM +0530, Bharat Kumar Gogada wrote:
> Platforms may have dedicated IRQ lines for PCIe services like
> AER/PME etc., check for such IRQ lines.
> Check mask and fill legacy irq line for services other than
Capitalize "IRQ" consistently in English text like this.
Em Tue, Sep 04, 2018 at 03:58:35PM +0200, Jiri Olsa escreveu:
> On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> > On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > > So, use 'c2c record' to get the samples:
> > IIRC that uses numa events and is
Em Tue, Sep 04, 2018 at 03:58:35PM +0200, Jiri Olsa escreveu:
> On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> > On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > > So, use 'c2c record' to get the samples:
> > IIRC that uses numa events and is
Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor.
Its been more than 2 years of wait for this to be fixed, which has
no hopes to be fixed. This change was introduced for the "lead device"
on msm8996 platform. It looks like all publicly available msm8996
devices have this
Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor.
Its been more than 2 years of wait for this to be fixed, which has
no hopes to be fixed. This change was introduced for the "lead device"
on msm8996 platform. It looks like all publicly available msm8996
devices have this
Hi!
Any other comment before I resubmit v2 tomorrow from
https://github.com/ribalda/linux/tree/gpio-addr-flash-v2
So far the diff for v2 I have
>From Boris Brezillon:
-Add Fixes and cc:stable
>From kbuild:
- Fix warnings
- Rebase
Thanks!
On Tue, Aug 21, 2018 at 4:31 PM Ricardo Ribalda
Hi!
Any other comment before I resubmit v2 tomorrow from
https://github.com/ribalda/linux/tree/gpio-addr-flash-v2
So far the diff for v2 I have
>From Boris Brezillon:
-Add Fixes and cc:stable
>From kbuild:
- Fix warnings
- Rebase
Thanks!
On Tue, Aug 21, 2018 at 4:31 PM Ricardo Ribalda
On Wed, Aug 29, 2018 at 08:44:07PM +0800, Pu Wen wrote:
> The ideal_nops for Dhyana processors should be p6_nops.
>
> Signed-off-by: Pu Wen
> ---
> arch/x86/kernel/alternative.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/kernel/alternative.c
On Wed, Aug 29, 2018 at 08:44:07PM +0800, Pu Wen wrote:
> The ideal_nops for Dhyana processors should be p6_nops.
>
> Signed-off-by: Pu Wen
> ---
> arch/x86/kernel/alternative.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/kernel/alternative.c
On Mon, Sep 03, 2018 at 07:56:54AM +0200, Michal Hocko wrote:
> On Thu 30-08-18 14:39:44, Jerome Glisse wrote:
> > On Thu, Aug 30, 2018 at 11:05:16AM -0700, Mike Kravetz wrote:
> > > On 08/30/2018 09:57 AM, Jerome Glisse wrote:
> > > > On Thu, Aug 30, 2018 at 06:19:52PM +0200, Michal Hocko wrote:
On Mon, Sep 03, 2018 at 07:56:54AM +0200, Michal Hocko wrote:
> On Thu 30-08-18 14:39:44, Jerome Glisse wrote:
> > On Thu, Aug 30, 2018 at 11:05:16AM -0700, Mike Kravetz wrote:
> > > On 08/30/2018 09:57 AM, Jerome Glisse wrote:
> > > > On Thu, Aug 30, 2018 at 06:19:52PM +0200, Michal Hocko wrote:
On 4 Sep 2018, at 4:01, Kirill A. Shutemov wrote:
> On Tue, Sep 04, 2018 at 03:55:10PM +0800, Peter Xu wrote:
>> When splitting a huge page, we should set all small pages as dirty if
>> the original huge page has the dirty bit set before. Otherwise we'll
>> lose the original dirty bit.
>
> We
On 4 Sep 2018, at 4:01, Kirill A. Shutemov wrote:
> On Tue, Sep 04, 2018 at 03:55:10PM +0800, Peter Xu wrote:
>> When splitting a huge page, we should set all small pages as dirty if
>> the original huge page has the dirty bit set before. Otherwise we'll
>> lose the original dirty bit.
>
> We
On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > So, use 'c2c record' to get the samples:
>
> IIRC that uses numa events and is completely useless.
I guess perf record on any other event would work
in
On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > So, use 'c2c record' to get the samples:
>
> IIRC that uses numa events and is completely useless.
I guess perf record on any other event would work
in
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> +static void compress_event_handler(uint32_t opcode, uint32_t token,
> +uint32_t *payload, void *priv)
> +{
> + struct q6asm_dai_rtd *prtd = priv;
> + struct snd_compr_stream *substream = prtd->cstream;
> +
On 09/03/2018 06:26 AM, Mark Brown wrote:
> On Fri, Aug 31, 2018 at 01:05:07PM -0500, Andrew F. Davis wrote:
>> Leaving microphone bias off is a valid setting and even used in the DT
>> binding document example. Add this setting here and document the same.
>> Although it may not make much sense to
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> +static void compress_event_handler(uint32_t opcode, uint32_t token,
> +uint32_t *payload, void *priv)
> +{
> + struct q6asm_dai_rtd *prtd = priv;
> + struct snd_compr_stream *substream = prtd->cstream;
> +
On 09/03/2018 06:26 AM, Mark Brown wrote:
> On Fri, Aug 31, 2018 at 01:05:07PM -0500, Andrew F. Davis wrote:
>> Leaving microphone bias off is a valid setting and even used in the DT
>> binding document example. Add this setting here and document the same.
>> Although it may not make much sense to
On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> So, use 'c2c record' to get the samples:
IIRC that uses numa events and is completely useless.
On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> So, use 'c2c record' to get the samples:
IIRC that uses numa events and is completely useless.
On Fri, Aug 10, 2018 at 09:09:40PM +0530, Bharat Kumar Gogada wrote:
> Add nwl_setup_service_irqs hook to setup_platform_service_irq IRQs to
> register platform provided IRQ number to kernel AER service.
>
> Signed-off-by: Bharat Kumar Gogada
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c |
On Fri, Aug 10, 2018 at 09:09:40PM +0530, Bharat Kumar Gogada wrote:
> Add nwl_setup_service_irqs hook to setup_platform_service_irq IRQs to
> register platform provided IRQ number to kernel AER service.
>
> Signed-off-by: Bharat Kumar Gogada
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c |
Hi,
On 28/08/18 14:53, Patrick Bellasi wrote:
> The number of clamp groups supported is limited and defined at compile
> time. However, a malicious user can currently ask for many different
Even if not malicious.. :-)
> clamp values thus consuming all the available clamp groups.
>
> Since on
Hi,
On 28/08/18 14:53, Patrick Bellasi wrote:
> The number of clamp groups supported is limited and defined at compile
> time. However, a malicious user can currently ask for many different
Even if not malicious.. :-)
> clamp values thus consuming all the available clamp groups.
>
> Since on
On Mon, Sep 03, 2018 at 11:33:05AM +0200, Peter Zijlstra wrote:
> On Mon, Sep 03, 2018 at 10:54:23AM +0200, Peter Zijlstra wrote:
> > On Mon, Sep 03, 2018 at 09:38:15AM +0200, Thomas Gleixner wrote:
> > > On Mon, 3 Sep 2018, Peter Zijlstra wrote:
> > > > On Sat, Sep 01, 2018 at 11:51:26AM +0930,
On Mon, Sep 03, 2018 at 11:33:05AM +0200, Peter Zijlstra wrote:
> On Mon, Sep 03, 2018 at 10:54:23AM +0200, Peter Zijlstra wrote:
> > On Mon, Sep 03, 2018 at 09:38:15AM +0200, Thomas Gleixner wrote:
> > > On Mon, 3 Sep 2018, Peter Zijlstra wrote:
> > > > On Sat, Sep 01, 2018 at 11:51:26AM +0930,
Em Tue, Sep 04, 2018 at 09:10:49AM +0200, Peter Zijlstra escreveu:
> On Mon, Sep 03, 2018 at 07:45:48PM -0700, Stephane Eranian wrote:
> > A few weeks ago, you had asked if I had more requests for the perf tool.
> I have one long standing one; that is IP based data structure
> annotation.
>
Em Tue, Sep 04, 2018 at 09:10:49AM +0200, Peter Zijlstra escreveu:
> On Mon, Sep 03, 2018 at 07:45:48PM -0700, Stephane Eranian wrote:
> > A few weeks ago, you had asked if I had more requests for the perf tool.
> I have one long standing one; that is IP based data structure
> annotation.
>
On 15:22-20180903, Kishon Vijay Abraham I wrote:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC (cbass_main) in addition to the
> register space. The size of the
On 15:22-20180903, Kishon Vijay Abraham I wrote:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC (cbass_main) in addition to the
> register space. The size of the
On 09/02/2018 11:54 PM, Shawn Guo wrote:
> On Fri, Aug 31, 2018 at 02:17:31PM -0500, Andrew F. Davis wrote:
>> The correct DT property for specifying a GPIO used for reset
>> is "reset-gpios", fix this here.
>>
>> Fixes: d763762e3b58 ("ARM: dts: imx6: add ZII RDU2 boards")
>
> This Fixes tag and
On 09/02/2018 11:54 PM, Shawn Guo wrote:
> On Fri, Aug 31, 2018 at 02:17:31PM -0500, Andrew F. Davis wrote:
>> The correct DT property for specifying a GPIO used for reset
>> is "reset-gpios", fix this here.
>>
>> Fixes: d763762e3b58 ("ARM: dts: imx6: add ZII RDU2 boards")
>
> This Fixes tag and
On Tue, Sep 4, 2018 at 1:55 PM Benjamin Tissoires
wrote:
>
> On Fri, Aug 31, 2018 at 11:36 AM Benjamin Tissoires
> wrote:
> >
> > This partially reverts commit f07b3c1da92db108662f99417a212fc1eddc44d1.
> >
> > It looks like some mice are not correctly treated by
> > HID_QUIRK_INPUT_PER_APP.
On Tue, Sep 4, 2018 at 1:55 PM Benjamin Tissoires
wrote:
>
> On Fri, Aug 31, 2018 at 11:36 AM Benjamin Tissoires
> wrote:
> >
> > This partially reverts commit f07b3c1da92db108662f99417a212fc1eddc44d1.
> >
> > It looks like some mice are not correctly treated by
> > HID_QUIRK_INPUT_PER_APP.
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> This patch adds board specific bindings required for dais, In particular
> for compressed dais and dai direction.
>
> Board specific setup involves setting up some of dais as compressed dais
> and also specify direction of any dai. Some of the dais
On 2018/9/4 18:48, Borislav Petkov wrote:
On Wed, Aug 29, 2018 at 08:43:54PM +0800, Pu Wen wrote:
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
That sentence reads funny.
Will rewrite this
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> This patch adds board specific bindings required for dais, In particular
> for compressed dais and dai direction.
>
> Board specific setup involves setting up some of dais as compressed dais
> and also specify direction of any dai. Some of the dais
On 2018/9/4 18:48, Borislav Petkov wrote:
On Wed, Aug 29, 2018 at 08:43:54PM +0800, Pu Wen wrote:
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
That sentence reads funny.
Will rewrite this
commit f07b3c1da92d ("HID: generic: create one input report per
application type") was effectively the same as MULTI_INPUT:
hidinput->report was never set, so hidinput_match_application()
always returned null.
Fix that by testing against the real application.
Note that this breaks some old
Or it creates some weird input names like:
"MI Dongle MI Wireless Mouse Mouse"
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-input.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index
When implementing commit 7f81c8db5489 ("HID: multitouch: simplify
the settings of the various features"), I wrongly removed a test
that made sure we never try to set the second InputMode feature
to something else than 0.
This broke badly some recent Elan panels that now forget to send the
click
Now that the application is simply stored in struct hid_input, we can
overwrite it in mt_input_mapping() for the faulty egalax and have a
simpler suffix processing in mt_input_configured()
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-multitouch.c | 72
commit f07b3c1da92d ("HID: generic: create one input report per
application type") was effectively the same as MULTI_INPUT:
hidinput->report was never set, so hidinput_match_application()
always returned null.
Fix that by testing against the real application.
Note that this breaks some old
Or it creates some weird input names like:
"MI Dongle MI Wireless Mouse Mouse"
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-input.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index
When implementing commit 7f81c8db5489 ("HID: multitouch: simplify
the settings of the various features"), I wrongly removed a test
that made sure we never try to set the second InputMode feature
to something else than 0.
This broke badly some recent Elan panels that now forget to send the
click
Now that the application is simply stored in struct hid_input, we can
overwrite it in mt_input_mapping() for the faulty egalax and have a
simpler suffix processing in mt_input_configured()
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-multitouch.c | 72
Hi Jiri,
there is no real link between those 4 commit but the fact that I wrote
them today ;)
2 patches should at least be scheduled for v4.19: 1/4 and 3/4
Both are stable fixes for mistakes I made in v4.18.
Patch 2 and 4 are just nice to have, so v4.20 should be fine.
Cheers,
Benjamin
Hi Jiri,
there is no real link between those 4 commit but the fact that I wrote
them today ;)
2 patches should at least be scheduled for v4.19: 1/4 and 3/4
Both are stable fixes for mistakes I made in v4.18.
Patch 2 and 4 are just nice to have, so v4.20 should be fine.
Cheers,
Benjamin
For platforms whose firmwares provide valid module handles
(SMBIOS type 17) in error records, this patch uses the module
handles to locate corresponding DIMMs and enables per-DIMM
error counter update.
Signed-off-by: Fan Wu
Reviewed-by: Tyler Baicar
Tested-by: Toshi Kani
---
Changes from v3:
For platforms whose firmwares provide valid module handles
(SMBIOS type 17) in error records, this patch uses the module
handles to locate corresponding DIMMs and enables per-DIMM
error counter update.
Signed-off-by: Fan Wu
Reviewed-by: Tyler Baicar
Tested-by: Toshi Kani
---
Changes from v3:
On Tue, Aug 28, 2018 at 04:05:11PM +0100, Punit Agrawal wrote:
> Hi Bjorn,
>
> As discussed before[0], here are a couple of patches to drop
> node-local allocations during host contoller initialisation. This set
> covers both arm64 and x86.
>
> I'm posting early to give the patches time on the
On Tue, Aug 28, 2018 at 04:05:11PM +0100, Punit Agrawal wrote:
> Hi Bjorn,
>
> As discussed before[0], here are a couple of patches to drop
> node-local allocations during host contoller initialisation. This set
> covers both arm64 and x86.
>
> I'm posting early to give the patches time on the
> -Original Message-
> From: Borislav Petkov
> Sent: Tuesday, September 4, 2018 1:29 AM
> To: Fan Wu
> Cc: mche...@kernel.org; james.mo...@arm.com; baicar.ty...@gmail.com;
> linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org;
> -Original Message-
> From: Borislav Petkov
> Sent: Tuesday, September 4, 2018 1:29 AM
> To: Fan Wu
> Cc: mche...@kernel.org; james.mo...@arm.com; baicar.ty...@gmail.com;
> linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org;
On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote:
> On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa wrote:
> >
> > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote:
> > > +Cc Andrey Smirnov who made me aware of this issue.
> > >
> > > On Wed, Aug 22, 2018 at 04:48:21PM +0300,
On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote:
> On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa wrote:
> >
> > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote:
> > > +Cc Andrey Smirnov who made me aware of this issue.
> > >
> > > On Wed, Aug 22, 2018 at 04:48:21PM +0300,
Hi all,
On Mon, Aug 27, 2018 at 10:21:44AM +0200, Johan Hovold wrote:
> Several drivers currently use of_find_compatible_node() to lookup child
> nodes while failing to notice that the of_find_ functions search the
> entire tree depth-first (from a given start node) and therefore can
> match
Hi all,
On Mon, Aug 27, 2018 at 10:21:44AM +0200, Johan Hovold wrote:
> Several drivers currently use of_find_compatible_node() to lookup child
> nodes while failing to notice that the of_find_ functions search the
> entire tree depth-first (from a given start node) and therefore can
> match
On Thu, Aug 30, 2018 at 05:47:33PM -0700, Florian Fainelli wrote:
> On 08/27/2018 01:21 AM, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the mdio child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node
On Thu, Aug 30, 2018 at 05:47:33PM -0700, Florian Fainelli wrote:
> On 08/27/2018 01:21 AM, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the mdio child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node
Calling dmi_check_system() early only works on X86. Other
architectures initialize the DMI subsystem later so it's not
ready yet when ACPI itself gets initialized.
In the best case it results in a useless call to a function which
will do nothing. But depending on the dmi implementation, it could
Calling dmi_check_system() early only works on X86. Other
architectures initialize the DMI subsystem later so it's not
ready yet when ACPI itself gets initialized.
In the best case it results in a useless call to a function which
will do nothing. But depending on the dmi implementation, it could
On Mon, Aug 27, 2018 at 04:44:44PM +0200, Ulf Hansson wrote:
> On 27 August 2018 at 10:21, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the slot child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node
On Mon, Aug 27, 2018 at 04:44:44PM +0200, Ulf Hansson wrote:
> On 27 August 2018 at 10:21, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the slot child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node
On Mon, 3 Sep 2018 09:54:08 +
Prabhakar Kushwaha wrote:
> Dear Yogesh,
>
> > -Original Message-
> > From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Yogesh Gaur
> > Sent: Friday, August 31, 2018 4:00 PM
> > To: linux-...@lists.infradead.org;
Hi Stephen,
On Tue, 4 Sep 2018 09:19:50 +1000, Stephen Rothwell wrote:
> Today's linux-next merge of the dmi tree got a conflict in:
>
> drivers/acpi/bus.c
>
> between commit:
>
> ae976358cd7b ("Revert "ACPI / bus: Parse tables as term_list for Dell XPS
> 9570 and Precision M5530"")
>
>
On Mon, 3 Sep 2018 09:54:08 +
Prabhakar Kushwaha wrote:
> Dear Yogesh,
>
> > -Original Message-
> > From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Yogesh Gaur
> > Sent: Friday, August 31, 2018 4:00 PM
> > To: linux-...@lists.infradead.org;
Hi Stephen,
On Tue, 4 Sep 2018 09:19:50 +1000, Stephen Rothwell wrote:
> Today's linux-next merge of the dmi tree got a conflict in:
>
> drivers/acpi/bus.c
>
> between commit:
>
> ae976358cd7b ("Revert "ACPI / bus: Parse tables as term_list for Dell XPS
> 9570 and Precision M5530"")
>
>
The RISC-V local interrupt controller manages software interrupts,
timer interrupts, external interrupts (which are routed via the
platform level interrupt controller) and per-HART local interrupts.
This patch add a driver for RISC-V local interrupt controller. It's
a major re-write over
The RISC-V local interrupt controller manages software interrupts,
timer interrupts, external interrupts (which are routed via the
platform level interrupt controller) and per-HART local interrupts.
This patch add a driver for RISC-V local interrupt controller. It's
a major re-write over
The scause is already part of pt_regs so no need to pass
scause as separate arg to do_IRQ().
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 1 -
arch/riscv/kernel/irq.c | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S
This patchset provides a new RISC-V Local Interrupt Controller Driver
for managing per-CPU local interrupts. The overall approach is inspired
from the way per-CPU local interrupts are handled by Linux ARM64 and
ARM GICv3 driver.
Few advantages of having this new driver are as follows:
1. It
The mechanism to trigger IPI is generally part of interrupt-controller
driver for various architectures. On RISC-V, we have an option to trigger
IPI using SBI or SOC vendor can implement RISC-V CPU where IPI will be
triggered using SOC interrupt-controller (e.g. custom PLIC).
This patch makes IPI
This patch selects following GENERIC_IRQ kconfig options:
GENERIC_IRQ_MULTI_HANDLER
GENERIC_IRQ_PROBE
GENERIC_IRQ_SHOW_LEVEL
HANDLE_DOMAIN_IRQ
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
The scause is already part of pt_regs so no need to pass
scause as separate arg to do_IRQ().
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 1 -
arch/riscv/kernel/irq.c | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S
This patchset provides a new RISC-V Local Interrupt Controller Driver
for managing per-CPU local interrupts. The overall approach is inspired
from the way per-CPU local interrupts are handled by Linux ARM64 and
ARM GICv3 driver.
Few advantages of having this new driver are as follows:
1. It
The mechanism to trigger IPI is generally part of interrupt-controller
driver for various architectures. On RISC-V, we have an option to trigger
IPI using SBI or SOC vendor can implement RISC-V CPU where IPI will be
triggered using SOC interrupt-controller (e.g. custom PLIC).
This patch makes IPI
This patch selects following GENERIC_IRQ kconfig options:
GENERIC_IRQ_MULTI_HANDLER
GENERIC_IRQ_PROBE
GENERIC_IRQ_SHOW_LEVEL
HANDLE_DOMAIN_IRQ
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2 -
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2 -
On Tue, Sep 04, 2018 at 05:24:35PM +0530, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports
> multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs).
> PF0 is called administrative / admin function
On Tue, Sep 04, 2018 at 05:24:35PM +0530, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports
> multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs).
> PF0 is called administrative / admin function
On 2018/9/4 16:02, Borislav Petkov wrote:
shows only old mails so I'm going to assume this got fixed, finally! And
you probably have received a *fixed* BIOS even, allegedly.
So what's up?
I tested the function on Hygon Dhyana platforms with the latest BIOS,
found that this problem is indeed
On 2018/9/4 16:02, Borislav Petkov wrote:
shows only old mails so I'm going to assume this got fixed, finally! And
you probably have received a *fixed* BIOS even, allegedly.
So what's up?
I tested the function on Hygon Dhyana platforms with the latest BIOS,
found that this problem is indeed
Hi Yogesh,
On Fri, 31 Aug 2018 15:59:57 +0530
Yogesh Gaur wrote:
> - Add a driver for NXP FlexSPI host controller
>
> FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
> which supports two SPI channels and up to 4 external devices.
> Each channel supports
Hi Yogesh,
On Fri, 31 Aug 2018 15:59:57 +0530
Yogesh Gaur wrote:
> - Add a driver for NXP FlexSPI host controller
>
> FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
> which supports two SPI channels and up to 4 external devices.
> Each channel supports
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