On Fri, 2019-07-05 at 12:03 +0200, Miquel Raynal wrote:
> The extension is now .yaml instead of .txt.
>
> Fixes: 8122de54602e ("dt-bindings: Convert vendor prefixes to json-schema")
> Signed-off-by: Miquel Raynal
> ---
> scripts/checkpatch.pl | 2 +-
> 1 file changed, 1 insertion(+), 1
Hello,
Miquel Raynal wrote on Fri, 5 Jul 2019
12:03:45 +0200:
> The extension is now .yaml instead of .txt.
>
> Fixes: 8122de54602e ("dt-bindings: Convert vendor prefixes to json-schema")
> Signed-off-by: Miquel Raynal
> ---
I am one month too late, didn't saw it was fixed in linux-next (as
On Monday, July 1, 2019 3:58:27 PM CEST Geert Uytterhoeven wrote:
> "git diff" says:
>
> \ No newline at end of file
>
> after modifying the files.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> v2:
> - Split patches per maintainer.
> ---
> Documentation/ABI/testing/sysfs-power | 2 +-
>
On Thursday, July 4, 2019 10:01:20 AM CEST Mika Westerberg wrote:
> On Thu, Jul 04, 2019 at 01:05:38AM +0200, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > After recent hibernation-related changes, there are no more callers
> > of dev_pm_skip_next_resume_phases() except for the PM
The Mobiveil internal MSI controller requires separate target addresses,
one per MSI vector; this is clearly incompatible with the Multiple MSI
feature, which requires the same target address for all vectors
requested by an endpoint (ie the Message Address field in the MSI
Capability structure),
Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
is not used in current code, and "apb_csr" is not used by some platforms.
Signed-off-by: Hou Zhiqiang
Acked-by: Subrahmanya Lingappa
Acked-by: Rob Herring
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
Hi!
> > > > Also still relevant is whether the LED device is being correctly
> > > > modelled if the act of turning on the LED doesn't, in fact, turn the LED
> > > > on. Is it *really* a correct implementation of an LED device that
> > > > setting it to LED_FULL using sysfs doesn't cause it to
To make the register updating more readable, outstand the fields
to update by changing the register updating sequence to:
a. Read out the original value from the target register.
b. Update the value in one sentence.
c. Program the updated value back to the register.
Signed-off-by: Hou Zhiqiang
The inbound and outbound windows have completely separate control
registers sets in the host controller MMIO space. Windows control
register are accessed through an MMIO base address and an offset
that depends on the window index.
Since inbound and outbound windows control registers are
Fix up the Class Code field in PCI configuration space and set it to
PCI_CLASS_BRIDGE_PCI.
Move the Class Code fixup to function mobiveil_host_init() where
it belongs.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by:
Reformat the code to make it more readable. No functional
change intended.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Lorenzo Pieralisi
Reviewed-by: Minghuan Lian
---
V6:
- Splited from #2 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c | 208
The current code only setup the lower 32-bit CPU base address in
outbound window, it will result in outbound transactions drop on
64-bit platforms.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by:
The current code only setup the lower 32-bit PCI base address in
inbound window, it can result in inbound transactions drop on
64-bit platforms.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by:
The lower 10-bit of window size field is hardcode to zero,
and then the lower 10-bit of PAB_AXI_AMAP_CTRL register are
used to control fields, so mask out the lower 10-bit of
window size in case override the control bits.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by:
>From the function program_ob_windows(), remove the redundant read
operations to registers PAB_AXI_AMAP_AXI_WIN and PAB_AXI_AMAP_PEX_WIN_H,
and remove the useless definition of 'value'. Rename the parameter
'config_io_bit' to 'type' and then remove the definition of 'type'.
>From the function
Move the resource type check into a if..else block, and only
set up outbound window for MEM and IO resource. No functional
change.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
---
V6:
- Splited from #2 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c |
The current code has only statistic for outbound windows initialized,
but lack of inbound windows statistic. This patch is to add the
statistic for inbound windows initialized.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
- Splited from #9
In function program_ib_windows(), currently it use the parameter
'pci_addr' to initialize both CPU base address and PCI base address
of the inbound window, it is not correct, and another problem is
the upper 32-bit CPU address is not initialized. So, this patch
adds an new parameter 'u64 cpu_addr'
Current check for devfn number in mobiveil_pci_valid_device() is
wrong in that it flags as invalid functions present in PCI device 0
in the root bus while it is perfectly valid to access all functions
in PCI device 0 in the root bus.
Update the check in mobiveil_pci_valid_device() to fix the
The reset value of Primary, Secondary and Subordinate bus numbers is
zero which is a broken setup.
Program a sensible default value for Primary/Secondary/Subordinate
bus numbers.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Lorenzo Pieralisi
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya
Check window index from the parameter instead of the total
number of initialized windows to determine if the specified
window is valid.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya
In the loop block, there is not code to update the loop key,
this patch updates the loop key by re-read the INTx status
register.
Note: Need MV to test this fix.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
The current INTx process is clear all the recorded INTx after
each one of the recorded INTx handled, this can result in
potential INTx missing. This patch change it to only clear the
handled INTx status.
Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by:
Clear the target fields in the register before programming with
an new value.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
- Splited from #9 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c | 17
Move the PCIe PIO master enablement to function mobiveil_host_init().
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
- Splited from #9 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c |9 +
1 files
This patch set is to add fixes for Mobiveil PCIe Host driver.
Splited #2, #3, #9 and #10 of v5 patches.
Hou Zhiqiang (28):
PCI: mobiveil: Unify register accessors
PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
PCI: mobiveil: Fix PCI base address in MEM/IO outbound windows
PCI:
As the .map_bus() use the WIN_NUM_0 for CFG transactions,
it is appropriate to pass WIN_NUM_0 explicitly when initializing
the CFG outbound window rather than implicitly relying on the
ob_wins_configure counter.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Lorenzo Pieralisi
Reviewed-by: Minghuan
The memory of private structure has been allocated together with the
pci_host_bridge structure in function devm_pci_alloc_host_bridge().
So it is unnecessary to check the return value when get the private
structure pointer.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by:
The irq_set_chained_handler_and_data() call is not dependent on device
tree firmware so it should be moved out of the DT parsing function for
clarity.
Signed-off-by: Hou Zhiqiang
[lorenzo.pieral...@arm.com: rewritten commit log]
Signed-off-by: Lorenzo Pieralisi
Reviewed-by: Minghuan Lian
The host initializing sequence does not depend on PCIe link up,
so move it to the plac just before the enumeration.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
- Rebased the patch, no functional change.
The outbound memory windows PCI base addresses should be taken
from the 'ranges' property of DT node to setup MEM/IO outbound
windows decoding correctly instead of being hardcoded to zero.
Update the code to retrieve the PCI base address for each range
and use it to program the outbound windows
Code that executes the resource list traversal does not need to
delete any node therefore using the *_safe() API version is
useless.
Replace function resource_list_for_each_entry_safe() with the
resource_list_for_each_entry() counterpart.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Lorenzo
It is confusing to have two sets of functions to read/write
registers, some with csr_readl()/csr_writel(), while others with
read_paged_register()/write_paged_register().
In the register space the lower 3KB of 4KB PCIe configure space can be
accessed directly and higher 1KB through a simple
This patch modified the returned error number by convention.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Minghuan Lian
Reviewed-by: Subrahmanya Lingappa
---
V6:
- Splited from #3 of v5 patches, no functional change.
drivers/pci/controller/pcie-mobiveil.c |6 +++---
1 files changed, 3
The extension is now .yaml instead of .txt.
Fixes: 8122de54602e ("dt-bindings: Convert vendor prefixes to json-schema")
Signed-off-by: Miquel Raynal
---
scripts/checkpatch.pl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index
Commit 5e9dcb6188a4 ("powerpc/boot: Expose Kconfig symbols to wrapper")
was wrong, but commit e41b93a6be57 ("powerpc/boot: Fix build failures
with -j 1") was also wrong.
The correct dependency is:
$(obj)/serial.o: $(obj)/autoconf.h
However, I do not see the reason why we need to copy
The next commit will make the way of passing CONFIG options more robust.
Unfortunately, it would uncover another hidden issue; without this
commit, skiroot_defconfig would be broken like this:
| WRAParch/powerpc/boot/zImage.pseries
| arch/powerpc/boot/wrapper.a(decompress.o): In function
On Fri, Jul 5, 2019 at 11:37 AM Dmitry Vyukov wrote:
>
> On Fri, Jul 5, 2019 at 11:23 AM Rafael J. Wysocki wrote:
> >
> > On Thursday, July 4, 2019 7:27:04 PM CEST syzbot wrote:
> > > Hello,
> > >
> > > syzbot found the following crash on:
> > >
> > > HEAD commit:16c474c9 Add linux-next
On Thu, Jul 4, 2019 at 9:26 AM Michael Ellerman wrote:
>
> Masahiro Yamada writes:
>
> > Commit 5e9dcb6188a4 ("powerpc/boot: Expose Kconfig symbols to wrapper")
> > was wrong, but commit e41b93a6be57 ("powerpc/boot: Fix build failures
> > with -j 1") was also wrong.
> >
> > The correct
Not all Qualcomm platforms need to care about the speedbin efuse,
nor the value blown into the speedbin efuse.
Therefore, make the nvmem-cells and opp-supported-hw properties
optional.
Signed-off-by: Niklas Cassel
---
Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4
1 file
Add support for qcs404 on nvmem driver.
The qcs404 SoC has support for Core Power Reduction (CPR), which is
implemented as a power domain provider, therefore add optional support
in this driver to attach to a genpd power domain.
Co-developed-by: Jorge Ramirez-Ortiz
Signed-off-by: Jorge
The Thunderbolt controller is integrated into the Ice Lake CPU itself
and requires special flows to power it on and off using force power bit
in NHI VSEC registers. Runtime PM (RTD3) and Sx flows also differ from
the discrete solutions. Now the firmware notifies the driver whether
RTD3 entry or
Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).
Add CPR and populate OPP table.
Co-developed-by: Jorge Ramirez-Ortiz
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Niklas Cassel
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 145 +--
1 file changed, 137 insertions(+), 8 deletions(-)
diff --git
This is depends on the controller and on the platform/CPU we are
running. Move it to struct icm so we can set it per controller.
Signed-off-by: Mika Westerberg
---
drivers/thunderbolt/icm.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git
From: Jorge Ramirez-Ortiz
Add qcs404 to cpufreq-dt-platdev blacklist.
Signed-off-by: Jorge Ramirez-Ortiz
Co-developed-by: Niklas Cassel
Signed-off-by: Niklas Cassel
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Thunderbolt host routers may not always contain DROM that includes
device identification information. This is mostly needed for Ice Lake
systems but some Falcon Ridge controllers on PCs also do not have DROM.
In that case hide the identification attributes.
Signed-off-by: Mika Westerberg
---
Enable CONFIG_QCOM_CPR.
Signed-off-by: Niklas Cassel
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index bfadf18e71c2..d1e8ad5d3079 100644
--- a/arch/arm64/configs/defconfig
+++
There are two ways to mark a port as unimplemented. Typical way is to
return port type as TB_TYPE_INACTIVE when its config space is read.
Alternatively if the port is not physically present (such as ports 10
and 11 in ICL) reading from port config space returns
TB_CFG_ERROR_INVALID_CONFIG_SPACE
Ice Lake Thunderbolt controller includes two new device property
compatible properties that we need to be able to extract in the driver
so add them to the growing array of GUIDs.
Signed-off-by: Mika Westerberg
---
drivers/acpi/property.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Refactor the driver to make it easier to extend in a later commit.
Create a driver struct to collect all common resources, in order to make
it easier to free up all common resources.
Create a driver match_data struct to make it easier to extend the driver
with support for new features that might
CPR (Core Power Reduction) is a technology that reduces core power on a
CPU or other device. It reads voltage settings in efuse from product
test process as initial settings.
Each OPP corresponds to a "corner" that has a range of valid voltages
for a particular frequency. While the device is
Add qcom-opp bindings with properties needed for Core Power Reduction
(CPR).
CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and
msm8996. CPR was first introduced in msm8974.
Changes since RFC:
-Removed opp-hz. It is already an optional property in opp.txt
so no need to specify
Enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM.
Signed-off-by: Niklas Cassel
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d1e8ad5d3079..ae458572d9be 100644
--- a/arch/arm64/configs/defconfig
+++
Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs.
Changes since RFC:
-Make compatible string SoC specific.
-Changed interrupt definition.
-Use clock binding for reference clock.
-Clarified qcom,vdd-apc-step-up-limit description.
-Added missing properties.
-Updated the
The register access should be using 32-bit reads/writes according to the
datasheet. With the previous generation hardware 16-bit writes have been
working but starting with ICL this is not the case anymore so fix
producer/consumer register update to use correct width register address.
Ice Lake Thunderbolt controller NVM firmware is part of the BIOS image
which means it is not writable through the DMA port anymore. However, we
can still read it so we can keep nvm_version and active parts of NVM.
This way users still can find out the active NVM version and other
potentially
PCIe tunnel path indices got mixed up when we added support for tunnels
between switches that are not adjacent. This did not affect the
functionality as it is just an index but fix it now nevertheless to make
the code easier to understand.
Reported-by: Rajmohan Mani
Fixes: 8c7acaaf020f
Hi all,
With the exception of the first patch which is fix, this series enables
Thunderbolt on Intel Ice Lake. Biggest difference from the previous
controllers is that the Thunderbolt controller is now integrated as part of
the SoC. The firmware messages pretty much follow Titan Ridge but there
From: Sricharan R
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
From: Sricharan R
The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
This series adds support for Core Power Reduction (CPR), a form of
Adaptive Voltage Scaling (AVS), found on certain Qualcomm SoCs.
This series is based on top of the qcs404 cpufreq patch series that
hasn't landed yet:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=137809
CPR is
From: Colin Ian King
The variable val is being assigned with a value that is never
read and it is being updated later with a new value. The
assignment is redundant and can be removed. Also remove a
goto statement and a label and replace with a break statement.
Addresses-Coverity: ("Unused
On 05/07/19 11:40, Wanpeng Li wrote:
> From: Wanpeng Li
>
> Reset timer_advance_ns to the default value 1000ns after adaptive tuning
> goes insane which can happen sporadically in product environment.
>
> Cc: Paolo Bonzini
> Cc: Radim Krčmář
> Signed-off-by: Wanpeng Li
> ---
>
On Monday, July 1, 2019 6:20:17 PM CEST Mika Westerberg wrote:
> On Mon, Jul 01, 2019 at 12:42:14PM +0200, Rafael J. Wysocki wrote:
> > Hi All,
> >
> > This series of patches addresses a few issues related to the handling of
> > hibernation in the PCI bus type and the ACPI PM domain and ACPI LPSS
On Fri, Jul 05, 2019 at 09:48:50AM +0100, Jon Hunter wrote:
> Commit 5e5e9c23f82a ("PCI: tegra: Add support for GPIO based PERST#")
> calls the function devm_gpiod_get_from_of_node() to request a GPIO.
> Unfortunately, around the same time this was merged, commit 025bf37725f1
> ("gpio: Fix return
On Tuesday, June 25, 2019 4:11:16 PM CEST Mika Westerberg wrote:
> On Tue, Jun 25, 2019 at 02:04:45PM +0200, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > If the power state of a device with ACPI PM is changed from D3hot to
> > D3cold, it merely is a matter of dropping references
On Tuesday, June 25, 2019 6:09:18 PM CEST Mika Westerberg wrote:
> On Tue, Jun 25, 2019 at 02:09:12PM +0200, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > In pci_pm_complete() there are checks to decide whether or not to
> > resume devices that were left in runtime-suspend during
On Thursday, July 4, 2019 9:46:40 AM CEST Mika Westerberg wrote:
> On Thu, Jul 04, 2019 at 01:02:49AM +0200, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > Using acpi_device_get_power() outside of ACPI device initialization
> > and ACPI sysfs is problematic due to the way in which
On Tuesday, July 2, 2019 3:10:29 PM CEST Colin King wrote:
> From: Colin Ian King
>
> The pointer clk is being initialized with a value that is never
> read and it is being updated later with a new value. The
> initialization is redundant and can be removed.
>
> Addresses-Coverity: ("Unused
On Thursday, July 4, 2019 4:43:32 AM CEST Dexuan Cui wrote:
>
> With some upcoming patches to save/restore the Hyper-V drivers related
> states, a Linux VM running on Hyper-V will be able to hibernate. When
> a Linux VM hibernates, unluckily we must disable the memory hot-add/remove
> and balloon
From: Wanpeng Li
Reset timer_advance_ns to the default value 1000ns after adaptive tuning
goes insane which can happen sporadically in product environment.
Cc: Paolo Bonzini
Cc: Radim Kr??m
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/lapic.c | 2 +-
1 file changed, 1 insertion(+), 1
On Friday, July 5, 2019 9:02:01 AM CEST Kai-Heng Feng wrote:
> at 19:57, Bjorn Helgaas wrote:
>
> > On Mon, May 27, 2019 at 11:57:47AM -0500, Bjorn Helgaas wrote:
> >> On Thu, May 23, 2019 at 12:39:23PM +0800, Kai-Heng Feng wrote:
> >>> at 04:52, Bjorn Helgaas wrote:
> On Wed, May 22, 2019
When a pin is active-low, logical trigger edge should be inverted
to match the same interrupt opportunity.
For example, a button pushed trigger falling edge in ACTIVE_HIGH
case; in ACTIVE_LOW case, the button pushed trigger rising edge.
For user space the IRQ requesting doesn't need to do any
From: Colin Ian King
The variable ret is being assigned with a value that is never
read and it is being updated later with a new value. The
assignment is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/power/supply/isp1704_charger.c
On Fri, Jul 5, 2019 at 11:23 AM Rafael J. Wysocki wrote:
>
> On Thursday, July 4, 2019 7:27:04 PM CEST syzbot wrote:
> > Hello,
> >
> > syzbot found the following crash on:
> >
> > HEAD commit:16c474c9 Add linux-next specific files for 20190704
> > git tree: linux-next
> > console
czw., 4 lip 2019 o 17:38 Sebastian Andrzej Siewior
napisał(a):
>
> For spinlocks the type spinlock_t should be used instead of "struct
> spinlock".
>
> Use spinlock_t for spinlock's definition.
>
> Cc: Linus Walleij
> Cc: Bartosz Golaszewski
> Cc: linux-g...@vger.kernel.org
> Signed-off-by:
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
pt., 5 lip 2019 o 11:30 Michael Wu napisał(a):
>
> When a pin is active-low, logical trigger edge should be inverted
> to match the same interrupt opportunity.
>
> For example, a button pushed trigger falling edge in ACTIVE_HIGH
> case; in ACTIVE_LOW case, the button pushed trigger rising edge.
>
On Fri, 5 Jul 2019 at 10:49, Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the akpm-current tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> In file included from include/linux/compiler.h:257,
> from arch/arm/kernel/asm-offsets.c:10:
>
On Thursday, July 4, 2019 7:27:04 PM CEST syzbot wrote:
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:16c474c9 Add linux-next specific files for 20190704
> git tree: linux-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=17f8b463a0
> kernel
> On Fri, Jul 05, 2019 at 01:33:49AM -0700, jeyentam wrote:
> > Add support for NI-Serial PXIe-RS232, PXI-RS485 and PXIe-RS485 devices.
> >
> > Signed-off-by: Je Yen Tam
> > ---
> > drivers/tty/serial/8250/8250_pci.c | 298 -
> > 1 file changed, 294 insertions(+), 4
Luke Nelson writes:
> commit 66d0d5a854a6 ("riscv: bpf: eliminate zero extension code-gen")
> added the new zero-extension optimization for some BPF ALU operations.
>
> Since then, bugs in the JIT that have been fixed in the bpf tree require
> this optimization to be added to other operations:
Hi Laurent,
On Fri, Jul 05, 2019 at 11:04:24AM +0300, Laurent Pinchart wrote:
...
> > A reasonable compromise would be to add a Kconfig option that allows
> > enabling MC. This way you can provide backwards compatibility and allow
> > making use of the full potential of the hardware. That's
On Fri 05-07-19 11:42:41, Anshuman Khandual wrote:
> unset_migratetype_isolate() already validates under zone lock that a given
> page has already been isolated as MIGRATE_ISOLATE. There is no need for
> another check before. Hence just drop this redundant validation.
unset_migratetype_isolate
Similar to commit 6ada1fc0e1c4
("time: settimeofday: Validate the values of tv from user"),
an unvalidated user input is multiplied by a constant, which can result
in an undefined behaviour for large values. While this is validated
later, we should avoid triggering undefined behaviour.
Hi Andrew,
On Fri, 5 Jul 2019 at 07:49, Andrew Lunn wrote:
>
> Hi Vladimir
>
> > - DSA is typically used for discrete switches, switchdev is typically
> > used for embedded ones.
>
> Typically DSA is for discrete switches, but not exclusively. The
> b53/SF2 is embedded in a number of Broadcom
On Thu, Jul 04, 2019 at 09:41:04PM -0400, Alan Stern wrote:
> On Fri, 5 Jul 2019, Suwan Kim wrote:
>
> > On Mon, Jun 24, 2019 at 01:24:15PM -0400, Alan Stern wrote:
> > > On Mon, 24 Jun 2019, Suwan Kim wrote:
> > >
> > > > > > + hcd->self.sg_tablesize = ~0;
> > > > > > +
The np variable is still being used after the of_node_put() call,
which may result in use-after-free.
We fix this issue by calling of_node_put() after the last usage.
Fixes: 3eb906c6b6c1 ("powerpc: Make cpu_to_chip_id() available when SMP=n")
Signed-off-by: Wen Yang
Cc: Benjamin Herrenschmidt
There is a possible use-after-free issue in the fixup_port_irq():
460 static void __init fixup_port_irq(int index,
461 struct device_node *np,
462 struct plat_serial8250_port *port)
463 {
...
469 if (!virq &&
Den 05.07.2019 04:19, skrev Parav Pandit:
On Fri, Jun 28, 2019 at 2:20 PM Dag Moxnes wrote:
Use neighbour lock when copying MAC address from neighbour data struct
in dst_fetch_ha.
When not using the lock, it is possible for the function to race with
neigh_update, causing it to copy an
On Fri, Jul 05, 2019 at 01:33:49AM -0700, jeyentam wrote:
> Add support for NI-Serial PXIe-RS232, PXI-RS485 and PXIe-RS485 devices.
>
> Signed-off-by: Je Yen Tam
> ---
> drivers/tty/serial/8250/8250_pci.c | 298 -
> 1 file changed, 294 insertions(+), 4 deletions(-)
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's src driver, add "fsl,imx8mq-src" as
src's fallback compatible to enable it.
Signed-off-by: Anson Huang
Reviewed-by: Philipp Zabel
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Anson Huang
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible
property and related info to support i.MX8MM.
Signed-off-by: Anson Huang
---
Changes since V3:
- Add comments to those reset indices to indicate which are NOT
supported on i.MX8MM.
---
The np variable is still being used after the of_node_put() call,
which may result in use-after-free.
We fix this issue by calling of_node_put() after the last usage.
This patatch also do some cleanup.
Fixes: fd066e850351 ("powerpc/mpc8308: fix USB DR controller initialization")
Signed-off-by:
Eric Biggers wrote:
> Also, since the case of a fd with an internal mount was overlooked, probably
> the man page needs to be updated clarify that move_mount(2) fails with
> EINVAL in this case. Where is the man page?
See below. I'm in the middle of updating the manpages I need to push.
Linus, Vasily, for your attention in the next merge window. (I would suggest to
apply
belows fixup during the merge of whatever tree is merged 2nd).
There is now a build conflict between the s390/features branch and the
driver-core/driver-core-next
especially between
commit 92ce7e83b4e5
On Thu, Jul 4, 2019 at 8:18 PM Ard Biesheuvel wrote:
> On Thu, 4 Jul 2019 at 09:52, Linus Walleij wrote:
> >
> > On Wed, Jul 3, 2019 at 3:50 PM Marc Zyngier wrote:
> > > On 03/07/2019 13:26, Linus Walleij wrote:
> > > > On Wed, Jul 3, 2019 at 11:24 AM tip-bot for Ard Biesheuvel
> > > > wrote:
This test relies on the fact that the PMU registers are accessible
from userspace. It then uses the perf_event_mmap_page to retrieve
the counter index and access the underlying register.
This test uses sched_setaffinity(2) in order to run on all CPU and thus
check the behaviour of the PMU of all
Keep track of event opened with direct access to the hardware counters
and modify permissions while they are open.
The strategy used here is the same which x86 uses: everytime an event
is mapped, the permissions are set if required. The atomic field added
in the mm_context helps keep track of the
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