The following commit has been merged into the core/rcu branch of tip:
Commit-ID: d97addc419e2b1cc1aba2ccc679373fbff7f2521
Gitweb:
https://git.kernel.org/tip/d97addc419e2b1cc1aba2ccc679373fbff7f2521
Author:Paul E. McKenney
AuthorDate:Wed, 25 Nov 2020 20:49:57 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 8847bd4988321cbc66c94e9dfb05b401c50378a3
Gitweb:
https://git.kernel.org/tip/8847bd4988321cbc66c94e9dfb05b401c50378a3
Author:Paul E. McKenney
AuthorDate:Fri, 27 Nov 2020 08:31:39 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: c679d90b21b76319b4a6c719442b6a1ff124b88d
Gitweb:
https://git.kernel.org/tip/c679d90b21b76319b4a6c719442b6a1ff124b88d
Author:Paul E. McKenney
AuthorDate:Thu, 26 Nov 2020 13:29:24 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: c66c0f94b345600aea881f6c4a1dac0ff5dd1aa8
Gitweb:
https://git.kernel.org/tip/c66c0f94b345600aea881f6c4a1dac0ff5dd1aa8
Author:Paul E. McKenney
AuthorDate:Fri, 27 Nov 2020 09:04:22 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 18fbf307b7319af3725c36e16af6ae9f35a8699c
Gitweb:
https://git.kernel.org/tip/18fbf307b7319af3725c36e16af6ae9f35a8699c
Author:Paul E. McKenney
AuthorDate:Mon, 16 Nov 2020 16:46:06 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: e3e1a99787fcf6297990c3b6cf53f5f6ef5aed60
Gitweb:
https://git.kernel.org/tip/e3e1a99787fcf6297990c3b6cf53f5f6ef5aed60
Author:Paul E. McKenney
AuthorDate:Fri, 11 Dec 2020 14:03:39 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: ea31fd9ca87399ac4e03cd6c215451fa7dc366e4
Gitweb:
https://git.kernel.org/tip/ea31fd9ca87399ac4e03cd6c215451fa7dc366e4
Author:Paul E. McKenney
AuthorDate:Tue, 17 Nov 2020 11:32:54 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 0b962c8fe0e5c72a252b236814a6b6e9df799061
Gitweb:
https://git.kernel.org/tip/0b962c8fe0e5c72a252b236814a6b6e9df799061
Author:Paul E. McKenney
AuthorDate:Sat, 19 Dec 2020 07:05:58 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 8a67a20bf257ca378d6e5588fbe4382966395ac8
Gitweb:
https://git.kernel.org/tip/8a67a20bf257ca378d6e5588fbe4382966395ac8
Author:Paul E. McKenney
AuthorDate:Wed, 25 Nov 2020 13:00:04 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 1afb95fee0342b8d9e05b0433e8e44a6dfd7c4a3
Gitweb:
https://git.kernel.org/tip/1afb95fee0342b8d9e05b0433e8e44a6dfd7c4a3
Author:Paul E. McKenney
AuthorDate:Sat, 19 Dec 2020 07:34:35 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: d945f797e483979bdeded76266c366f35929afb8
Gitweb:
https://git.kernel.org/tip/d945f797e483979bdeded76266c366f35929afb8
Author:Paul E. McKenney
AuthorDate:Fri, 25 Dec 2020 07:40:48 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: c261145abd2461f921ac44ad70c28778dda710f4
Gitweb:
https://git.kernel.org/tip/c261145abd2461f921ac44ad70c28778dda710f4
Author:Willy Tarreau
AuthorDate:Thu, 21 Jan 2021 08:20:23 +01:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: be60ca41fbaa93bc8f92b24e34d8cc62af41300d
Gitweb:
https://git.kernel.org/tip/be60ca41fbaa93bc8f92b24e34d8cc62af41300d
Author:Willy Tarreau
AuthorDate:Thu, 21 Jan 2021 08:20:26 +01:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 5b1c827ca3b349801e2faff4185118cfa74f94c6
Gitweb:
https://git.kernel.org/tip/5b1c827ca3b349801e2faff4185118cfa74f94c6
Author:Willy Tarreau
AuthorDate:Thu, 21 Jan 2021 08:20:27 +01:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: edf7b8417834c89d00ef88355ea507b0b0a630ae
Gitweb:
https://git.kernel.org/tip/edf7b8417834c89d00ef88355ea507b0b0a630ae
Author:Paul E. McKenney
AuthorDate:Wed, 02 Dec 2020 17:52:07 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 3c6ce7a5363723a05bfe3ee03a8d4a9b66841ae4
Gitweb:
https://git.kernel.org/tip/3c6ce7a5363723a05bfe3ee03a8d4a9b66841ae4
Author:Willy Tarreau
AuthorDate:Thu, 21 Jan 2021 08:20:31 +01:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 26cec81415b1b2a2e8e36ef0b24cf5f26467aa61
Gitweb:
https://git.kernel.org/tip/26cec81415b1b2a2e8e36ef0b24cf5f26467aa61
Author:Willy Tarreau
AuthorDate:Thu, 21 Jan 2021 08:48:08 +01:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 98f180837a896ecedf8f7e12af22b57f271d43c9
Gitweb:
https://git.kernel.org/tip/98f180837a896ecedf8f7e12af22b57f271d43c9
Author:Paul E. McKenney
AuthorDate:Tue, 08 Dec 2020 16:13:57 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: 3375efeddf6972df47df26a5b5c643189bd3c02a
Gitweb:
https://git.kernel.org/tip/3375efeddf6972df47df26a5b5c643189bd3c02a
Author:Paul E. McKenney
AuthorDate:Tue, 08 Dec 2020 14:43:43 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: b70fa3b12fc8d2b870d1ac7fd44da89271eb8705
Gitweb:
https://git.kernel.org/tip/b70fa3b12fc8d2b870d1ac7fd44da89271eb8705
Author:Paul E. McKenney
AuthorDate:Tue, 08 Dec 2020 15:26:22 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: b4b7914a6a73fc169fd1ce2fcd78a1d83d9528a9
Gitweb:
https://git.kernel.org/tip/b4b7914a6a73fc169fd1ce2fcd78a1d83d9528a9
Author:Paul E. McKenney
AuthorDate:Tue, 08 Dec 2020 13:45:49 -08:00
The following commit has been merged into the core/rcu branch of tip:
Commit-ID: bd34dcd4120d7e358baac9c22ef1321bd0c22079
Gitweb:
https://git.kernel.org/tip/bd34dcd4120d7e358baac9c22ef1321bd0c22079
Author:Paul E. McKenney
AuthorDate:Wed, 09 Dec 2020 15:15:27 -08:00
On Fri, Feb 12, 2021 at 11:30:41AM +, Steven Price wrote:
> On 11/02/2021 20:21, sonicadvan...@gmail.com wrote:
> > Why do we need compatibility layers?
> > There are ARMv8 CPUs that only support AArch64 but still need to run
> > AArch32 applications.
> > Cortex-A34/R82 and other cores are
Em Wed, Feb 10, 2021 at 02:18:02PM -0500, Nicholas Fraser escreveu:
> The first time dso__load() was called on a PE file it always returned -1
> error. This caused the first call to map__find_symbol() to always fail
> on a PE file so the first sample from each PE file always had symbol
> .
On Thu, Feb 11, 2021 at 07:08:20PM +0100, Nicolas Saenz Julienne wrote:
> - if (xfer->tx_buf || xfer->rx_buf) {
> + if ((xfer->tx_buf || xfer->rx_buf) && xfer->len) {
I think the issue here is more that some users were passing in buffers
with zero length transfers, the
* Paul E. McKenney wrote:
> Hello, Ingo!
>
> This pull request contains changes for RCU, KCSAN, LKMM, and nolibc.
> You can pull the entire group using branch for-mingo. Or, if you prefer,
> you can pull them separately, using for-mingo-rcu to pull the RCU changes,
> for-mingo-kcsan to pull
On Fri, Feb 12, 2021 at 12:00:15PM +, Lorenzo Pieralisi wrote:
> On Thu, Feb 11, 2021 at 03:33:52PM +, Vincenzo Frascino wrote:
> > When MTE async mode is enabled TFSR_EL1 contains the accumulative
> > asynchronous tag check faults for EL1 and EL0.
> >
> > During the suspend/resume
On Fri 12-02-21 12:22:07, Matthew Wilcox wrote:
> On Fri, Feb 12, 2021 at 08:18:11PM +0900, Tetsuo Handa wrote:
> > On 2021/02/12 1:41, Michal Hocko wrote:
> > > But I suspect we have drifted away from the original issue. I thought
> > > that a simple check would help us narrow down this
Em Wed, Feb 10, 2021 at 02:17:49PM -0500, Nicholas Fraser escreveu:
> A non-existent build-id used to be treated as all-zero SHA-1 hash.
> Build-ids are now variable width. A non-existent build-id is an empty
> string and "perf buildid-list" pads this with spaces.
>
> This fixes "perf-archive" to
On Fri, Feb 12, 2021 at 03:31:42PM +1100, Stephen Rothwell wrote:
> BTW Mark: the author's address in 258ea99fe25a uses a non existent domain :-(
Ugh, I think that's something gone wrong with b4 :( A bit late now to
try to fix it up.
signature.asc
Description: PGP signature
Em Wed, Feb 10, 2021 at 02:17:38PM -0500, Nicholas Fraser escreveu:
> dso__load_bfd_symbols() attempts to load a DSO at its original path,
> then closes it and loads the file in the debug cache. This is incorrect.
> It should ignore the original file and work with only the debug cache.
> The
a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Mihai-Carabas/misc-pvpanic-split-up-generic-and-platform-dependent-code/20210212-181711
base: https://git.kernel.org/pub/scm
On Thu, Jan 28, 2021 at 05:21:36PM -0300, Marcelo Tosatti wrote:
> Rather than waking up all nohz_full CPUs on the system, only wakeup
> the target CPUs of member threads of the signal.
>
> Reduces interruptions to nohz_full CPUs.
>
> Signed-off-by: Marcelo Tosatti
>
> Index:
On Thu, 2021-02-11 at 14:56 -0500, Steven Rostedt wrote:
> On Thu, 11 Feb 2021 17:17:42 +0100
> Viktor Rosendahl wrote:
>
> > It seems to work but I discovered during testing that it seems like newer
> > kernels have a tendency to lose some latencies in longer bursts. I guess
> > this
> > is
On Fri, Feb 12, 2021 at 03:05:29AM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> In preparation of offloading the bridge port flags which have
> independent settings for unknown multicast and for broadcast, we should
> also start reserving one destination Port Group ID for the
Code at line 967 implies that rsp->fwdata.supported_fec may be up to 4:
967: if (rsp->fwdata.supported_fec <= FEC_MAX_INDEX)
If rsp->fwdata.supported_fec evaluates to 4, then there is an
out-of-bounds read at line 971 because fec is an array with
a maximum of 4 elements:
954 const int
On Fri, Feb 12, 2021 at 08:18:11PM +0900, Tetsuo Handa wrote:
> On 2021/02/12 1:41, Michal Hocko wrote:
> > But I suspect we have drifted away from the original issue. I thought
> > that a simple check would help us narrow down this particular case and
> > somebody messing up from the IRQ context
On Thu, Feb 11, 2021 at 11:34:21AM +0100, Ahmad Fatoum wrote:
> Hello Jarkko,
>
> On 10.02.21 18:00, Jarkko Sakkinen wrote:
> > On Tue, Nov 03, 2020 at 09:31:43PM +0530, Sumit Garg wrote:
> >> + case Opt_new:
> >> + key_len = payload->key_len;
> >> + ret =
On Tue, 9 Feb 2021 at 20:09, wrote:
>
> From: Roman Kiryanov
>
> Android Studio Emulator no longer uses
> this driver.
>
> Signed-off-by: Roman Kiryanov
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/Kconfig| 7 -
> drivers/mmc/host/Makefile |
On Mon, 8 Feb 2021 at 10:52, Jiapeng Chong
wrote:
>
> Fix the following coccicheck warning:
>
> ./drivers/mmc/host/omap_hsmmc.c:297:6-25: WARNING: Comparison of 0/1 to
> bool variable.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
I already have a patch for this:
On Tue, 9 Feb 2021 at 15:52, wrote:
>
> From: Yann Gautier
>
> Since [1], the erase argument for mmc_erase() function is saved in
> erase_arg field of card structure. It is preferable to use it instead of
> hard-coded MMC_SECURE_ERASE_ARG, which from eMMC 4.51 spec is not
> recommended:
>
The LSI/CSI LS7266R1 chip provides programmable output via the FLG pins.
When interrupts are enabled on the ACCES 104-QUAD-8, they occur whenever
FLG1 is active. Four functions are available for the FLG1 signal: Carry,
Compare, Carry-Borrow, and Index.
Carry:
Interrupt
On Mon, Feb 08, 2021 at 05:09:21PM -0700, Shuah Khan wrote:
> On 2/2/21 3:02 PM, Jarkko Sakkinen wrote:
> > On Mon, Feb 01, 2021 at 09:26:49PM +0800, Tianjia Zhang wrote:
> > > Simplify the sgx code implemntation by using library function
> > > getauxval() instead of a custom function to get the
On Thu, Feb 11, 2021 at 02:04:12PM +0800, Tianjia Zhang wrote:
> Hi,
>
> Sorry for the late reply.
>
> On 1/28/21 1:40 AM, Jarkko Sakkinen wrote:
> > I could bet some money that this does not bring any significant
> > performance gain.
> >
>
> Yes, this does not bring performance gains. This
On Fri, Feb 12, 2021 at 12:05:14PM +, Luis Henriques wrote:
> Greg KH writes:
>
> > On Fri, Feb 12, 2021 at 10:22:16AM +0200, Amir Goldstein wrote:
> >> On Fri, Feb 12, 2021 at 9:49 AM Greg KH wrote:
> >> >
> >> > On Fri, Feb 12, 2021 at 12:44:00PM +0800, Nicolas Boichat wrote:
> >> > >
This patch introduces a character device interface for the Counter
subsystem. Device data is exposed through standard character device read
operations. Device data is gathered when a Counter event is pushed by
the respective Counter device driver. Configuration is handled via ioctl
operations on
This patch replaces the mutex I/O lock with a spinlock. This is in
preparation for a subsequent patch adding IRQ support for 104-QUAD-8
devices; we can't sleep in an interrupt context, so we'll need to use a
spinlock instead.
Cc: Syed Nayyar Waris
Signed-off-by: William Breathitt Gray
---
The events_queue_size sysfs attribute provides a way for users to
dynamically configure the Counter events queue size for the Counter
character device interface. The size is in number of struct
counter_event data structures. The number of elements will be rounded-up
to a power of 2 due to a
The Generic Counter chrdev interface expects users to supply extension
IDs in order to select extensions for requests. In order for users to
know what extension ID belongs to which extension this information must
be exposed. The extension*_name attribute provides a way for users to
discover what
This patch adds high-level documentation about the Counter subsystem
character device interface.
Signed-off-by: William Breathitt Gray
---
Documentation/driver-api/generic-counter.rst | 243 +++---
.../userspace-api/ioctl/ioctl-number.rst | 1 +
2 files changed, 203
This is in preparation for a subsequent patch implementing a character
device interface for the Counter subsystem.
Signed-off-by: William Breathitt Gray
---
MAINTAINERS | 1 +
include/linux/counter.h | 42 +--
include/uapi/linux/counter.h | 56
The Counter subsystem architecture and driver implementations have
changed in order to handle Counter sysfs interactions in a more
consistent way. This patch updates the Generic Counter interface
documentation to reflect the changes.
Signed-off-by: William Breathitt Gray
---
The Counter subsystem architecture and driver implementations have
changed in order to handle Counter sysfs interactions in a more
consistent way. This patch updates the Generic Counter interface
header file comments to reflect the changes.
Signed-off-by: William Breathitt Gray
---
Signal values will always be levels so let's be explicit it about it to
make the intent of the code clear.
Cc: Syed Nayyar Waris
Cc: Kamel Bouhara
Signed-off-by: William Breathitt Gray
---
drivers/counter/104-quad-8.c| 5 +++--
drivers/counter/counter.c | 12
The phrase "Counter Count function" is verbose and unintentionally
implies that function is a Count extension. This patch adjusts the
Counter subsystem code to use the more direct "Counter function" phrase
to make the intent of this code clearer. The phrase "Count action" is
adjusted herein as
ERANGE is a semantically better error code to return when an argument
value falls outside the supported limit range of a device.
Cc: Syed Nayyar Waris
Cc: Fabrice Gasnier
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Signed-off-by: William Breathitt Gray
---
drivers/counter/104-quad-8.c|
Only a select set of modes (function, action, etc.) are valid for a
given device configuration. This patch ensures that invalid modes result
in a return -EINVAL. Such a situation should never occur in reality, but
it's good to define a default switch cases for the sake of making the
intent of the
The struct counter_synapse actions_list member expects a const enum
counter_synapse_action array. This patch adds the const qualifier to the
quad8_index_actions_list and quad8_synapse_actions_list to match
actions_list.
Cc: Syed Nayyar Waris
Signed-off-by: William Breathitt Gray
---
The struct counter_synapse actions_list member expects a const enum
counter_synapse_action array. This patch adds the const qualifier to the
ftm_quaddec_synapse_actions to match actions_list.
Cc: Patrick Havelange
Signed-off-by: William Breathitt Gray
---
drivers/counter/ftm-quaddec.c | 2 +-
The struct counter_count functions_list member expects a const enum
counter_count_function array. This patch adds the const qualifier to the
quad8_functions_list to match functions_list.
Cc: Syed Nayyar Waris
Signed-off-by: William Breathitt Gray
---
drivers/counter/104-quad-8.c | 2 +-
1 file
The 104-QUAD-8 only has two count modes where a ceiling value makes
sense: Range Limit and Modulo-N. Outside of these two modes, setting a
ceiling value is an invalid operation -- so let's report it as such by
returning -EINVAL.
Fixes: fc069262261c ("counter: 104-quad-8: Add lock guards - generic
Add some safety by qualifying the quad8_preset_register_set() function
parameters as const.
Cc: Syed Nayyar Waris
Signed-off-by: William Breathitt Gray
---
drivers/counter/104-quad-8.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/counter/104-quad-8.c
When the kernel is running in secure boot mode, we lock down the kernel to
prevent userspace from modifying the running kernel image. Whilst this
includes prohibiting access to things like /dev/mem, it must also prevent
access by means of configuring driver modules in such a way as to cause a
"Miscellaneous" is the correct spelling.
Signed-off-by: William Breathitt Gray
---
Documentation/driver-api/generic-counter.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/driver-api/generic-counter.rst
b/Documentation/driver-api/generic-counter.rst
index
Duplicate ABIs are not valid, so let's consolidate these sysfs
attributes into the main sysfs-bus-counter documentation file.
Cc: Patrick Havelange
Signed-off-by: William Breathitt Gray
---
Documentation/ABI/testing/sysfs-bus-counter | 76 ++-
Changes in v8:
- Consolidated Counter sysfs ABI documentation to single file
- Added events_queue_size sysfs attribute to allow users to dynamically
resize the events queue
- Fixed markup syntax and typos in generic-counter.rst
- Improved documentation in include/uapi/linux/counter.h and
Adding documentation and dt-bindings file which contains MIO pin
configuration defines for Xilinx ZynqMP pinctrl driver.
Signed-off-by: Sai Krishna Potthuri
---
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 339 ++
include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 +
2 files
Hi,
On Thu, Feb 11, 2021 at 04:02:55PM -0500, Steve Grubb wrote:
> On Thursday, February 11, 2021 11:29:34 AM EST Paul Moore wrote:
> > > If I'm not mistaken, iptables emits a single audit log per table, ipset
> > > doesn't support audit at all. So I wonder how much audit logging is
> > >
Adding pinctrl driver for Xilinx ZynqMP platform.
This driver queries pin information from firmware and registers
pin control accordingly.
Signed-off-by: Sai Krishna Potthuri
---
drivers/pinctrl/Kconfig | 13 +
drivers/pinctrl/Makefile |1 +
Adding pinctrl support to query platform specific information (pins)
from firmware.
Signed-off-by: Sai Krishna Potthuri
Acked-by: Michal Simek
---
drivers/firmware/xilinx/zynqmp.c | 114 +++
include/linux/firmware/xlnx-zynqmp.h | 90 +
2 files
Add support for Xilinx ZynqMP pinctrl driver and also update the
Xilinx firmware driver to support pinctrl functionality.
This driver queries the pin information from the firmware and
allow configuring the pins as per the request.
changes in v3:
- Fixed binding doc comments from Rob.
- Used
On Fri 2021-02-12 13:28:56, Sakari Ailus wrote:
> On Thu, Feb 11, 2021 at 06:14:28PM +0100, Petr Mladek wrote:
> > On Tue 2021-02-09 19:47:55, Sakari Ailus wrote:
> > > Hi Andy,
> > >
> > > On Tue, Feb 09, 2021 at 11:58:40AM +0200, Andy Shevchenko wrote:
> > > > On Tue, Feb 09, 2021 at 11:20:32AM
On Wed, Feb 10, 2021 at 02:16:10PM +0530, Bhaskar Chowdhury wrote:
>
>
> s/postive/positive/
A bit more verbose, please, e.g.:
"Fix spelling error in arch/x86/entry/vdso/vsgx.S: postive -> positive."
> Signed-off-by: Bhaskar Chowdhury
> ---
> arch/x86/entry/vdso/vsgx.S | 2 +-
> 1 file
This is useful to debug DP negotiation and pin assignment even
when the firmware does all the work.
Signed-off-by: Guido Günther
---
drivers/usb/typec/tps6598x.c | 12 ++-
drivers/usb/typec/tps6598x.h | 36
drivers/usb/typec/tps6598x_trace.h | 54
This allows to trace status information which helps to debug problems
with role switching, etc.
Signed-off-by: Guido Günther
---
drivers/usb/typec/tps6598x.c | 26 -
drivers/usb/typec/tps6598x.h | 66 +
drivers/usb/typec/tps6598x_trace.h | 94
Allow to get irq event information via the tracing framework. This
allows to inspect USB-C negotiation at runtime.
Signed-off-by: Guido Günther
---
drivers/usb/typec/Makefile | 3 +
drivers/usb/typec/tps6598x.c | 9 ++-
drivers/usb/typec/tps6598x.h | 64
This series adds tracing events for the chips IRQ and registers that are useful
to figure out the current data and power status. This came about since
diagnosing why a certain usb-c hub or dp-alt-mode adapter fails is hard with
the information in /sys/class/typec alone since this does not have a
Together with the PD status register this is vital for debugging power
negotiations at runtime.
Signed-off-by: Guido Günther
---
drivers/usb/typec/tps6598x.c | 19 +--
drivers/usb/typec/tps6598x.h | 19 +++
drivers/usb/typec/tps6598x_trace.h | 38
Greg KH writes:
> On Fri, Feb 12, 2021 at 10:22:16AM +0200, Amir Goldstein wrote:
>> On Fri, Feb 12, 2021 at 9:49 AM Greg KH wrote:
>> >
>> > On Fri, Feb 12, 2021 at 12:44:00PM +0800, Nicolas Boichat wrote:
>> > > Filesystems such as procfs and sysfs generate their content at
>> > > runtime.
On Thu, Feb 11, 2021 at 03:33:52PM +, Vincenzo Frascino wrote:
> When MTE async mode is enabled TFSR_EL1 contains the accumulative
> asynchronous tag check faults for EL1 and EL0.
>
> During the suspend/resume operations the firmware might perform some
> operations that could change the state
On 12.02.21 10:58, Linus Walleij wrote:
Hi,
I think Intel people often take the stance that the ACPI DSDT (or whatever)
needs to be fixed.
It should, actually board/firmware vendors should think more carefully
and do it right in the first place. But reality is different. And
firmware upgrade
Now that we have GCC define, use the enums instead of numbers in the DTS
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 91 ++--
1 file changed, 46 insertions(+), 45 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
This enabled the four remoteprocs found in SM8350, audio, compute, modem
and sensor for MTP platform and adds firmware for them.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 20
1 file changed, 20 insertions(+)
diff --git
Add remoteproc nodes for the audio, compute and sensor cores, define
glink for each one.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 158 +++
1 file changed, 158 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
SMP2P is used for interrupting and being interrupted about remoteproc
state changes related to the audio, compute, modem and sensor subsystems.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 96
1 file changed, 96 insertions(+)
diff --git
Add HID subsystem (TC=0x15) devices. These devices need to be registered
for 7th-generation Surface models. On previous generations, these
devices are either provided as platform devices via ACPI (Surface Laptop
1 and 2) or implemented as standard USB device.
Signed-off-by: Maximilian Luz
---
Add the rmtfs as a reserved memory node.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0bf5cec3a2aa..faa0d0a716e6 100644
---
Add the detachment system (DTX) SSAM device for the Surface Book 3. This
device is accessible under the base (TC=0x11) subsystem.
Signed-off-by: Maximilian Luz
---
drivers/platform/surface/surface_aggregator_registry.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
This adds RPMH power domain found in SM8350 SoC
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 49
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index
Fix the typo s/Limaited/Limited
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 188f4011352c..b53744618102 100644
---
This series fixes a typo, adds remoteproc nodes and enables them for MTP and
uses enums for GCC
This is v5.13 material and dependent on 20210204170907.63545-1-vk...@kernel.org
Vinod Koul (7):
arm64: dts: qcom: sm8350: fix typo
arm64: dts: qcom: sm8350: Add rpmhpd node
arm64: dts: qcom:
Add the SSAM platform profile device to the SSAM device registry. This
device is accessible under the thermal subsystem (TC=0x03) and needs to
be registered for all Surface models.
Signed-off-by: Maximilian Luz
---
.../surface/surface_aggregator_registry.c | 15 +++
1 file
Add battery subsystem (TC=0x02) devices (battery and AC) to the SSAM
device registry. These devices need to be registered for 7th-generation
Surface models. On 5th- and 6th-generation models, these devices are
handled via the standard ACPI battery/AC interface, which in turn
accesses the same SSAM
The Surface Book 3 has a detachable base part. While the top part
(so-called clipboard) contains the CPU, touchscreen, and primary
battery, the base contains, among other things, a keyboard, touchpad,
and secondary battery.
Those devices do not react well to being accessed when the base part is
The Surface System Aggregator Module (SSAM) subsystem provides various
functionalities, which are separated by spreading them across multiple
devices and corresponding drivers. Parts of that functionality / some of
those devices, however, can (as far as we currently know) not be
auto-detected by
The Surface System Aggregator Module (SSAM) subsystem provides various
functionalities, which are separated by spreading them across multiple
devices and corresponding drivers. Parts of that functionality / some of
those devices, however, can (as far as we currently know) not be
auto-detected by
On 12/02/2021 13:29, Song Bao Hua (Barry Song) wrote:
-Original Message-
From: Andy Shevchenko [mailto:andy.shevche...@gmail.com]
Sent: Friday, February 12, 2021 11:57 PM
To: Song Bao Hua (Barry Song)
Cc: Grygorii Strashko ; Arnd Bergmann
; luojiaxing ; Linus Walleij
; Santosh
From: Kalyan Thota
Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.
To enable vblank_disable_immediate flag the
This introduces the pureLiFi LiFi driver for LiFi-X, LiFi-XC
and LiFi-XL USB devices.
This driver implementation has been based on the zd1211rw driver.
Driver is based on 802.11 softMAC Architecture and uses
native 802.11 for configuration and management.
The driver is compiled and tested in
Hi,
I have realized that I did not comment the two ideas.
On Wed 2021-02-10 11:27:45, Timur Tabi wrote:
>
>
> On 2/10/21 7:41 AM, Petr Mladek wrote:
> >
> > The option causes that vsprintf() will not hash pointers. Yes, it is
> > primary used by printk(). But it is used also in some other
> >
801 - 900 of 1096 matches
Mail list logo
