The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 114
The current driver is failing without complete bootchain in
BAM mode since NAND_DEV_CMD_VLD value is not valid. So
programmed the required value in NAND_DEV_CMD_VLD register.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file chan
The current driver is failing without complete bootchain in
BAM mode since NAND_DEV_CMD_VLD value is not valid. So
programmed the required value in NAND_DEV_CMD_VLD register.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file changed, 4 insertions(+)
diff --git
1. BAM uses READ_LOCATION registers to copy data from offset
into data buffer.
2. BAM requires EOT flag should be set only for the last data
write in a codeword.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.
1. BAM uses READ_LOCATION registers to copy data from offset
into data buffer.
2. BAM requires EOT flag should be set only for the last data
write in a codeword.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 46 ++-
1 file
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 44 ++
drivers/mtd/nand/qcom_n
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 44 ++
drivers/mtd/nand/qcom_nandc.c | 54
the registers read/write descriptors in
command channel.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 119 --
1 file changed, 114 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c
the registers read/write descriptors in
command channel.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 119 --
1 file changed, 114 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index
transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 190 +++---
1 file
functions
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 63 ++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8e7dc9e..1
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status for ECC
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_n
functions
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 63 ++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8e7dc9e..17766af 100644
--- a/drivers/mtd
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status for ECC
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 67
the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.
The configuration for BCH is not correct in the current
driver so this patch fixed the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
The configuration for BCH is not correct in the current
driver so this patch fixed the same.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index
the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 41 +-
drivers/mtd/nand/qc
and the command
descriptor will be mapped with dma_map_sg so the register buffer
should be DMA coherent.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 25 +++--
drivers/mtd/nand/qcom_nandc.c
and the command
descriptor will be mapped with dma_map_sg so the register buffer
should be DMA coherent.
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 25 +++--
drivers/mtd/nand/qcom_nandc.c | 106 -
2 files changed
every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from bam
transaction.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mt
every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from bam
transaction.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 116
.
https://www.spinics.net/lists/kernel/msg2542483.html
Abhishek Sahu (14):
qcom: mtd: nand: Add driver data for QPIC DMA
qcom: mtd: nand: add and initialize QPIC DMA resources
qcom: mtd: nand: Fixed config error for BCH
qcom: mtd: nand: reorganize nand devices probing
qcom: mtd: nand: allocate
.
https://www.spinics.net/lists/kernel/msg2542483.html
Abhishek Sahu (14):
qcom: mtd: nand: Add driver data for QPIC DMA
qcom: mtd: nand: add and initialize QPIC DMA resources
qcom: mtd: nand: Fixed config error for BCH
qcom: mtd: nand: reorganize nand devices probing
qcom: mtd: nand: allocate
-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
include/linux/dma/qcom_bam_dma.h | 79
1 file changed, 79 insertions(+)
create mode 100644 include/linux/dma/qcom_bam_dma.h
diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam
-off-by: Abhishek Sahu
---
include/linux/dma/qcom_bam_dma.h | 79
1 file changed, 79 insertions(+)
create mode 100644 include/linux/dma/qcom_bam_dma.h
diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_dma.h
new file mode 100644
which tells the DMA
controller that the passed data is in command descriptor
format so added the flag in DMA API for this.
Abhishek Sahu (3):
dmaengine: add DMA_PREP_CMD for non-Data descriptors.
dmaengine: qcom: bam_dma: wrapper functions for command descriptor
dmaengine: qcom: bam_dma: add
which tells the DMA
controller that the passed data is in command descriptor
format so added the flag in DMA API for this.
Abhishek Sahu (3):
dmaengine: add DMA_PREP_CMD for non-Data descriptors.
dmaengine: qcom: bam_dma: wrapper functions for command descriptor
dmaengine: qcom: bam_dma: add
is in command format
and DMA driver will form descriptor in the required format.
This flag can be used by any DMA controller driver which requires
special handling for non-Data descriptors.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
include/linux/dmaengine.h | 3 +++
1 file chan
is in command format
and DMA driver will form descriptor in the required format.
This flag can be used by any DMA controller driver which requires
special handling for non-Data descriptors.
Signed-off-by: Abhishek Sahu
---
include/linux/dmaengine.h | 3 +++
1 file changed, 3 insertions(+)
diff
If DMA_PREP_CMD flag is passed in prep_slave_sg then peripheral
driver has passed the data is in BAM command descriptor format
and BAM driver should set CMD bit for each of the HW descriptors.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/dma/qcom/bam_dma.c | 6 +-
If DMA_PREP_CMD flag is passed in prep_slave_sg then peripheral
driver has passed the data is in BAM command descriptor format
and BAM driver should set CMD bit for each of the HW descriptors.
Signed-off-by: Abhishek Sahu
---
drivers/dma/qcom/bam_dma.c | 6 +-
1 file changed, 5 insertions
These configs are required for booting kernel in QCOM IPQ4019 boards.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 4
These configs are required for booting kernel in QCOM IPQ4019 boards.
Signed-off-by: Abhishek Sahu
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 4ffdd60..28c98c6 100644
--- a/arch
erated per NAND page read/write
for 2K page
- The mtd read speed 7419 KiB/s which increases boot time
and decrease the File System KPI's
--
Abhishek Sahu
erated per NAND page read/write
for 2K page
- The mtd read speed 7419 KiB/s which increases boot time
and decrease the File System KPI's
--
Abhishek Sahu
am_apply_descriptor_flags)
This makes it bam specific and causes issues if we want to use this
code in
generic libs, but yes this is an option but should be last resort.
If adding flags is a possibility (which it didn't seem to be in the
past), that
would make things much easier.
Also, Main reason for this approach was to set different flags for each
BAM descriptor present in a TX descriptor.
Regards,
Andy
--
Abhishek Sahu
am_apply_descriptor_flags)
This makes it bam specific and causes issues if we want to use this
code in
generic libs, but yes this is an option but should be last resort.
If adding flags is a possibility (which it didn't seem to be in the
past), that
would make things much easier.
Also, Main reason for this approach was to set different flags for each
BAM descriptor present in a TX descriptor.
Regards,
Andy
--
Abhishek Sahu
On 2016-12-29 23:24, Andy Gross wrote:
On Thu, Dec 22, 2016 at 01:04:37AM +0530, Abhishek Sahu wrote:
On 2016-12-21 01:55, Andy Gross wrote:
>On Wed, Dec 21, 2016 at 12:58:50AM +0530, Abhishek Sahu wrote:
>
>
>
>>>>Okay, do you have pointer on that one, will avoid askin
On 2016-12-29 23:24, Andy Gross wrote:
On Thu, Dec 22, 2016 at 01:04:37AM +0530, Abhishek Sahu wrote:
On 2016-12-21 01:55, Andy Gross wrote:
>On Wed, Dec 21, 2016 at 12:58:50AM +0530, Abhishek Sahu wrote:
>
>
>
>>>>Okay, do you have pointer on that one, will avoid askin
with recalc_rate operation.
Abhishek Sahu (1):
clk: qcom: ipq4019: Add the cpu clock frequency change notifier
drivers/clk/qcom/gcc-ipq4019.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
--
The Qualcomm Innovation Center, Inc. is a member
the parent of this clock to stable PLL FEPLL500 for
PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu <
with recalc_rate operation.
Abhishek Sahu (1):
clk: qcom: ipq4019: Add the cpu clock frequency change notifier
drivers/clk/qcom/gcc-ipq4019.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
--
The Qualcomm Innovation Center, Inc. is a member
the parent of this clock to stable PLL FEPLL500 for
PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu
---
drivers/clk
On 2016-12-21 01:55, Andy Gross wrote:
On Wed, Dec 21, 2016 at 12:58:50AM +0530, Abhishek Sahu wrote:
>>Okay, do you have pointer on that one, will avoid asking the same
>>questions
>>again.
>
>I'll see if I can find the correspondance and send to you directly.
>
On 2016-12-21 01:55, Andy Gross wrote:
On Wed, Dec 21, 2016 at 12:58:50AM +0530, Abhishek Sahu wrote:
>>Okay, do you have pointer on that one, will avoid asking the same
>>questions
>>again.
>
>I'll see if I can find the correspondance and send to you directly.
>
On 2016-12-19 23:22, Andy Gross wrote:
On Mon, Dec 19, 2016 at 09:19:23PM +0530, Vinod Koul wrote:
On Sun, Dec 18, 2016 at 11:06:42PM -0600, Andy Gross wrote:
> On Sun, Dec 18, 2016 at 09:56:02PM +0530, Vinod Koul wrote:
> > On Thu, Dec 15, 2016 at 03:25:52PM +0530, Abhishek S
On 2016-12-19 23:22, Andy Gross wrote:
On Mon, Dec 19, 2016 at 09:19:23PM +0530, Vinod Koul wrote:
On Sun, Dec 18, 2016 at 11:06:42PM -0600, Andy Gross wrote:
> On Sun, Dec 18, 2016 at 09:56:02PM +0530, Vinod Koul wrote:
> > On Thu, Dec 15, 2016 at 03:25:52PM +0530, Abhishek S
peripheral drivers.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/dma/qcom/bam_dma.c | 6 +-
include/linux/dma/qcom_bam_dma.h | 25 +
2 files changed, 26 insertions(+), 5 deletions(-)
create mode 100644 include/linux/dma/qcom_bam_dma.h
diff
peripheral drivers.
Signed-off-by: Abhishek Sahu
---
drivers/dma/qcom/bam_dma.c | 6 +-
include/linux/dma/qcom_bam_dma.h | 25 +
2 files changed, 26 insertions(+), 5 deletions(-)
create mode 100644 include/linux/dma/qcom_bam_dma.h
diff --git a/drivers/dma/qcom
BAM custom mapping mainly adds per SG BAM specific flag support
which cannot be implemented with generic SG mapping function.
For each SG, it checks for dma_flags and set the same in
bam_async_desc.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/dma/qcom/bam_dma.c
BAM custom mapping mainly adds per SG BAM specific flag support
which cannot be implemented with generic SG mapping function.
For each SG, it checks for dma_flags and set the same in
bam_async_desc.
Signed-off-by: Abhishek Sahu
---
drivers/dma/qcom/bam_dma.c | 92
driver can set per SG flag and submit it to custom DMA
mapping function.
Abhishek Sahu (5):
dmaengine: qca: bam_dma: Add header file for bam driver
dmaengine: Add support for custom data mapping
dmaengine: qca: bam_dma: Add support for bam sgl
dmaengine: qca: bam_dma: implement custom data
driver can set per SG flag and submit it to custom DMA
mapping function.
Abhishek Sahu (5):
dmaengine: qca: bam_dma: Add header file for bam driver
dmaengine: Add support for custom data mapping
dmaengine: qca: bam_dma: Add support for bam sgl
dmaengine: qca: bam_dma: implement custom data
read data result address,
reserved
reserved
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
include/linux/dma/qcom_bam_dma.h | 46
1 file changed, 46 insertions(+)
diff --git a/include
engine
drivers also which are unable to do DMA mapping with already
available API’s.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
include/linux/dmaengine.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index cc535a4..6
and DMA flag field.
The mapping operations are just wrapper functions
over generic SG functions with per-SG DMA flag support.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
include/linux/dma/qcom_bam_dma.h | 78
1 file changed, 78 inse
read data result address,
reserved
reserved
Signed-off-by: Abhishek Sahu
---
include/linux/dma/qcom_bam_dma.h | 46
1 file changed, 46 insertions(+)
diff --git a/include/linux/dma/qcom_bam_dma.h b
engine
drivers also which are unable to do DMA mapping with already
available API’s.
Signed-off-by: Abhishek Sahu
---
include/linux/dmaengine.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index cc535a4..6324c1f 100644
--- a/include
and DMA flag field.
The mapping operations are just wrapper functions
over generic SG functions with per-SG DMA flag support.
Signed-off-by: Abhishek Sahu
---
include/linux/dma/qcom_bam_dma.h | 78
1 file changed, 78 insertions(+)
diff --git a/include/linux
1. The parent for sdcc clock is sdccpll.
2. The frequency value was wrong so modified the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/d
for this.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 132 +++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
2 files changed, 133 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qc
the parent of this clock to stable PLL FEPLL500 when it gets
for PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu <
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-i
The APSS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/cl
will be divided
down by different PLL internal dividers. Some of the PLL
internal dividers are fixed while other are programmable.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 254 +--
include/dt-bindings/clock/qcom,gcc-i
1. The parent for sdcc clock is sdccpll.
2. The frequency value was wrong so modified the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
for this.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 132 +++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
2 files changed, 133 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index fa922fd
the parent of this clock to stable PLL FEPLL500 when it gets
for PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 39
The APSS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b
will be divided
down by different PLL internal dividers. Some of the PLL
internal dividers are fixed while other are programmable.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 254 +--
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2 files
the i2c node frequency table for 19.05 MHz clock.
[V2]
1. Removed the fixed clock references and add the same as clock nodes
with recalc_rate operation.
Abhishek Sahu (6):
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
the i2c node frequency table for 19.05 MHz clock.
[V2]
1. Removed the fixed clock references and add the same as clock nodes
with recalc_rate operation.
Abhishek Sahu (6):
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
On 2016-11-02 06:54, Stephen Boyd wrote:
On 09/21, Abhishek Sahu wrote:
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 12 +++-
On 2016-11-02 06:54, Stephen Boyd wrote:
On 09/21, Abhishek Sahu wrote:
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 12 +++-
1 file changed, 11 insertions
The current I2C freq table uses MND values which is not
applicable for I2C since its RCG does not have MND
counter. This patch updates the freq table for 19.05
MHz clk frequency with FEPLL_200 parent.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019
1. The parent for sdcc clock is sdccpll so corrected the same
in its parent map.
2. The frequency value was wrong so changed to correct
frequency.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 16
1 file changed, 8 inse
The current I2C freq table uses MND values which is not
applicable for I2C since its RCG does not have MND
counter. This patch updates the freq table for 19.05
MHz clk frequency with FEPLL_200 parent.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 3 +--
1 file changed, 1
1. The parent for sdcc clock is sdccpll so corrected the same
in its parent map.
2. The frequency value was wrong so changed to correct
frequency.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
The feedback divider for DDR PLL has been changed in IPQ4019
bootloader from 111 to 112 so changed the frequency values
for the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 52 +-
1 file chang
The feedback divider for DDR PLL has been changed in IPQ4019
bootloader from 111 to 112 so changed the frequency values
for the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 52 +-
1 file changed, 26 insertions(+), 26 deletions
for this.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu <
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-i
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/cl
for this.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu
---
drivers/clk
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 39
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers
0x2d to 0x2 for
supporting the PLL registers read.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 292 ++-
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2 files changed, 290 insertions(+), 11 del
nodes
with recalc_rate operation.
2. Added all the supported cpu frequencies in frequency table.
Abhishek Sahu (7):
clk: qcom: ipq4019: Added the clock nodes and operations for pll
clk: qcom: ipq4019: Added the apss cpu pll divider clock node
clk: qcom: ipq4019: Added the nodes for pcnoc
0x2d to 0x2 for
supporting the PLL registers read.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 292 ++-
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2 files changed, 290 insertions(+), 11 deletions(-)
diff --git a/drivers
nodes
with recalc_rate operation.
2. Added all the supported cpu frequencies in frequency table.
Abhishek Sahu (7):
clk: qcom: ipq4019: Added the clock nodes and operations for pll
clk: qcom: ipq4019: Added the apss cpu pll divider clock node
clk: qcom: ipq4019: Added the nodes for pcnoc
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 37
include/dt-bindings/clock/qc
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 37
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
2 files
for this.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu <
for this.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu
---
drivers/clk
to 0x2 for
supporting the PLL registers read.
5. Changes the fixed clock name to have consistency in all
clock names
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 316 ---
include/dt-bindings/cloc
to 0x2 for
supporting the PLL registers read.
5. Changes the fixed clock name to have consistency in all
clock names
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 316 ---
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2
the parent of this clock to stable PLL FEPLL500 when it gets
for PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu <
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