On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn
01101700
01111600
10001500
10011400
10101300
10111200
11001100
11011000
1110 900
800
Signed-off-by: Anson Huang
---
No changes
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Anson Huang
---
Changes since V1:
- split the patch into 2 patches, #1 fixed tho
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++
2 files changed, 45
Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn
Hi, Stephen
> Quoting Anson Huang (2019-08-17 15:22:01)
> > Hi, Stephen
> >
> > > Quoting anson.hu...@nxp.com (2019-08-15 03:59:42)
> > > > diff --git a/drivers/clk/imx/clk-imx8mn.c
> > > > b/drivers/clk/imx/clk-imx8mn.c index ecd1062..3f1239a 1
Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table, also add .rate_count assignment which
is necessary for searching required PLL rate from the table.
Signed-off-by: Anson Huang
---
Changes since V1:
- Improve commit log, no code change
On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn
Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++
2 files changed, 45
01101700
01111600
10001500
10011400
10101300
10111200
11001100
11011000
1110 900
800
Signed-off-by: Anson Huang
---
No changes
Hi, Stephen
> Quoting anson.hu...@nxp.com (2019-08-15 03:59:42)
> > diff --git a/drivers/clk/imx/clk-imx8mn.c
> > b/drivers/clk/imx/clk-imx8mn.c index ecd1062..3f1239a 100644
> > --- a/drivers/clk/imx/clk-imx8mn.c
> > +++ b/drivers/clk/imx/clk-imx8mn.c
> > @@ -82,6 +84,7 @@ static struct
Hi, Shawn
> > On 16/08/2019 02:38, Anson Huang wrote:
> > > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
> > > are supported, details as below:
> > >
> > > root@imx8mmevk:~# cat
> > /sys/devices/system/cpu/cpu0/cpuidle/s
/cpu/cpu0/cpuidle/state1/name
cpu-pd-wait
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
6647
Signed-off-by: Anson Huang
Acked-by: Daniel Lezcano
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64
Hi, Daniel/Shawn
> On 16/08/2019 02:38, Anson Huang wrote:
> > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
> > are supported, details as below:
> >
> > root@imx8mmevk:~# cat
> /sys/devices/system/cpu/cpu0/cpuidle/state0/name
> > WF
Hi, Daniel
> Hi Anson,
>
> sorry for the late review, I've been pretty busy.
That is OK for sure.
>
> If Shawn is ok, I can pick the patches 1-4 in my tree and then this one after
> you fix the comments below.
Shawn should be OK for it, and he already took patch [PATCH V5 2/5] arm64:
Enable
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot
/cpu/cpu0/cpuidle/state1/name
cpu-pd-wait
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
6647
Signed-off-by: Anson Huang
---
Changes since V5:
- improve state1 idle name to better match PSCI doc;
- remove wakeup-latency-us property as it is NOT necessary when
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang
---
No changes
From: Anson Huang
On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn
From: Anson Huang
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index
From: Anson Huang
i.MX8MN has different speed grading definition as below, it has 4 bits
to define speed grading, add support for it.
SPEED_GRADE[3:0]MHz
2300
00012200
00102100
00112000
01001900
0101
From: Anson Huang
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++
2 files changed, 45
From: Anson Huang
Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b
From: Anson Huang
Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale
From: Anson Huang
Add "gpio-ranges" property to establish connections between GPIOs
and PINs on i.MX8MN pinctrl driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/i
Hi, Alexandre
> On 19/07/2019 19:04:21+, Trent Piepho wrote:
> > On Fri, 2019-07-19 at 02:57 +0000, Anson Huang wrote:
> > >
> > > > I do worry that handling the irq before the rtc device is
> > > > registered could still result in a crash. From wha
From: Anson Huang
The i.MX7ULP Watchdog Timer (WDOG) module is an independent timer
that is available for system use.
It provides a safety feature to ensure that software is executing
as planned and that the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module
From: Anson Huang
Select CONFIG_IMX7ULP_WDT by default to support i.MX7ULP watchdog.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/arch/arm/configs
From: Anson Huang
Add wdog1 node to support watchdog driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm/boot/dts/imx7ulp.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 6859a3a..1fdb5a35
From: Anson Huang
Add the watchdog bindings for Freescale i.MX7ULP.
Signed-off-by: Anson Huang
---
No changes.
---
.../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog
From: Anson Huang
An error message is already displayed by watchdog_register_device()
when failed, so no need to have error log again for failure of
calling devm_watchdog_register_device().
Signed-off-by: Anson Huang
---
drivers/watchdog/imx_sc_wdt.c | 5 +
1 file changed, 1 insertion
Hi, Guenter
> On Fri, Aug 09, 2019 at 03:13:59PM +0800, Anson Huang wrote:
> > Add the watchdog bindings for Freescale i.MX7ULP.
> >
> > Signed-off-by: Anson Huang
> > ---
> > .../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22
> +
Hi, Guenter
> On Fri, Aug 09, 2019 at 03:14:00PM +0800, Anson Huang wrote:
> > The i.MX7ULP Watchdog Timer (WDOG) module is an independent timer
> that
> > is available for system use.
> > It provides a safety feature to ensure that software is executing as
>
(refreshed) within a certain period, it resets the MCU.
Add driver support for i.MX7ULP watchdog.
Signed-off-by: Anson Huang
---
drivers/watchdog/Kconfig | 13 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/imx7ulp_wdt.c | 221 +
3 files
Add wdog1 node to support watchdog driver.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx7ulp.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 6859a3a..1fdb5a35 100644
--- a/arch/arm/boot/dts
Select CONFIG_IMX7ULP_WDT by default to support i.MX7ULP watchdog.
Signed-off-by: Anson Huang
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/arch/arm/configs/imx_v6_v7_defconfig
index bd2e2f5..f69075b 100644
Add the watchdog bindings for Freescale i.MX7ULP.
Signed-off-by: Anson Huang
---
.../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
diff --git
From: Anson Huang
When of_clk_add_provider failed, all clks should be unregistered.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index e494e99
From: Anson Huang
When of_clk_add_provider failed, all clks should be unregistered.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mq.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index
Hi, Marco
Are you OK with this patch?
Thanks,
Anson.
> On Tue, Jul 02, 2019 at 03:45:45PM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Add i.MX SCU SoC's UID(unique identifier) support, user can read it
> > from sysfs:
> >
> > r
Gentle Ping...
> From: Anson Huang
>
> Add compatible for i.MX8MN and add i.MX8MM/i.MX8MN to the description.
>
> Signed-off-by: Anson Huang
> ---
> Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
&
Ping for this patch series...
> From: Anson Huang
>
> This patch adds the soc & board binding for i.MX8MN.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
> ---
> No change.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 6
explicitly if the
CLK_SET_RATE_GATE/CLK_SET_PARENT_GATE is present, most likely it will impact
other platforms I think, so the most safe way is just to do it inside our
i.MX7ULP composite clock driver. What do you think?
Thanks,
Anson
> Hi, Stephen
>
> > Quoting Anson Huang (2019-04
Gentle ping...
> From: Anson Huang
>
> The system counter block guide states that the base clock is internally
> divided
> by 3 before use, that means the clock input of system counter defined in DT
> should be base clock which is normally from OSC, and then internally div
From: Anson Huang
i.MX SoC's GPIO clock is optional, so it is better to use
devm_clk_get_optional instead of devm_clk_get.
Signed-off-by: Anson Huang
---
drivers/gpio/gpio-mxc.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio
From: Anson Huang
When registering tmu zone failed, the error path should be err_tmu
instead of err_iomap, as iounmap() needs to be called.
Signed-off-by: Anson Huang
---
New patch.
---
drivers/thermal/qoriq_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
From: Anson Huang
Some platforms like i.MX8M series SoCs have clock control for TMU,
add optional clocks property to the binding doc.
Signed-off-by: Anson Huang
Reviewed-by: Rob Herring
---
No changes, noted the i.MX8M series SoCs need this clock in commit log.
---
Documentation/devicetree
From: Anson Huang
Some platforms like i.MX8MQ has clock control for this module,
need to add clock operations to make sure the driver is working
properly.
Signed-off-by: Anson Huang
Reviewed-by: Guido Günther
---
Changes since V2:
- move this patch as first patch in the series
From: Anson Huang
Use __maybe_unused for power management related functions
instead of #if CONFIG_PM_SLEEP to simply the code.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/thermal/qoriq_thermal.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers
From: Anson Huang
Use devm_platform_ioremap_resource() instead of of_iomap() to
save the iounmap() call in error handle path;
Signed-off-by: Anson Huang
---
No change, just adjust the patch sequence and handle the conflicts.
---
drivers/thermal/qoriq_thermal.c | 18 ++
1 file
From: Anson Huang
Some platforms like i.MX8MQ has clock control for this module,
need to add clock operations to make sure the driver is working
properly.
Signed-off-by: Anson Huang
Reviewed-by: Guido Günther
---
Changes since V1:
- use devm_clk_get_optional() instead of devm_clk_get
From: Anson Huang
Some platforms have clock control for TMU, add optional
clocks property to the binding doc.
Signed-off-by: Anson Huang
---
No changes.
---
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
From: Anson Huang
Use devm_platform_ioremap_resource() instead of of_iomap() to
save the iounmap() call in error handle path;
Signed-off-by: Anson Huang
---
No changes.
---
drivers/thermal/qoriq_thermal.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git
From: Anson Huang
Use __maybe_unused for power management related functions
instead of #if CONFIG_PM_SLEEP to simply the code.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/thermal/qoriq_thermal.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers
Hi, Guido
> On Fri, Jul 05, 2019 at 12:56:10PM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Some platforms like i.MX8MQ has clock control for this module, need to
> > add clock operations to make sure the driver is working properly.
> &g
Hi, Daniel
> On Mon, Jul 29, 2019 at 10:20 AM Daniel Baluta
> wrote:
> >
> >
> > > > Your explanation makes a lot of sense. We will take care today of
> > > > Abel's patch.
> > > > What do you think about Fabio's patch? I also think this is a valid
> > > > patch:
> > > >
> >
> >
> > >
> > >
Hi, Daniel
> On Mon, Jul 29, 2019 at 4:29 AM Anson Huang
> wrote:
> >
> > Hi, Abel/Daniel
> >
> > > On 19-07-27 09:33:10, Daniel Baluta wrote:
> > > > On Sat, Jul 27, 2019 at 9:19 AM Anson Huang
> > > wrote:
> > > > >
&g
Hi, Abel/Daniel
> On 19-07-27 09:33:10, Daniel Baluta wrote:
> > On Sat, Jul 27, 2019 at 9:19 AM Anson Huang
> wrote:
> > >
> > > Hi, Daniel
> > >
> > > > Subject: Re: [PATCH 5/6] clk: imx8mq: Remove CLK_IS_CRITICAL flag
>
origin/HEAD)
> Author: Stephen Rothwell
> Date: Fri Jul 26 15:18:02 2019 +1000
>
> Add linux-next specific files for 20190726
>
> Signed-off-by: Stephen Rothwell
>
>
> I know this is crazy but reverting commit:
>
> commit 431bdd1df48ee2896ea9980d9153e3ae
Hi, Shawn
> On 09-07-19, 16:00, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Update opp-suspend property's description to support multiple
> > opp-suspend properties defined in DT, the OPP with highest opp-hz and
> > with opp-suspend property pr
> On Sun, Jul 21, 2019 at 7:51 PM Shawn Guo wrote:
> >
> > On Wed, Jun 19, 2019 at 01:52:43PM +0800, anson.hu...@nxp.com wrote:
> > > From: Anson Huang
> > >
> > > Add the clock binding doc for i.MX8MN.
> > >
> > > Signed-off-by: An
From: Anson Huang
YAML file can NOT contain tab as indentation, fix it.
Fixes: 6d6062553e3d ("dt-bindings: imx: Add clock binding doc for i.MX8MN")
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml | 2 +-
1 file changed, 1 insertion(+),
Hi, Stephen
> Quoting Anson Huang (2019-04-24 22:19:12)
> > i.MX7ULP peripheral clock ONLY allow parent/rate to be changed with
> > clock gated, however, during clock tree initialization, the peripheral
> > clock could be enabled by bootloader, but the prepare count in cl
From: Anson Huang
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mn.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx
From: Anson Huang
imx_register_uart_clocks_hws() function is NOT implemented
at all, remove it.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 9995f2a..f7a389a 100644
--- a/drivers/clk
From: Anson Huang
Earlycon's clock could be disabled during kernel boot up,
if earlycon is enabled and its clock is gated, then kernel
boot up will fail. Make sure earlycon's clock is enabled
during kernel boot up.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx7ulp.c | 31
Hi, Shawn
> On Wed, Jul 10, 2019 at 02:30:54PM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Add i.MX8MM system counter node to enable timer-imx-sysctr broadcast
> > timer driver.
> >
> > Signed-off-by: Anson Huang
>
> Do I need t
Hi, Shawn
> On Mon, Jun 24, 2019 at 02:35:10AM +0000, Anson Huang wrote:
> > Hi, Shawn
> >
> > > -Original Message-
> > > From: Shawn Guo
> > > Sent: Monday, June 24, 2019 10:27 AM
> > > To: Anson Huang
> > > Cc: mark.rutl...@a
Hi, Alexandre
> On 19/07/2019 11:01:02+0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > The RTC IRQ is requested before the struct rtc_device is allocated,
> > this may lead to a NULL pointer dereference in IRQ handler.
> >
> > To fix this
From: Anson Huang
The RTC IRQ is requested before the struct rtc_device is allocated,
this may lead to a NULL pointer dereference in IRQ handler.
To fix this issue, allocating the rtc_device struct and register rtc
device before requesting the RTC IRQ.
Using devm_rtc_allocate_device
Hi, Trent
> On Thu, 2019-07-18 at 03:08 +, Aisheng Dong wrote:
> > > From: Anson Huang
> > > Sent: Wednesday, July 17, 2019 9:58 PM> Hi, Aisheng
> > >
> > > > > From: anson.hu...@nxp.com
> > > > > Sent: Tuesday, July 16, 2
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sx.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sl.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6ul.dtsi | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sll.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/pwm/pwm-mxs.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
Hi, Aisheng
> > From: anson.hu...@nxp.com
> > Sent: Tuesday, July 16, 2019 3:19 PM
> >
> > The RTC IRQ is requested before the struct rtc_device is allocated,
> > this may lead to a NULL pointer dereference in IRQ handler.
> >
> > To fix this issue, allocating the rtc_device struct before
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/mmc/host/mxs-mmc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/i2c/busses/i2c-mxs.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/i2c/busses/i2c-imx-lpi2c.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/rtc/rtc-imxdi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
---
drivers/rtc/rtc-mxc_v2.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff
From: Anson Huang
The RTC IRQ is requested before the struct rtc_device is allocated,
this may lead to a NULL pointer dereference in IRQ handler.
To fix this issue, allocating the rtc_device struct before requesting
the RTC IRQ using devm_rtc_allocate_device, and use rtc_register_device
From: Anson Huang
According to i.MX8MM reference manual Rev.1, 03/2019:
SAI3_RXC pin's mux option #1 should be GPT1_CLK, NOT GPT1_CAPTURE2;
SAI3_TXFS pin's mux option #1 should be GPT1_CAPTURE2, NOT GPT1_CLK.
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm&quo
From: Anson Huang
Add compatible for i.MX8MN and add i.MX8MM/i.MX8MN to the description.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/nvmem/imx
From: Anson Huang
i.MX8MN is a new SoC of i.MX8M series, it is similar to i.MX8MM
in terms of addressing and clock setup, add support for its fuse
read/write.
Signed-off-by: Anson Huang
---
drivers/nvmem/imx-ocotp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/nvmem/imx
Hi, Rob
> On Tue, Jul 9, 2019 at 7:30 PM Anson Huang wrote:
> >
> > Hi, Rob
> >
> > > On Mon, Jul 1, 2019 at 3:47 AM wrote:
> > > >
> > > > From: Anson Huang
> > >
> > > 'dt-bindings: timer: ...' for the subject.
&
From: Anson Huang
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
Changes since V4:
- update the clock info using fixed clock node;
- correct the reg range;
- update the interrupt number as the system
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
Changes since V4:
- update the clock info using fixed clock node;
- correct the reg range;
- update the interrupt number as the system
From: Anson Huang
Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
are supported, details as below:
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
3973
root@imx8mmevk:~# cat
From: Anson Huang
ARCH_MXC platforms needs system counter as broadcast timer
to support cpuidle, enable it by default.
Signed-off-by: Anson Huang
---
New patch, now that system counter driver lands in main line, we can enable it
by default.
---
arch/arm64/Kconfig.platforms | 1 +
1 file
From: Anson Huang
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang
Hi, Rob
> On Mon, Jul 1, 2019 at 3:47 AM wrote:
> >
> > From: Anson Huang
>
> 'dt-bindings: timer: ...' for the subject.
OK, I made a mistake.
>
> >
> > Systems which use platform driver model for clock driver require the
> > clock frequency
From: Anson Huang
With property "opp-supported-hw" introduced, the OPP table
in DT could be a large OPP table and ONLY a subset of OPPs
are available, based on the version of the hardware running
on. That introduces restriction of using "opp-suspend"
property to define th
From: Anson Huang
Add opp-suspend property to each OPP, the of opp core will
select the OPP HW supported and with highest rate to be
suspend opp, it will speed up the suspend/resume process.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4
1
From: Anson Huang
Add opp-suspend property to each OPP, the of opp core will
select the OPP HW supported and with highest rate to be
suspend opp, it will speed up the suspend/resume process.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 +++
1
From: Anson Huang
Update opp-suspend property's description to support multiple
opp-suspend properties defined in DT, the OPP with highest opp-hz
and with opp-suspend property present will be used as suspend opp.
Signed-off-by: Anson Huang
---
New patch.
---
Documentation/devicetree/bindings
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