tate control functions, as through
> the generic framework PCI Core takes care of the necessary operations,
> and drivers are required to do only device-specific jobs.
>
> Signed-off-by: Vaibhav Gupta
s/.suspen/.suspend/ above
These both look right to me.
Reviewed-by: Bjorn Helgaas
Look
On Thu, Aug 06, 2020 at 03:40:41PM -0700, Tuan Phan wrote:
>
> > On Aug 6, 2020, at 3:27 PM, Bjorn Helgaas wrote:
> >
> > On Thu, Aug 06, 2020 at 02:57:34PM -0700, Tuan Phan wrote:
> >> Ampere Altra SOC supports only 32-bit ECAM reading. Therefore,
> >
On Thu, Aug 06, 2020 at 02:57:34PM -0700, Tuan Phan wrote:
> Ampere Altra SOC supports only 32-bit ECAM reading. Therefore,
> add an MCFG quirk for the platform.
This is interesting. So this host bridge supports sub 32-bit config
*writes*, but not reads?
I actually don't know whether that
On Thu, Jul 30, 2020 at 11:45:45AM +0300, Dan Carpenter wrote:
> On Wed, Jul 29, 2020 at 06:13:44PM +0300, Andy Shevchenko wrote:
> > On Wed, Jul 29, 2020 at 5:00 PM Cengiz Can wrote:
> > >
> > > `find_gmin_subdev` function that returns a pointer to `struct
> > > gmin_subdev` can return NULL.
> >
On Thu, Aug 06, 2020 at 10:54:45AM +0100, Lorenzo Pieralisi wrote:
> On Wed, Aug 05, 2020 at 06:30:50PM -0500, Bjorn Helgaas wrote:
> > On Wed, Aug 05, 2020 at 05:03:26PM -0500, Bjorn Helgaas wrote:
> > > On Wed, Aug 05, 2020 at 10:39:28PM +0100, Lorenzo Pieralisi wrote:
>
On Wed, Aug 05, 2020 at 05:03:26PM -0500, Bjorn Helgaas wrote:
> On Wed, Aug 05, 2020 at 10:39:28PM +0100, Lorenzo Pieralisi wrote:
> > On Wed, Aug 05, 2020 at 03:43:58PM -0500, Bjorn Helgaas wrote:
> > > On Tue, Jun 16, 2020 at 06:26:54PM +0530, Bharat Kumar Gogada wrote:
>
On Wed, Aug 05, 2020 at 10:39:28PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Aug 05, 2020 at 03:43:58PM -0500, Bjorn Helgaas wrote:
> > On Tue, Jun 16, 2020 at 06:26:54PM +0530, Bharat Kumar Gogada wrote:
> > > - Add support for Versal CPM as Root Port.
> > > - The Versa
On Tue, Jun 16, 2020 at 06:26:54PM +0530, Bharat Kumar Gogada wrote:
> - Add support for Versal CPM as Root Port.
> - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
> block for CPM along with the integrated bridge can function
> as PCIe Root Port.
> - Bridge error and
On Wed, Aug 05, 2020 at 11:37:11PM +0530, Vaibhav Gupta wrote:
> Drivers using legacy power management .suspen()/.resume() callbacks
> have to manage PCI states and device's PM states themselves. They also
> need to take care of standard configuration registers.
s/using legacy/using legacy PCI/
[update Linus's address, drop Qi's (bounced)]
On Wed, Aug 05, 2020 at 10:23:31AM -0500, Bjorn Helgaas wrote:
> [+cc Tomoya, Linus, Qi, Ben from e9bc8fa5df1c]
>
> On Mon, Jul 20, 2020 at 07:30:32PM +0530, Vaibhav Gupta wrote:
> > Drivers using legacy PM have to manage PCI states
[+cc Tomoya, Linus, Qi, Ben from e9bc8fa5df1c]
On Mon, Jul 20, 2020 at 07:30:32PM +0530, Vaibhav Gupta wrote:
> Drivers using legacy PM have to manage PCI states and device's PM states
> themselves. They also need to take care of configuration registers.
>
> With improved and powerful support of
On Wed, Aug 05, 2020 at 09:51:54PM +0530, Vaibhav Gupta wrote:
> On Wed, Aug 05, 2020 at 10:28:32AM -0500, Bjorn Helgaas wrote:
> > On Wed, Aug 05, 2020 at 10:23:31AM -0500, Bjorn Helgaas wrote:
> > > On Mon, Jul 20, 2020 at 07:30:32PM +0530, Vaibhav Gupta wrote:
> > >
On Tue, Aug 04, 2020 at 12:40:43PM -0700, Sean V Kelley wrote:
> From: Sean V Kelley
>
> On the use of FLR on RCiEPs for the fatal case, still interested in more
> feedback from the earlier discussion here [1]:
>
> [1]
>
"git log --oneline" again.
On Tue, Aug 04, 2020 at 12:40:45PM -0700, Sean V Kelley wrote:
> From: Qiuxu Zhuo
>
> If a Root Complex Integrated Endpoint (RCiEP) is implemented, errors may
> optionally be sent to a corresponding Root Complex Event Collector (RCEC).
> Each RCiEP must be associated
On Tue, Aug 04, 2020 at 12:40:46PM -0700, Sean V Kelley wrote:
> From: Qiuxu Zhuo
>
> When an RCEC device signals error(s) to a CPU core, the CPU core
> needs to walk all the RCiEPs associated with that RCEC to check
> errors. So add the function pcie_walk_rcec() to walk all RCiEPs
> associated
On Tue, Aug 04, 2020 at 12:40:44PM -0700, Sean V Kelley wrote:
> From: Qiuxu Zhuo
>
> A PCIe Root Complex Event Collector(RCEC) has the base class 0x08,
> sub-class 0x07, and programming interface 0x00. Add the class code
> 0x0807 to identify RCEC devices and add the defines for the RCEC
>
On Wed, Aug 05, 2020 at 11:32:16AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the pci tree, today's linux-next build (x86_64 allmodconfig)
> produced this warning:
>
> drivers/pci/controller/pcie-altera.c: In function 'altera_pcie_parse_dt':
>
On Tue, Aug 04, 2020 at 05:13:25PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Aug 04, 2020 at 02:04:30PM +0200, Geert Uytterhoeven wrote:
> > The conversion to modern host bridge probing made the driver allocate
> > its private data using devm_pci_alloc_host_bridge(), but forgot to
> > remove the
On Sun, Aug 02, 2020 at 08:46:48PM +0200, Borislav Petkov wrote:
> On Sun, Aug 02, 2020 at 07:28:00PM +0200, Saheed Bolarinwa wrote:
> > Because the value ~0 has a meaning to some drivers and only
>
> No, ~0 means that the PCI read failed. For *every* PCI device I know.
Wait, I'm not convinced
dn and up to 0 when a value of ~0 is read into them, this
> ensures false is returned on failure in this case.
>
> Suggested-by: Bjorn Helgaas
> Signed-off-by: Saheed O. Bolarinwa
> ---
>
> drivers/infiniband/hw/hfi1/aspm.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 dele
On Thu, Jul 30, 2020 at 10:58:03PM +, Mark Tomlinson wrote:
> On Thu, 2020-07-30 at 11:09 -0500, Bjorn Helgaas wrote:
> > I think it would be better to have a warning once per device, so if
> > XYZ device has a problem and we look at the dmesg log, we would find a
> > sing
PCI fixes:
- Disable ASPM on ASM1083/1085 PCIe-to-PCI bridge (Robert Hancock)
The following changes since commit d08c30d7a0d1826f771f16cde32bd86e48401791:
Revert "PCI/PM: Assume ports without DLL Link Active train links in 100 ms"
(2020-07-22 10:31:52 -0500)
are available in the Git
On Thu, Jul 30, 2020 at 09:36:14AM -0700, Ray Jui wrote:
> On 7/30/2020 9:09 AM, Bjorn Helgaas wrote:
> > On Thu, Jul 30, 2020 at 03:37:46PM +1200, Mark Tomlinson wrote:
> >> The pci_generic_config_write32() function will give warning messages
> >> whenever writing
[+cc Lorenzo, Rob]
On Thu, Jul 30, 2020 at 03:37:46PM +1200, Mark Tomlinson wrote:
> The pci_generic_config_write32() function will give warning messages
> whenever writing less than 4 bytes at a time. As there is nothing we can
> do about this without changing the hardware, the message is just a
he churn adding to the list of allowed
> host bridges.
>
> Signed-off-by: Logan Gunthorpe
> Cc: Bjorn Helgaas
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Huang Rui
Thanks, applied as below with Alex's reviewed-by to pci/peer-to-peer
for v5.9.
I had to enable CONFIG_MEM
On Wed, Jul 29, 2020 at 10:12:18PM +0200, Krzysztof Kozlowski wrote:
> Hi,
>
> Changes since v2:
> 1. Fix almost all warnings, except:
>drivers/pci/controller/pci-hyperv.c:2534: warning: Function parameter or
> member 'version' not described in 'hv_pci_protocol_negotiation'
>
On Tue, Jul 21, 2020 at 08:18:03PM -0600, Robert Hancock wrote:
> Recently ASPM handling was changed to no longer disable ASPM on all
> PCIe to PCI bridges. Unfortunately these ASMedia PCIe to PCI bridge
> devices don't seem to function properly with ASPM enabled, as they
> cause the parent PCIe
On Mon, Jul 27, 2020 at 03:06:55PM +0800, Tiezhu Yang wrote:
> In the current code, we can not see the PCI info after fixup which is
> correct to reflect the reality, it is better to move pci_info() after
> pci_fixup_device() in pci_setup_device().
>
> Signed-off-by: Tiezhu Yang
Applied to
On Tue, Jul 28, 2020 at 06:45:53PM +0800, Kai-Heng Feng wrote:
> We are seeing AMD Radeon Pro W5700 doesn't work when IOMMU is enabled:
> [3.375841] iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT
> device=63:00.0 address=0x42b5b01a0]
> [3.375845] iommu ivhd0: AMD-Vi: Event logged
On Tue, Jul 28, 2020 at 01:24:33PM -0600, Logan Gunthorpe wrote:
> Fix a number of missing __iomem and __user tags in the ioctl functions of
> the switchtec driver. This fixes a number of sparse warnings of the form:
>
> sparse: sparse: incorrect type in ... (different address spaces)
>
>
On Wed, Jul 29, 2020 at 08:26:20AM +0200, Krzysztof Kozlowski wrote:
> Fix W=1 compile warnings (invalid kerneldoc):
>
> drivers/pci/vc.c:188: warning: Excess function parameter 'name'
> description in 'pci_vc_do_save_buffer'
>
> Signed-off-by: Krzysztof Kozlowski
This looks great, but
On Wed, Jul 29, 2020 at 03:47:30PM +0530, Vaibhav Gupta wrote:
> On Tue, Jul 28, 2020 at 03:04:13PM -0500, Bjorn Helgaas wrote:
> > On Tue, Jul 28, 2020 at 09:58:10AM +0530, Vaibhav Gupta wrote:
> > > The .suspend() and .resume() callbacks are not defined for this driver.
> &
On Tue, Jul 28, 2020 at 09:57:55PM +0100, James Ettle wrote:
> On Mon, 2020-07-27 at 16:47 -0500, Bjorn Helgaas wrote:
> >
> > I don't see anything in rtsx that enables L0s. Can you collect
> > the dmesg log when booting with "pci=earlydump"? That will show
> &
On Tue, Jul 28, 2020 at 09:58:10AM +0530, Vaibhav Gupta wrote:
> The .suspend() and .resume() callbacks are not defined for this driver.
> Still, their power management structure follows the legacy framework. To
> bring it under the generic framework, simply remove the binding of
> callbacks from
Patch looks fine, but can you run "git log --oneline drivers/pci/vc.c"
and match the subject line style?
On Tue, Jul 28, 2020 at 07:10:45PM +0200, Krzysztof Kozlowski wrote:
> Fix W=1 compile warnings (invalid kerneldoc):
>
> drivers/pci/vc.c:188: warning: Excess function parameter 'name'
>
On Mon, Jul 27, 2020 at 08:52:25PM +0100, James Ettle wrote:
> On Mon, 2020-07-27 at 09:14 -0500, Bjorn Helgaas wrote:
> > I don't know the connection between ASPM and package C-states, so I
> > need to simplify this even more. All I want to do right now is
> > verify
>
t; > Signed-off-by: Tianshu Qiu
Also, Documentation/process/submitting-patches.rst says "the last
Signed-off-by: must always be that of the developer submitting the
patch," which means these should be reversed, since Bingbu submitted
the patch.
> > Reported-by: Bjorn Helgaas
I d
On Sat, Jul 25, 2020 at 09:27:11PM +0100, James Ettle wrote:
> On Fri, 2020-07-24 at 18:13 -0500, Bjorn Helgaas wrote:
> >
> > Maybe we should simplify this a little bit more. James, if you don't
> > touch ASPM config at all, either manually or via udev, does the ASPM
&
PCI fixes:
- Reject invalid IRQ 0 command line argument for virtio_mmio because
IRQ 0 now generates warnings (Bjorn Helgaas)
- Revert "PCI/PM: Assume ports without DLL Link Active train links
in 100 ms", which broke nouveau (Bjorn Helgaas)
The following changes si
esume?
> > -----Original Message-
> > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > Sent: Friday, July 24, 2020 1:13 AM
> > To: 吳昊澄 Ricky; Rui Feng
> > Cc: Arnd Bergmann; Greg Kroah-Hartman; James Ettle; Len Brown; Puranjay
> > Mohan; linux-...@vger.kernel.o
[+cc Rafael, in case you can clear up our wakeup confusion]
original patch:
https://lore.kernel.org/r/20200720155714.714114-1-vaibhavgupt...@gmail.com
On Fri, Jul 24, 2020 at 11:16:55PM +0300, Andy Shevchenko wrote:
> On Fri, Jul 24, 2020 at 6:17 PM Vaibhav Gupta
> wrote:
> > On Fri, Jul 24,
On Thu, Jul 23, 2020 at 02:10:52PM -0600, Logan Gunthorpe wrote:
> On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:
> > On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
> >> On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe
> >> wrote:
> >>>
>
s
> PASID feature discovery (pci_pasid_features) for PRI.
>
> Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities
> before ATS")
> Signed-off-by: Ashok Raj
Applied with Baolu's reviewed-by and Joerg's ack to pci/virtualization
for v5.9, thanks!
>
On Fri, Jul 24, 2020 at 12:57:51PM +0300, Mika Westerberg wrote:
> On Thu, Jul 23, 2020 at 10:30:58PM +0200, Karol Herbst wrote:
> > On Wed, Jul 22, 2020 at 11:25 AM Mika Westerberg
> > wrote:
> > >
> > > On Tue, Jul 21, 2020 at 01:37:12PM -0500, Patrick Volkerding wrote:
> > > > On 7/21/20 10:27
On Fri, Jul 24, 2020 at 09:00:41AM +, Shiju Jose wrote:
> >-Original Message-
> >From: Bjorn Helgaas [mailto:helg...@kernel.org]
> >Sent: 24 July 2020 00:21
> >To: Shiju Jose
> >Cc: linux-a...@vger.kernel.org; linux-...@vger.kernel.org; linux
s
> PASID feature discovery (pci_pasid_features) for PRI.
>
> Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities
> before ATS")
> Signed-off-by: Ashok Raj
This looks right to me, but I would like Joerg's ack before applying
it.
> To: Bjorn Helgaa
On Wed, Jul 22, 2020 at 11:42:43AM +0100, Shiju Jose wrote:
> CPER records describing a firmware-first error are identified by GUID.
> The ghes driver currently logs, but ignores any unknown CPER records.
> This prevents describing errors that can't be represented by a standard
> entry, that would
On Wed, Jul 22, 2020 at 11:39:51AM +0100, Shiju Jose wrote:
> CPER records describing a firmware-first error are identified by GUID.
> The ghes driver currently logs, but ignores any unknown CPER records.
> This prevents describing errors that can't be represented by a standard
> entry, that would
o work. Therefore add it
> > to the list.
> >
> > Signed-off-by: Logan Gunthorpe
> > Cc: Bjorn Helgaas
> > Cc: Christian König
> > Cc: Huang Rui
> > Cc: Alex Deucher
>
> Starting with Zen, all AMD platforms support P2P for reads and writes.
What's the
On Thu, Jul 23, 2020 at 10:38:19AM -0700, Raj, Ashok wrote:
> Hi Bjorn
>
> On Tue, Jul 21, 2020 at 09:54:01AM -0500, Bjorn Helgaas wrote:
> > On Mon, Jul 20, 2020 at 09:43:00AM -0700, Ashok Raj wrote:
> > > PASID and PRI capabilities are only enumerated in PF devi
[+cc Jacopo]
On Thu, Jul 23, 2020 at 11:56:22AM -0500, Bjorn Helgaas wrote:
> James reported this issue with rtsx_pci; can you guys please take a
> look at it? https://bugzilla.kernel.org/show_bug.cgi?id=208117
>
> There's a lot of good info in the bugzilla already.
Likely dupl
James reported this issue with rtsx_pci; can you guys please take a
look at it? https://bugzilla.kernel.org/show_bug.cgi?id=208117
There's a lot of good info in the bugzilla already.
Bjorn
On Wed, Jul 22, 2020 at 06:46:06PM -0600, Robert Hancock wrote:
> On Wed, Jul 22, 2020 at 11:40 AM Bjorn Helgaas wrote:
> > On Tue, Jul 21, 2020 at 08:18:03PM -0600, Robert Hancock wrote:
> > > Recently ASPM handling was changed to no longer disable ASPM on all
> &g
On Wed, Jul 22, 2020 at 03:50:48PM -0600, Jerry Hoemann wrote:
> On Wed, Jul 22, 2020 at 10:21:23AM -0500, Bjorn Helgaas wrote:
> > On Wed, Jul 22, 2020 at 10:52:26PM +0800, Kairui Song wrote:
> > > I think I didn't make one thing clear, The PCI UR error never arrives
>
On Wed, Jul 22, 2020 at 02:15:13AM +0200, Julia Suvorova wrote:
> Scanning for PCI devices at boot takes a long time for KVM guests. It
> can be reduced if KVM will handle all configuration space accesses for
> non-existent devices without going to userspace [1]. But for this to
> work, all
On Tue, Jul 21, 2020 at 12:39:39PM +0530, Vaibhav Gupta wrote:
> Okay. I will improve on it. Just inform me after testing that if any other
> changes are required. I guess [PATCH 1/3] and [PATCH 2/3] are okay, so I will
> only send v3 of [PATCH 3/3] after suggested changes.
FWIW, there's a recent
[+cc Puranjay]
On Tue, Jul 21, 2020 at 08:18:03PM -0600, Robert Hancock wrote:
> Recently ASPM handling was changed to no longer disable ASPM on all
> PCIe to PCI bridges. Unfortunately these ASMedia PCIe to PCI bridge
> devices don't seem to function properly with ASPM enabled, as they
> cause
On Wed, Jul 22, 2020 at 10:52:26PM +0800, Kairui Song wrote:
> On Fri, Mar 6, 2020 at 5:38 PM Baoquan He wrote:
> > On 03/04/20 at 08:53pm, Deepa Dinamani wrote:
> > > On Wed, Mar 4, 2020 at 7:53 PM Baoquan He wrote:
> > > > On 03/03/20 at 01:01pm, Deepa Dinamani wrote:
> > > > > I looked at
gt; allocated")
> Reviewed-by: Andy Shevchenko
> Signed-off-by: Jon Derrick
> Cc: sta...@vger.kernel.org
Acked-by: Bjorn Helgaas# drivers/pci
> ---
> arch/mips/pci/pci-xtalk-bridge.c| 3 +++
> arch/x86/kernel/apic/io_apic.c | 5 +
> drivers/iommu/intel/irq
On Thu, Jul 02, 2020 at 11:06:11AM +0800, Jason Wang wrote:
> On 2020/7/2 上午6:10, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas
> >
> > The "virtio_mmio.device=" command line argument allows a user to specify
> > the size, address, and IRQ of a virtio device.
From: Bjorn Helgaas
rtsx_pci_read_config_dword() and similar wrappers around the PCI config
accessors add very little value, and they obscure the fact that often we
are accessing standard PCI registers that should be coordinated with the
PCI core.
Remove the wrappers and use the PCI config
From: Bjorn Helgaas
Instead of using the driver-specific rtsx_pci_write_config_byte() to update
the PCIe Link Control Register, use pcie_capability_write_word() like the
rest of the kernel does. This makes it easier to maintain ASPM across the
PCI core and drivers.
No functional change
From: Bjorn Helgaas
Instead of hard-coding the location of the L1 PM Substates capability based
on the Device ID, search for it in the extended capabilities list. This
works for any device, as long as it implements the L1 PM Substates
capability correctly, so it doesn't require maintenance
From: Bjorn Helgaas
There are no more uses of struct rtsx_pcr.pcie_cap. Remove it.
Signed-off-by: Bjorn Helgaas
---
drivers/misc/cardreader/rtsx_pcr.c | 1 -
include/linux/rtsx_pci.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/misc/cardreader/rtsx_pcr.c
b/drivers
From: Bjorn Helgaas
Clean up some needlessly device-specific stuff in the Realtek card reader
drivers.
This implements some of my suggestions from
https://lore.kernel.org/r/20200720220651.GA1035857@bjorn-Precision-5520
This will conflict with Ricky's post here:
https://lore.kernel.org/r
From: Bjorn Helgaas
When reading registers defined by the PCIe spec, use the names already
defined by the PCI core. This makes maintenance of the PCI core and
drivers easier. No functional change intended.
Signed-off-by: Bjorn Helgaas
---
drivers/misc/cardreader/rts5249.c | 8
nd.
Does this fix a regression? Is it associated with a commit that we
could add as a "Fixes:" tag so we know how far back to try to apply
to stable kernels?
> To: Bjorn Helgaas
> To: Joerg Roedel
> To: Lu Baolu
> Cc: sta...@vger.kernel.org
> Cc: linux-...@vger.kernel.
[+cc Puranjay, for LTR issues, original posting at
https://lore.kernel.org/r/20200706070259.32565-1-ricky...@realtek.com]
I've complained about some of this stuff before, but we haven't really
made any progress yet:
On Fri, Jul 17, 2020 at 10:43:18AM -0400, Sasha Levin wrote:
> On Fri, Jul 17, 2020 at 02:43:52AM +0200, Karol Herbst wrote:
> > On Fri, Jul 17, 2020 at 1:54 AM Bjorn Helgaas wrote:
> > > On Fri, Jul 17, 2020 at 12:10:39AM +0200, Karol Herbst wrote:
> > > > On Tue
From: Bjorn Helgaas
This reverts commit ec411e02b7a2e785a4ed9ed283207cd14f48699d.
Patrick reported that this commit broke hybrid graphics on a ThinkPad X1
Extreme 2nd with Intel UHD Graphics 630 and NVIDIA GeForce GTX 1650 Mobile:
nouveau :01:00.0: fifo: PBDMA0: 0100 [] ch 0
On Fri, Jul 17, 2020 at 03:59:25PM +0800, Xiongfeng Wang wrote:
> When I cat ASPM parameter 'policy' by sysfs, it displays as follows.
> It's better to add a newline for easy reading.
>
> [root@localhost ~]# cat /sys/module/pcie_aspm/parameters/policy
> [default] performance powersave
nge adds a global stub to DECLARE_PCI_FIXUP_SECTION to fix the
> issue when PREL32 relocations are used.
>
> Signed-off-by: Sami Tolvanen
Acked-by: Bjorn Helgaas
> ---
> include/linux/pci.h | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --g
On Fri, Jul 17, 2020 at 10:55:28AM +0800, Wei Hu wrote:
> Kdump could fail sometime on HyperV guest over Accerlated Network
> interface. This is because the retry in hv_pci_enter_d0() relies on
> an asynchronous host event to arrive guest before calling
> hv_send_resources_allocated(). This fixes
[+cc Sasha -- stable kernel regression]
[+cc Patrick, Kai-Heng, LKML]
On Fri, Jul 17, 2020 at 12:10:39AM +0200, Karol Herbst wrote:
> On Tue, Jul 7, 2020 at 9:30 PM Karol Herbst wrote:
> >
> > Hi everybody,
> >
> > with the mentioned commit Nouveau isn't able to load firmware onto the
> > GPU on
On Thu, Jul 16, 2020 at 04:10:52PM -0500, Gustavo A. R. Silva wrote:
> Replace the existing /* fall through */ comments and its variants with
> the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> fall-through markings when it is the case.
>
> [1]
>
On Thu, Jul 16, 2020 at 05:06:19PM +0800, Yicong Yang wrote:
> On 2020/7/11 7:09, Bjorn Helgaas wrote:
> > On Sat, Jun 13, 2020 at 05:32:13PM +0800, Yicong Yang wrote:
> >> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex
> >> integrated Endpoi
On Wed, Jul 15, 2020 at 07:55:11PM -0700, Randy Dunlap wrote:
> On 7/13/20 11:23 PM, David E. Box wrote:
> > Add PCIe DVSEC extended capability ID and defines for the header offsets.
> > Defined in PCIe r5.0, sec 7.9.6.
> >
> > Signed-off-by: David E. Box
On Wed, Jul 15, 2020 at 02:38:29PM +, David Laight wrote:
> From: Oliver O'Halloran
> > Sent: 15 July 2020 05:19
> >
> > On Wed, Jul 15, 2020 at 8:03 AM Arnd Bergmann wrote:
> ...
> > > - config space accesses are very rare compared to memory
> > > space access and on the hardware side the
-- Forwarded message -
From: Patrick Volkerding
Date: Tue, Jul 14, 2020 at 2:22 PM
Subject: Hybrid graphics regression in 5.4.49+ [bisected]
To: Bjorn Helgaas , Mika Westerberg
Cc: Patrick Volkerding
Hello,
I ran into a problem recently with a laptop with hybrid graphics
[+cc Kjetil]
On Wed, Jul 15, 2020 at 12:01:56AM +0200, Arnd Bergmann wrote:
> On Tue, Jul 14, 2020 at 8:45 PM Bjorn Helgaas wrote:
> > On Mon, Jul 13, 2020 at 05:08:10PM +0200, Arnd Bergmann wrote:
> > > On Mon, Jul 13, 2020 at 3:22 PM Saheed O. Bolarinwa
> > >
On Thu, Jun 04, 2020 at 02:50:01PM -0700,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan
>
> Fatal (DPC) error recovery is currently broken for non-hotplug
> capable devices. With current implementation, after successful
> fatal error recovery, non-hotplug
y: Shiju Jose
OK by me unless Lorenzo has any comments.
Acked-by: Bjorn Helgaas
Looks like Rafael is willing to merge it?
> --
> drivers/pci/controller/Kconfig | 8 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-hisi-error.c | 336 ++
On Mon, Jul 13, 2020 at 03:09:00PM +0100, Shiju Jose wrote:
> CPER records describing a firmware-first error are identified by GUID.
Does the spec really connect "firmware-first" and CPER records? Are
there non-firmware-first CPER records?
This sentence suggests that firmware-first CPER records
The subject suggests that currently we create NUMA nodes from SRAT
*and* other sources, and that this patch will remove the other
sources. Is that right?
On Mon, Jul 13, 2020 at 11:10:18PM +0800, Jonathan Cameron wrote:
> Here, I will use the term Proximity Domains for the ACPI description and
>
[trimmed the cc list; it's still too large but maybe arch folks care]
On Mon, Jul 13, 2020 at 05:08:10PM +0200, Arnd Bergmann wrote:
> On Mon, Jul 13, 2020 at 3:22 PM Saheed O. Bolarinwa
> wrote:
> > This goal of these series is to move the definition of *all*
> > PCIBIOS* from
On Tue, Jul 14, 2020 at 01:04:42PM +0200, Saheed Olayemi Bolarinwa wrote:
> From: Bolarinwa Olayemi Saheed
> ...
> Bolarinwa Olayemi Saheed (14):
> IB/hfi1: Check the return value of pcie_capability_read_*()
> misc: rtsx: Check the return value of pcie_capability_read_*()
> ath9k: Check
-by: Giovanni Cabiddu
Acked-by: Bjorn Helgaas
> ---
> include/linux/pci_ids.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 0ad57693f392..f3166b1425ca 100644
> --- a/include/linux/pci_ids.h
&g
On Mon, Jul 13, 2020 at 12:01:51PM +0200, Hans Verkuil wrote:
> On 29/06/2020 09:36, Vaibhav Gupta wrote:
> > The .suspend() and .resume() callbacks are not defined for this driver.
> > Still, their power managemgement stucture can be easily upgraded to
>
> management structure
>
> > gemeric,
On Sat, Jul 11, 2020 at 05:08:51PM -0700, Rajat Jain wrote:
> On Sat, Jul 11, 2020 at 12:53 PM Bjorn Helgaas wrote:
> > On Fri, Jul 10, 2020 at 03:53:59PM -0700, Rajat Jain wrote:
> > > On Fri, Jul 10, 2020 at 2:29 PM Raj, Ashok wrote:
> > > > On Fri, Jul 10, 2
On Fri, Jul 10, 2020 at 03:53:59PM -0700, Rajat Jain wrote:
> On Fri, Jul 10, 2020 at 2:29 PM Raj, Ashok wrote:
> > On Fri, Jul 10, 2020 at 03:29:22PM -0500, Bjorn Helgaas wrote:
> > > On Tue, Jul 07, 2020 at 03:46:04PM -0700, Rajat Jain wrote:
> > > > When en
On Fri, Jul 10, 2020 at 03:53:59PM -0700, Rajat Jain wrote:
> On Fri, Jul 10, 2020 at 2:29 PM Raj, Ashok wrote:
> > On Fri, Jul 10, 2020 at 03:29:22PM -0500, Bjorn Helgaas wrote:
> > > On Tue, Jul 07, 2020 at 03:46:04PM -0700, Rajat Jain wrote:
> > > > When en
On Sat, Jun 13, 2020 at 05:32:13PM +0800, Yicong Yang wrote:
> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex
> integrated Endpoint(RCiEP) device, providing the capability
> to dynamically monitor and tune the PCIe traffic parameters(tune),
> and trace the TLP headers to the
From: Bjorn Helgaas
acpi_pci_osc_control_set() is called only inside pci_root.c and there's no
need for it to be called by modules. Make it static and unexport it.
Signed-off-by: Bjorn Helgaas
---
drivers/acpi/pci_root.c | 4 ++--
include/linux/acpi.h| 3 ---
2 files changed, 2
From: Bjorn Helgaas
Unexport a couple functions that are no longer needed by modules.
Bjorn Helgaas (2):
PCI/ACPI: Unexport acpi_pci_osc_control_set()
PCI/ACPI: Unexport acpi_pci_find_root()
drivers/acpi/pci_root.c | 5 ++---
include/linux/acpi.h| 3 ---
2 files changed, 2 insertions
From: Bjorn Helgaas
acpi_pci_find_root() is called only from pci_root.c and
drivers/pci/hotplug/acpi_pcihp.c, neither of which can be modules.
Unexport it.
Signed-off-by: Bjorn Helgaas
---
drivers/acpi/pci_root.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/acpi/pci_root.c b
On Thu, May 28, 2020 at 08:47:12PM +0200, Heiner Kallweit wrote:
> Currently, if both resource types are enabled before the call, the mask
> value doesn't matter. Means as of today I wouldn't be able to e.g.
> disable PCI_COMMAND_IO. At least my interpretation is that mask defines
> which resource
On Wed, Jun 10, 2020 at 04:07:35AM +, Z.q. Hou wrote:
> Hi Kuppuswamy,
>
> Thanks a lot for your comments and sorry for my late response!
>
> > -Original Message-
> > From: Kuppuswamy, Sathyanarayanan
> >
> > Sent: 2020年5月29日 12:25
> > To: Z.q. Hou ; linux-...@vger.kernel.org;
> >
On Wed, May 27, 2020 at 09:13:22PM -0500, wu000...@umn.edu wrote:
> From: Qiushi Wu
>
> kobject_init_and_add() takes reference even when it fails.
> If this function returns an error, kobject_put() must be called to
> properly clean up the memory associated with the object. Thus,
> when call of
On Tue, Jul 07, 2020 at 03:46:01PM -0700, Rajat Jain wrote:
> Move pci_enable_acs() and the functions it depends on, further up in the
> source code to avoid having to forward declare it when we make it static
> in near future (next patch).
>
> No functional changes intended.
>
> Signed-off-by:
On Tue, Jul 07, 2020 at 03:46:04PM -0700, Rajat Jain wrote:
> When enabling ACS, enable translation blocking for external facing ports
> and untrusted devices.
>
> Signed-off-by: Rajat Jain
> ---
> v4: Add braces to avoid warning from kernel robot
> print warning for only external-facing
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