Hi, Yongqiang:
On Mon, 2021-04-12 at 16:45 +0800, Yongqiang Niu wrote:
> On Mon, 2021-04-12 at 16:28 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> > > gamma lut set in vsync active will caused display f
Hi, Yongqiang:
On Mon, 2021-04-12 at 15:25 +0800, Yongqiang Niu wrote:
> the orginal formula will caused rdma fifo threshold config overflow
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> gamma lut set in vsync active will caused display flash issue
> set gamma lut with cmdq
In MT8173, it's ok to set gammma out of vblank period. Why do you
setting gamma in vblank in this patch?
Regards,
CK
>
>
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> mt8183 aal has no gamma function
Separate this patch to two patch: one is add has_gamma config in aal.
another one is add mt8183 aal support.
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
>
Hi, Jitao:
On Tue, 2021-03-30 at 23:53 +0800, Jitao Shi wrote:
> Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
> the possible output and input formats for the current mode and monitor,
> and use the negotiated formats in a basic atomic_check callback.
>
>
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> add support for mediatek SOC MT8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqi
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Fix setting to follow hardware datasheet. The original error setting
> affects mt8192 display.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi W
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> ccorr ctm matrix bits will be different in mt8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/
Hi, Hsin-Yi:
It looks like that postmask driver could be placed in mtk_drm_ddp_comp.c
and this patch would much smaller.
Regards,
CK
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu
>
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
>
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/m
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
>
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/m
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
> wrote:
> >
> > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > On Thu,
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > for 5 or 6 bpc panel,
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Signed-off-by:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
ponents (dither,
> gamma) can call this function.
Reviewed-by: CK Hu
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 de
On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > Modify the title's prefix to 'soc: mediatek:'
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > >
On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
>
> Modify the title's prefix to 'soc: mediatek:'
Modify more, the title should be 'soc: mediatek: add mtk mutex support
for MT8183'
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqi
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> 1. add ovl private data
> 2. add rdma private data
> 3. add gamma privte data
> 4. add main and external path module for crtc create
Reviewed-by: CK Hu
>
> Signed-off-by:
Hi, Hsin-Yi:
Modify the title's prefix to 'soc: mediatek:'
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add DDP support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
>
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
>
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Not all SoC has dither function in gamma module.
> Add private data to control this function setting.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed
On Thu, 2021-01-28 at 13:09 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 12:39 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > There may be data structure other than mtk_ddp_comp_dev that would
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> There may be data structure other than mtk_ddp_comp_dev that would call
> mtk_dither_set(), so use regs as parameter instead of device.
You does not change the interface of mtk_dither_set(). You move the
common part in
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add RDMA fifo size error handle
> rdma fifo size will not always bigger than the calculated threshold
> if that case happened, we need set fifo size as the threshold
>
> Signed-off-by:
Hi, Enric:
On Fri, 2020-11-27 at 11:49 +0100, Enric Balletbo i Serra wrote:
> Add display subsystem device nodes to allow video output.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++
> 1 file changed, 114
@@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaT
Hi, Chunfeng:
On Thu, 2020-09-03 at 11:34 +0800, Chunfeng Yun wrote:
> From: CK Hu
>
> add support runtime pm feature
>
> Signed-off-by: Zhanyong Wang
> Signed-off-by: Chunfeng Yun
> ---
> drivers/usb/host/xhci-mtk.c | 446
> +
Hi, Linus:
On Thu, 2020-08-27 at 10:52 +0200, Linus Walleij wrote:
> On Mon, Aug 17, 2020 at 2:18 AM Zhiyong Tao wrote:
>
> > This series includes 3 patches:
> > 1.add pinctrl file on mt8192.
> > 2.add pinctrl binding document on mt8192.
> > 3.add pinctrl driver on MT8192.
>
> Patches applied
Hi, Chih-En:
On Wed, 2020-08-26 at 14:21 +0800, Chih-En Hsu wrote:
> This patch is to remove function "mtk_reg_write" since
> Mediatek EFUSE hardware only supports read functionality
> for NVMEM consumers.
>
Reviewed-by: CK Hu
> Fixes: 4c7e4fe37766 ("nvmem: media
Hi, Chih-En:
On Wed, 2020-08-26 at 13:01 +0800, Chih-En Hsu wrote:
> This patch is to remove function "mtk_reg_write" since
> Mediatek EFUSE hardware only supports read functionality
> for NVMEM consumers.
>
This is a bug-fix patch, so need a 'Fixes' tag. You could refer to [1].
[1]
Hi, Seiya:
On Wed, 2020-07-29 at 16:02 +0800, CK Hu wrote:
> Hi, Seiya:
>
> On Wed, 2020-07-29 at 09:30 +0800, Seiya Wang wrote:
> > Add basic chip support for Mediatek MT8192
> >
> > Signed-off-by: Seiya Wang
> > ---
> > arch/arm64/boot/dts/mediatek
Hi, Seiya:
On Wed, 2020-07-29 at 09:30 +0800, Seiya Wang wrote:
> Add basic chip support for Mediatek MT8192
>
> Signed-off-by: Seiya Wang
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++
>
+ Tiffany & Maoguang.
On Sat, 2020-05-30 at 16:10 +0800, Yong Wu wrote:
> MediaTek IOMMU has already added the device_link between the consumer
> and smi-larb device. If the vcodec device call the pm_runtime_get_sync,
> the smi-larb's pm_runtime_get_sync also be called automatically.
>
> CC:
+ Tiffany & Maoguang.
On Sat, 2020-05-30 at 16:10 +0800, Yong Wu wrote:
> From: Maoguang Meng
>
> MTK H264 Encoder(VENC_SYS) and VP8 Encoder(VENC_LT_SYS) are two
> independent hardware instance. They have their owner interrupt,
> register mapping, and special clocks.
>
> This patch seperates
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
I've rewrite this patch and applied to mediatek-drm-next-5.5 [1] with
the title "drm/mediatek: add no_clk into ddp private data",
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_
Hi, Bibby:
On Fri, 2019-09-27 at 19:42 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: CK Hu
You've modified this patch in t
V_ROUND_UP_ULL
> - use div_u64 when 80ULL / dsi->data_rate.
>
> Changes since v3
> - add one more 'tab' for bitwise define.
> - add Tested-by: Ryan Case
> and Reviewed-by: CK Hu .
> - remove compare da_hs_zero to da_hs_prepare.
>
> Changes since v
Hi, Jitao:
For this series, applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
On Wed, 2019-08-07 at 16:46 +0800, Jitao Shi wrote:
> Change since v5:
> - remove mipi_tx->ref_clk
> - remove mt8183 pll
Hi, Bibby:
On Fri, 2019-08-30 at 15:38 +0800, Bibby Hsieh wrote:
> Currently we use a single mutex to allow only a single atomic
> update at a time. In truth, though, we really only want to
> ensure that only a single atomic update is allowed per CRTC.
>
> In other words, for each atomic update,
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from DITHER0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to COLOR0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32
Hi, Matthias:
On Thu, 2019-08-29 at 09:19 +0200, Matthias Brugger wrote:
>
> On 01/07/2019 10:57, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> >> Add power controller node and smi-common node for MT8183
> &
Hi, Weiyi:
On Wed, 2019-08-28 at 17:11 +0800, Weiyi Lu wrote:
> Add power controller node and smi-common node for MT8183
> In scpsys node, it contains clocks and regmapping of
> infracfg and smi-common for bus protection.
>
> Signed-off-by: Weiyi Lu
> ---
>
Hi, Bibby:
On Tue, 2019-08-20 at 16:36 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: CK Hu
> ---
> drivers/soc/media
Hi, Bibby:
On Mon, 2019-08-19 at 10:53 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-
Hi, Weiyi:
On Tue, 2019-07-23 at 12:06 +0800, Weiyi Lu wrote:
> On Tue, 2019-07-16 at 09:50 +0800, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Mon, 2019-07-15 at 17:07 +0800, Weiyi Lu wrote:
> > > On Mon, 2019-07-15 at 16:07 +0800, CK Hu wrote:
> > > > Hi,
Hi, Weiyi:
On Mon, 2019-07-15 at 17:07 +0800, Weiyi Lu wrote:
> On Mon, 2019-07-15 at 16:07 +0800, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Mon, 2019-07-01 at 16:57 +0800, CK Hu wrote:
> > > Hi, Weiyi:
> > >
> > > On Thu, 2019-06-20 at 10:38 +08
Hi, Macpaul:
On Fri, 2019-07-12 at 17:43 +0800, Macpaul Lin wrote:
> From: Mars Cheng
>
> Add basic chip support for Mediatek 6765, include
> uart node with correct uart clocks, pwrap device
>
> Add clock controller nodes, include topckgen, infracfg,
> apmixedsys and subsystem.
>
>
Hi, Weiyi:
On Mon, 2019-07-01 at 16:57 +0800, CK Hu wrote:
> Hi, Weiyi:
>
> On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> > Add power controller node and smi-common node for MT8183
> > In scpsys node, it contains clocks and regmapping of
> > infracfg and sm
Hi, Weiyi:
On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> Add power controller node and smi-common node for MT8183
> In scpsys node, it contains clocks and regmapping of
> infracfg and smi-common for bus protection.
>
> Signed-off-by: Weiyi Lu
> ---
>
Hi, Bibby:
On Mon, 2019-07-01 at 15:48 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
Reviewed-by: CK Hu
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-
Hi, Derek:
On Fri, 2019-06-21 at 20:41 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
er pixel
>
> Signed-off-by: Jitao Shi
> Tested-by: Ryan Case
> Reviewed-by: CK Hu
This version is different than previous version, so you should remove
Reviewed-by tag. For this version, I still give you a
Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 117 +++
Hi, Jitao:
On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
This version is different than previous version, so yo
Hi, Bibby:
On Thu, 2019-06-27 at 14:19 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
>
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
In the binding document [1], clock is required property. In this patch,
you change it to optional property. I think you should change
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these
Hi, Bibby:
On Wed, 2019-06-12 at 16:53 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
>
Hi, Stu:
"mediatek,mt2712-mipicsi" and "mediatek,mt2712-mipicsi-common" have many
common part with "mediatek,mt8183-seninf", and I've a discussion in [1],
so I would like these two to be merged together.
[1] https://patchwork.kernel.org/patch/10979131/
Regards,
CK
On Tue, 2019-06-04 at 18:11
tion is defualt on. But this driver doesn't use this
> function. So add the disable control.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/
Hi, Jitao:
On Sun, 2019-05-19 at 17:25 +0800, Jitao Shi wrote:
> mtk_mipi_tx is the phy of mtk_dsi.
> mtk_dsi get the phy(mtk_mipi_tx) in probe().
>
> So, mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
> defer to wait mtk_mipi_tx probe done.
Reviewed-by: CK Hu
Hi, Hsin-Yi:
On Tue, 2019-05-28 at 15:39 +0800, Hsin-Yi Wang wrote:
> mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), which
> needs
> ovl irq for drm_crtc_wait_one_vblank(), since after mtk_dsi_stop() is called,
> ovl irq will be disabled. If drm_crtc_wait_one_vblank() is
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +
>
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> According to the cmdq hardware design, the subsys is u8,
> the offset is u16 and the event id is u16.
> This patch changes the type of subsys, offset and event id
> to the correct type.
Reviewed-by: CK Hu
>
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> The order of instructions gce knowed is [subsys offset value]
> so reorder the parameter of cmdq_pkt_write_mask
> and cmdq_pkt_write function.
>
Except the word 'knowed',
Reviewed-by: CK Hu
> Signed-off-
On Sun, 2019-05-19 at 17:36 +0800, Jitao Shi wrote:
> On Tue, 2019-05-07 at 17:52 +0800, CK Hu wrote:
> > Hi, Jitao:
> >
> > On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> > > DSI panel driver need attach function which is incu
Hi, Stu:
On Tue, 2019-05-14 at 14:13 +0800, Stu Hsieh wrote:
> This patch add ISR for writing the data to buffer
>
> When mipicsi HW complete to write the data in buffer,
> the interrupt woulb be trigger.
> So, the ISR need to clear interrupt status for next interrupt.
>
> Signed-off-by: Stu
Hi, Stu:
On Tue, 2019-05-14 at 14:13 +0800, Stu Hsieh wrote:
> This patch add mediatek mipicsi driver for mt2712,
> including probe function to get the value from device tree,
> and register to v4l2 the host device.
>
> Signed-off-by: Stu Hsieh
> ---
>
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> Define a instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 113
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> tcmdq driver provide a function that get the relationship
What is 'tcmdq'?
> of sub system number from device node for client.
> add specification for #subsys-cells, mediatek,gce-subsys.
The property name is
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the relationship of subsys
> and register base address.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 25
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> When client ask gce to clear or wait for event,
> client need to pass event number to the API.
> We suggest client store the event information in device node,
> so we provide an API for client parse the event property.
>
>
Hi, Bibby:
On Fri, 2019-05-10 at 11:27 +0800, Bibby Hsieh wrote:
> Hi, CK,
>
> On Wed, 2019-05-08 at 13:10 +0800, CK Hu wrote:
> > Hi, Bibby:
> >
> > On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> > > Client hardware would send event to GCE hard
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> add polling function in cmdq helper functions
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 29
> include/linux/mailbox/mtk-c
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> Define a instruction structure for gce driver to append command.
I would like you to describe _WHY_ do this. I think you do this for
'code readability'.
>
> Signed-off-by: Bibby Hsieh
> ---
>
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> Client hardware would send event to GCE hardware,
> mediatek,gce-event-names and mediatek,gce-events
> can be used to present the event.
>
> Signed-off-by: Bibby Hsieh
> ---
>
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> tcmdq driver provide a function that get the relationship
> of sub system number from device node for client.
> add specification for #subsys-cells, mediatek,gce-subsys.
>
> Signed-off-by: Bibby Hsieh
> ---
>
Hi, Jitao:
On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more delay.
I think this patch just prevent delay, not to prevent dsi
Hi, Jitao:
On Tue, 2019-04-16 at 13:52 +0800, Jitao Shi wrote:
I need the commit message. Even though the code is easy to understand,
words for this patch is still necessary.
Regards,
CK
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++
> 1 file
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> Implement a function can encode the GCE instructions
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 125 ---
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
>
o wait event but not really trigger the
> corresponding hardware.
>
> In order to make sure that the wait event function is
> exactly correct, we need to clear the sysram value in
> cmdq initial flow.
>
> Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver&q
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> add mt8183 compatible name for supporting gce function
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> The interrupt mask and thread number has positive correlation,
> so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate
> it by thread number.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
&
Hi, Stu:
On Tue, 2019-04-16 at 17:30 +0800, Stu Hsieh wrote:
> This patch add mediatek mipicsi driver for mt2712,
> including probe function to get the value from device tree,
> and register to v4l2 the host device.
>
> Signed-off-by: Stu Hsieh
> ---
>
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: chunhui dai
>
> Recalculate the rate of this clock, by querying hardware.
You just describe _WHAT_ do you do here, I would like you to describe
_WHT_ do you do here. I think this patch is to make implementation of
recalc_rate() to
Hi, Wangyan:
On Wed, 2019-03-06 at 18:13 +0800, CK Hu wrote:
> Hi, Wangyan:
>
> On Mon, 2019-02-25 at 10:09 +0800, wangyan wang wrote:
> > From: chunhui dai
> >
> > We should not change the rate of parent for hdmi phy when
> > doing round_rate for this clock.
Hi, Bibby:
On Wed, 2019-03-06 at 17:50 +0800, Bibby Hsieh wrote:
> cmdq driver provide a function that get event number
> from device node for client.
I think device tree is based on the view of hardware design, so you need
not to mention how the driver design.
Client hardware would send event
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