Hi Abel,
On 17.11.20 15:48, Abel Vesa wrote:
On 20-11-11 17:13:25, Dong Aisheng wrote:
On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa wrote:
...
+static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct
On 22.02.21 16:08, Schrempf Frieder wrote:
From: Frieder Schrempf
This fixes the return value of pca9450_i2c_probe() to use the correct
error code when getting the sd-vsel GPIO fails.
Signed-off-by: Frieder Schrempf
Sorry, I just noticed, that the PR for v5.12 was already sent, but I
nd I guess this deserves a "Fixes" and "Cc: stable" tag, so:
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Cc: sta...@vger.kernel.org
Reviewed-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 +-
1 file chan
On 30.11.20 12:44, Andy Shevchenko wrote:
On Mon, Nov 30, 2020 at 1:06 PM Schrempf Frieder
wrote:
From: Frieder Schrempf
There are other NXP NCI compatible NFC controllers such as the PN7150
that use an integrated firmware and therefore do not have a GPIO to
select firmware downloading mode
ve
tested this more properly.
Reviewed-by: Frieder Schrempf
---
v1 -> v2:
* Simplify commit message and error (Krzysztof).
* Pick up Krzysztof's tag.
arch/arm64/boot/dts/freescale/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale
or member '0'
not described in 'SPINAND_OP_VARIANTS'
Cc: Miquel Raynal
Cc: Richard Weinberger
Cc: Vignesh Raghavendra
Cc: Yoshio Furuyama
Cc: Frieder Schrempf
Cc: linux-...@lists.infradead.org
Signed-off-by: Lee Jones
Reviewed-by: Frieder Schrempf
---
drivers/mtd/nand/spi/toshiba.c | 2
On 01.10.20 15:30, Frieder Schrempf wrote:
On 01.10.20 14:57, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM
On 01.10.20 14:57, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards
On 01.10.20 14:59, Krzysztof Kozlowski wrote:
On Thu, Oct 01, 2020 at 02:06:59PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf
Reviewed-by: Rob Herring
---
Changes
On 01.10.20 14:34, Schrempf Frieder wrote:
From: Frieder Schrempf
In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
Signed-off-by: Frieder
On 01.10.20 14:53, Mark Brown wrote:
On Thu, Oct 01, 2020 at 02:34:31PM +0200, Schrempf Frieder wrote:
+ pca9450->sd_vsel_gpio = gpiod_get_optional(pca9450->dev, "sd-vsel",
GPIOD_OUT_HIGH);
We need a patch adding this to the binding document too.
Right, totally forgot about that.
On 01.10.20 14:34, Schrempf Frieder wrote:
From: Frieder Schrempf
In order to use ultra high speed modes (UHS) on the SD card slot, we
add matching pinctrls and fix the voltage switching for LDO5 of the
PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
Signed-off-by: Frieder
On 17.08.20 10:51, Shawn Guo wrote:
On Thu, Jul 16, 2020 at 06:11:58PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have
On 10.08.20 12:57, Robin Gong wrote:
On 2020/08/10 15:33 Frieder Schrempf wrote:
Hi Robin,
This patch seems to break UART DMA in case the ROM firmware is used. In that
case sdma->script_number is set to SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1, so
the ROM scripts at uart_2_mcu_a
Hi Robin,
On 24.07.20 20:51, Robin Gong wrote:
For the compatibility of NXP internal legacy kernel before 4.19 which
is based on uart ram script and upstreaming kernel based on uart rom
script, add both uart ram/rom script in latest sdma firmware. By default
uart rom script used.
Besides, add
On 23.07.20 13:12, Robin Gong wrote:
On 2020/07/23 17:04 Frieder Schrempf
wrote:
Hi Robin,
On 30.06.20 15:31, Robin Gong wrote:
Add 'fw_loaded' and 'is_ram_script' to check if the script used by
channel is ram script and it's loaded or not, so that could prevent
meaningless following malloc
Hi Robin,
On 30.06.20 15:31, Robin Gong wrote:
Add 'fw_loaded' and 'is_ram_script' to check if the script used by channel
is ram script and it's loaded or not, so that could prevent meaningless
following malloc dma descriptor and bd allocate in sdma_transfer_init(),
otherwise memory may be
On 15.07.20 21:06, Geert Uytterhoeven wrote:
On Mon, Jul 13, 2020 at 5:11 PM Mark Brown wrote:
On Mon, Jul 13, 2020 at 03:19:52PM +0200, Frieder Schrempf wrote:
I would have expected that there is some kind of existing userspace API to
load an overlay manually, but it seems like there isn't
On 15.07.20 15:10, Mark Brown wrote:
On Wed, Jul 15, 2020 at 01:45:51PM +0200, Frieder Schrempf wrote:
On 15.07.20 13:36, Mark Brown wrote:
Hey, I proposed other solutions you didn't want to implement!
Right, but you have to admit that the other solutions turned out to be
rather out
On 15.07.20 13:36, Mark Brown wrote:
On Wed, Jul 15, 2020 at 09:26:29AM +0200, Frieder Schrempf wrote:
On 14.07.20 21:29, Mark Brown wrote:
On Tue, Jul 14, 2020 at 10:54:15AM +0200, Frieder Schrempf wrote:
patch in our own tree, or if a node with a custom compatible string like for
example
On 14.07.20 21:29, Mark Brown wrote:
On Tue, Jul 14, 2020 at 10:54:15AM +0200, Frieder Schrempf wrote:
It would still be quite nice to benefit from the flexibility of DT overlays
not only for the SPI use case. But before I come up with any custom
solution, for now I will rather have the device
On 13.07.20 17:11, Mark Brown wrote:
On Mon, Jul 13, 2020 at 03:19:52PM +0200, Frieder Schrempf wrote:
I would have expected that there is some kind of existing userspace API to
load an overlay manually, but it seems like there isn't!?
So what's the reasoning behind this? How can I solve
On 02.07.20 18:24, Frieder Schrempf wrote:
On 02.07.20 17:07, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:46:09PM +0200, Frieder Schrempf wrote:
My intention is to use the spidev driver in the default board DT for an
interface that is routed to an extension connector and has no dedicated
On 03.07.20 18:19, Robin Gong wrote:
Add NXP pca9450 pmic driver.
Signed-off-by: Robin Gong
Reviewed-by: Frieder Schrempf
---
drivers/regulator/Kconfig | 8 +
drivers/regulator/Makefile| 1 +
drivers/regulator/pca9450-regulator.c | 843
Hi Marcel,
On 03.07.20 09:56, Marcel Ziswiler wrote:
Hi Frieder
Nice to see some more i.MX 8M Mini action. Much appreciated!
On Thu, 2020-07-02 at 16:33 +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8MM
On 02.07.20 17:07, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:46:09PM +0200, Frieder Schrempf wrote:
My intention is to use the spidev driver in the default board DT for an
interface that is routed to an extension connector and has no dedicated
slave device attached onboard. So users can
Hi Geert,
On 02.07.20 16:57, Geert Uytterhoeven wrote:
Hi Frieder,
On Thu, Jul 2, 2020 at 4:46 PM Frieder Schrempf
wrote:
On 02.07.20 16:25, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:18:46PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Allow external SPI ports on Kontron
On 02.07.20 16:25, Mark Brown wrote:
On Thu, Jul 02, 2020 at 04:18:46PM +0200, Schrempf Frieder wrote:
From: Frieder Schrempf
Allow external SPI ports on Kontron boards to use the spidev driver.
I'd have expected this to require loading a DT overlay for whatever's
attached?
My intention
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
From: Frieder Schrempf
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Frieder Schrempf
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Frieder Schrempf
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files
From: Frieder Schrempf
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |9
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
From: Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65
.../devicetree/bindings/spi/spi-fsl-qspi.txt
From: Frieder Schrempf
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files
From: Frieder Schrempf
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |9
From: Frieder Schrempf
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1
From: Frieder Schrempf
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
.../devicetree/bindings/mtd/fsl-quadspi.txt | 65
.../devicetree/bindings/spi/spi-fsl-qspi.txt
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never read by the
driver a
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'num-cs' and 'bus-num' were never read by the
driver a
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi
From: Frieder Schrempf
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chi
From: Frieder Schrempf
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
The "old" driver was using the "fsl,qspi-has-second-chip" property to
select one of two dual chip setups (two chips on one bus or two chi
From: Frieder Schrempf
The FSL QSPI driver was moved to the SPI framework and it now
acts as a SPI controller. Therefore the subnodes need to set
spi-[rx/tx]-bus-width = <4>, so quad mode is used just as before.
Also the properties 'bus-num', 'fsl,spi-num-chipselects' and
'fsl,spi
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic
Some SOCs in the i.MX6 family have a USB host controller that is
only capable of the HSIC interface and has no on-board PHY.
To be able to use these controllers, we need to add "usb-nop-xceiv"
dummy PHYs.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6qdl
Some SOCs in the i.MX6 family have a USB host controller that is
only capable of the HSIC interface and has no on-board PHY.
To be able to use these controllers, we need to add "usb-nop-xceiv"
dummy PHYs.
Signed-off-by: Frieder Schrempf
---
arch/arm/boot/dts/imx6qdl
Hi Quentin,
On 09.10.2018 09:52, Quentin Schulz wrote:
Hi Frieder,
On Mon, Oct 08, 2018 at 11:53:21AM +0200, Frieder Schrempf wrote:
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi
Hi Quentin,
On 09.10.2018 09:52, Quentin Schulz wrote:
Hi Frieder,
On Mon, Oct 08, 2018 at 11:53:21AM +0200, Frieder Schrempf wrote:
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
I'd like to know if any progress has been made on that problem
(I
Hi,
On 27.09.2018 10:14, Maxime Ripard wrote:
On Wed, Sep 26, 2018 at 10:19:22PM +0200, Hans de Goede wrote:
On 26-09-18 16:44, Frieder Schrempf wrote:
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
I'd like to know if any progress has been made on that problem
(I
Hi Boris,
On 29.09.2018 17:40, Boris Brezillon wrote:
Hi Yogesh,
On Fri, 21 Sep 2018 15:51:59 +0530
Yogesh Gaur wrote:
+/* Registers used by the driver */
+#define FSPI_MCR0 0x00
+#define FSPI_MCR0_AHB_TIMEOUT_SHIFT24
+#define FSPI_MCR0_AHB_TIMEOUT_MASK (0xFF <<
Hi Boris,
On 29.09.2018 17:40, Boris Brezillon wrote:
Hi Yogesh,
On Fri, 21 Sep 2018 15:51:59 +0530
Yogesh Gaur wrote:
+/* Registers used by the driver */
+#define FSPI_MCR0 0x00
+#define FSPI_MCR0_AHB_TIMEOUT_SHIFT24
+#define FSPI_MCR0_AHB_TIMEOUT_MASK (0xFF <<
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
>> > I'd like to know if any progress has been made on that problem
(I may
>> > have missed patches).
>> > Had you had the time to look at the issue?
>>
>> I have looked at the issue, but not manage to cook some patches
Hi,
On Fri, Feb 09, 2018 at 03:01:00PM +0100, Ulf Hansson wrote:
[...]
>> > I'd like to know if any progress has been made on that problem
(I may
>> > have missed patches).
>> > Had you had the time to look at the issue?
>>
>> I have looked at the issue, but not manage to cook some patches
On 26.09.2018 06:53, Chen-Yu Tsai wrote:
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.
This patch enables the SPI controller and adds a device node
for the flash chip using the
On 26.09.2018 06:53, Chen-Yu Tsai wrote:
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.
This patch enables the SPI controller and adds a device node
for the flash chip using the
Hi Marek, hi Boris,
On 09.07.2018 23:34, Boris Brezillon wrote:
+Fabio
Hi Yogesh,
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
Some SPI controllers can't write nor->page_size bytes in a single
step because their TX FIFO is too small.
Allow nor->write() to return a size that is
Hi Marek, hi Boris,
On 09.07.2018 23:34, Boris Brezillon wrote:
+Fabio
Hi Yogesh,
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
Some SPI controllers can't write nor->page_size bytes in a single
step because their TX FIFO is too small.
Allow nor->write() to return a size that is
Hi Yogesh,
I have some remarks about your general approach that came to me when
looking at the FSPI driver with the things at the back of my mind, that
I've learned from working at the FSL QSPI driver.
On 17.09.2018 11:48, Yogesh Gaur wrote:
- Add a driver for NXP FlexSPI host controller
Hi Yogesh,
I have some remarks about your general approach that came to me when
looking at the FSPI driver with the things at the back of my mind, that
I've learned from working at the FSL QSPI driver.
On 17.09.2018 11:48, Yogesh Gaur wrote:
- Add a driver for NXP FlexSPI host controller
Hi Boris, Yogesh,
On 17.09.2018 13:37, Boris Brezillon wrote:
Hi Yogesh,
On Mon, 17 Sep 2018 15:18:26 +0530
Yogesh Gaur wrote:
+
+ /*
+* R/W functions for big- or little-endian registers:
+* The FSPI controller's endianness is independent of
+* the CPU core's
Hi Boris, Yogesh,
On 17.09.2018 13:37, Boris Brezillon wrote:
Hi Yogesh,
On Mon, 17 Sep 2018 15:18:26 +0530
Yogesh Gaur wrote:
+
+ /*
+* R/W functions for big- or little-endian registers:
+* The FSPI controller's endianness is independent of
+* the CPU core's
Hi Yogesh,
On 05.09.2018 12:07, Yogesh Narayan Gaur wrote:
Hi Boris,
-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
Sent: Tuesday, September 4, 2018 8:29 PM
To: Yogesh Narayan Gaur
Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
Hi Yogesh,
On 05.09.2018 12:07, Yogesh Narayan Gaur wrote:
Hi Boris,
-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
Sent: Tuesday, September 4, 2018 8:29 PM
To: Yogesh Narayan Gaur
Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
Hi Boris, hi Mark,
On 02.08.2018 15:09, Boris Brezillon wrote:
On Thu, 2 Aug 2018 14:53:52 +0200
Frieder Schrempf wrote:
We usually try to avoid empty commit message, even if this one is
pretty obvious, I'd suggest adding something here.
"
Fix a typo in the @drvpriv descri
Hi Boris, hi Mark,
On 02.08.2018 15:09, Boris Brezillon wrote:
On Thu, 2 Aug 2018 14:53:52 +0200
Frieder Schrempf wrote:
We usually try to avoid empty commit message, even if this one is
pretty obvious, I'd suggest adding something here.
"
Fix a typo in the @drvpriv descri
Signed-off-by: Frieder Schrempf
---
include/linux/spi/spi-mem.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..72cc9bc 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
Signed-off-by: Frieder Schrempf
---
include/linux/spi/spi-mem.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 4fa34a2..72cc9bc 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when controller drivers are
ported from the MTD to the SPI layer.
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
for the memory device.
Example for the FSL QSPI driver:
Name with the old driver: 21e.qspi,
or with multiple devices: 21e.qspi-0, 21e.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
---
drivers
for the memory device.
Example for the FSL QSPI driver:
Name with the old driver: 21e.qspi,
or with multiple devices: 21e.qspi-0, 21e.qspi-1, ...
Name with the new driver without spi_mem_get_name: spi4.0
Suggested-by: Boris Brezillon
Signed-off-by: Frieder Schrempf
---
drivers
of the memory device in probe of m25p80
* Add Suggested-by tags
Changes in v2:
==
* Add a name field to struct spi_mem and fill it while probing
Frieder Schrempf (3):
spi: spi-mem: Fix a typo in the documentation of struct spi_mem
spi: spi-mem: Extend the SPI mem interface to set a custom
of the memory device in probe of m25p80
* Add Suggested-by tags
Changes in v2:
==
* Add a name field to struct spi_mem and fill it while probing
Frieder Schrempf (3):
spi: spi-mem: Fix a typo in the documentation of struct spi_mem
spi: spi-mem: Extend the SPI mem interface to set a custom
Hi Mark,
On 02.08.2018 12:17, Mark Brown wrote:
On Wed, Aug 01, 2018 at 09:57:33PM +0200, Boris Brezillon wrote:
Mark Brown wrote:
2/ Getting this patch [1] merged and implementing the ->get_name() hook
in this driver so that SPI NOR devs declared to the MTD layer keep
the same
Hi Mark,
On 02.08.2018 12:17, Mark Brown wrote:
On Wed, Aug 01, 2018 at 09:57:33PM +0200, Boris Brezillon wrote:
Mark Brown wrote:
2/ Getting this patch [1] merged and implementing the ->get_name() hook
in this driver so that SPI NOR devs declared to the MTD layer keep
the same
Hi Rob,
On 12.07.2018 17:20, Rob Herring wrote:
On Thu, Jul 12, 2018 at 2:14 AM Frieder Schrempf
wrote:
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver
Hi Rob,
On 12.07.2018 17:20, Rob Herring wrote:
On Thu, Jul 12, 2018 at 2:14 AM Frieder Schrempf
wrote:
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Bindings shouldn't change (other than new properties) due to driver
Hi Rob,
On 11.07.2018 18:05, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:01PM +0200, Frieder Schrempf wrote:
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Bindings shouldn't change (other than new properties) due to driver
Hi Rob,
On 11.07.2018 17:54, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:00PM +0200, Frieder Schrempf wrote:
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
Changes in v2
Hi Rob,
On 11.07.2018 17:54, Rob Herring wrote:
On Thu, Jul 05, 2018 at 01:15:00PM +0200, Frieder Schrempf wrote:
Move the documentation of the old SPI NOR driver to the place of the new
SPI memory interface based driver.
Signed-off-by: Frieder Schrempf
---
Changes in v2
Hi Boris,
On 05.07.2018 14:56, Boris Brezillon wrote:
On Thu, 5 Jul 2018 13:14:58 +0200
Frieder Schrempf wrote:
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when
Hi Boris,
On 05.07.2018 14:56, Boris Brezillon wrote:
On Thu, 5 Jul 2018 13:14:58 +0200
Frieder Schrempf wrote:
By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
set a custom name for the memory device if necessary.
This is useful to keep mtdparts compatible when
Hi Boris,
On 05.07.2018 14:39, Boris Brezillon wrote:
Hi Frieder,
On Thu, 5 Jul 2018 13:14:57 +0200
Frieder Schrempf wrote:
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility
Hi Boris,
On 05.07.2018 14:39, Boris Brezillon wrote:
Hi Frieder,
On Thu, 5 Jul 2018 13:14:57 +0200
Frieder Schrempf wrote:
When porting (Q)SPI controller drivers from the MTD layer to the SPI
layer, the naming scheme for the memory devices changes. To be able
to keep compatibility
-by: Frieder Schrempf
---
Changes in v2:
==
* Add Yogesh Gaur and Suresh Gupta as authors
* Use GENMASK() for generating bitmasks
* Use callback functions for read/write of registers
* Attach the seq variable to the selected CS
* Avoid using conditional in read/write loop
* Avoid infinite
-by: Frieder Schrempf
---
Changes in v2:
==
* Add Yogesh Gaur and Suresh Gupta as authors
* Use GENMASK() for generating bitmasks
* Use callback functions for read/write of registers
* Attach the seq variable to the selected CS
* Avoid using conditional in read/write loop
* Avoid infinite
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
==
* Split the moving and editing of the dt-bindings in two patches
.../devicetree/bindings/spi/spi-fsl-qspi.txt| 22
Adjust the documentation of the new SPI memory interface based
driver to reflect the new drivers settings.
Signed-off-by: Frieder Schrempf
---
Changes in v2:
==
* Split the moving and editing of the dt-bindings in two patches
.../devicetree/bindings/spi/spi-fsl-qspi.txt| 22
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files changed, 2 insertions
The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
at mtd/fsl-quadspi.c. Switch to the new driver in the defconfigs.
Signed-off-by: Frieder Schrempf
---
arch/arm/configs/imx_v6_v7_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 2 +-
2 files changed, 2 insertions
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
The driver was ported to the SPI framework so it can be used as
a generic SPI memory driver and not only for SPI NOR.
Reflect this transition in the MAINTAINERS file.
Signed-off-by: Frieder Schrempf
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
There's a new driver using the SPI memory interface of the SPI framework
at spi/spi-fsl-qspi.c, which can be used together with m25p80.c to
replace the functionality of this SPI NOR driver.
Signed-off-by: Frieder Schrempf
---
drivers/mtd/spi-nor/Kconfig |9 -
drivers/mtd/spi-nor
After switching to the new FSL QSPI driver the property
'fsl,qspi-has-second-chip' is not needed anymore.
The driver now uses the 'reg' property to determine the bus and
the chipselect.
Signed-off-by: Frieder Schrempf
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 -
1 file changed, 1
1 - 100 of 184 matches
Mail list logo
