Am Sonntag, 29. September 2019, 05:22:30 CEST schrieb Vivek Unune:
> Fix usb-c on X99 TV Box. Tested with armbian w/ kernel 5.3
>
> Signed-off-by: Vivek Unune
applied as fix for 5.4
Thanks
Heiko
Am Freitag, 4. Oktober 2019, 22:32:13 CEST schrieb Soeren Moch:
> According to the RockPro64 schematic [1] the rk3399 sdmmc controller is
> connected to a microSD (TF card) slot. Remove the cap-mmc-highspeed
> property of the sdmmc controller, since no mmc card can be connected here.
>
> [1]
Am Donnerstag, 3. Oktober 2019, 18:41:52 CEST schrieb Matthias Kaehlcke:
> Use interpolated brightness tables (added by commit 573fe6d1c25
> ("backlight: pwm_bl: Linear interpolation between
> brightness-levels") for veyron, instead of specifying every single
> step. Some devices/panels have
Am Mittwoch, 4. September 2019, 14:29:33 CEST schrieb YueHaibing:
> Use devm_platform_ioremap_resource() to simplify the code a bit.
> This is detected by coccinelle.
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
Reviewed-by: Heiko Stuebner
> ---
Hi Vivek,
Am Montag, 30. September 2019, 01:46:15 CEST schrieb Vivek Unune:
> On Sun, Sep 29, 2019 at 01:22:17PM +0200, Vicente Bergas wrote:
> > On Sunday, September 29, 2019 5:22:30 AM CEST, Vivek Unune wrote:
> > > Fix usb-c on X99 TV Box. Tested with armbian w/ kernel 5.3
> > >
> > >
Hi Sören,
Am Freitag, 4. Oktober 2019, 22:15:45 CEST schrieb Soeren Moch:
> Heiko,
>
> since you started to apply the first 2 Patches of this series (thanks
> for that!), now after all the discussions here (and the heads-up for the
> implemented mode detection) I think we should leave the
Am Donnerstag, 3. Oktober 2019, 23:50:35 CEST schrieb Soeren Moch:
> The RockPro64 schematics [1], [2] show that the rk3399 EMMC_STRB pin is
> connected to the RESET pin instead of the DATA_STROBE pin of the eMMC module.
> So the data strobe cannot be used for its intended purpose on this board,
>
Am Donnerstag, 3. Oktober 2019, 23:50:34 CEST schrieb Soeren Moch:
> The RockPro64 schematic [1] page 18 states a min voltage of 0.8V and a
> max voltage of 1.4V for the VDD_LOG pwm regulator. However, there is an
> additional note that the pwm parameter needs to be modified.
> From the schematics
Hi Katsuhiro,
Am Freitag, 4. Oktober 2019, 19:26:00 CEST schrieb Katsuhiro Suzuki:
> Past about 1 month, so I send a ping...
>
> On 2019/09/08 2:48, Katsuhiro Suzuki wrote:
> > This patch adds audio codec (Everest ES8316) and I2S audio nodes for
> > RK3399 RockPro64.
> >
> > Signed-off-by:
Am Dienstag, 17. September 2019, 10:36:25 CEST schrieb Heiko Stuebner:
> The rk3399 gic-its was missing the #msi-cells property as found by
> dt-schema checks, so add it.
>
> Signed-off-by: Heiko Stuebner
applied for 5.5
Am Donnerstag, 19. September 2019, 07:28:22 CEST schrieb Jagan Teki:
> Few, know rk808 pmic regulators VCC[1-4], VCC[6-7], VCC[9-11],
> VDD_LOG, VDD_GPU, VDD_CPU_B, VCC3V3_SYS are inputting with vcc_sys
> which is 5V power rail from dc_12v.
>
> So, replace the vin-supply of above mentioned
Am Donnerstag, 19. September 2019, 07:28:21 CEST schrieb Jagan Teki:
> It is always better practice to follow regulator naming conventions
> as per the schematics for future references.
>
> This would indeed helpful to review and check the naming convention
> directly on schematics, both for the
Hi Stephen,
Am Donnerstag, 3. Oktober 2019, 23:56:45 CEST schrieb Stephen Rothwell:
> In commit
>
> b62ce630fddb ("arm64: dts: rockchip: fix Rockpro64 RK808 interrupt line")
>
> Fixes tag
>
> Fixes: e4f3fb4 ("arm64: dts: rockchip: add initial dts support for
> Rockpro64")
I fixed the git
Am Dienstag, 17. September 2019, 10:26:47 CEST schrieb Heiko Stuebner:
> The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel,
> so fix that in the px30.dtsi
>
> Signed-off-by: Heiko Stuebner
applied patches 1-11 for 5.5
Patches 12+13 need the correspondin
Am Dienstag, 17. September 2019, 10:34:53 CEST schrieb Heiko Stuebner:
> The naming convention for the existing Theobroma boards is
> soc-q7module-baseboard, so rk3399-puma-haikou and the in-kernel
> devicetrees also follow that scheme.
>
> For some reason in the binding a wr
Hi Jagan,
Am Donnerstag, 19. September 2019, 07:28:20 CEST schrieb Jagan Teki:
> Though the ROC-PC is manufactured by firefly, it is co-designed
> by libretch like other Libretech computer boards from allwinner,
> amlogic does.
>
> So, it is always meaningful to keep maintain those vendors who
>
Hi Jagan,
Am Donnerstag, 19. September 2019, 07:28:17 CEST schrieb Jagan Teki:
> ROC-PC is not able to boot linux console if PWM2_d is
> unattached to any pinctrl logic.
>
> To be precise the linux boot hang with last logs as,
> ...
> .
> [0.003367] Console: colour dummy device 80x25
> [
Am Samstag, 21. September 2019, 15:14:57 CEST schrieb Hugh Cole-Baker:
> Fix the pinctrl and interrupt specifier for RK808 to use GPIO3_B2. On the
> Rockpro64 schematic [1] page 16, it shows GPIO3_B2 used for the interrupt
> line PMIC_INT_L from the RK808, and there's a note which translates as:
>
-pll.c| 28 ---
for the Rockchip part
Acked-by: Heiko Stuebner
Am Donnerstag, 19. September 2019, 23:26:41 CEST schrieb Douglas Anderson:
> This just adds in another field of what's stored in the e-fuse on
> rk3288. Though I can't personally promise that every rk3288 out there
> has the CPU ID stored in the eFuse at this location, there is some
> evidence
Newer Rockchip SoCs use a different IP for accessing special one-
time-programmable memory, so add a binding for these controllers.
Signed-off-by: Heiko Stuebner
---
.../bindings/nvmem/rockchip-otp.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
-off-by: Heiko Stuebner
---
drivers/nvmem/Kconfig| 11 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/rockchip-otp.c | 268 +++
3 files changed, 281 insertions(+)
create mode 100644 drivers/nvmem/rockchip-otp.c
diff --git a/drivers/nvmem/Kconfig b
Enable the phy node ion the px30 evb board.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts
b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 1185a314ba4a
Add the usb2phy node on the px30 and hook it up to the usb controllers
it supplies.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 43 ++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot
One of the separate General Register Files contains the registers for
controlling the usb2phy, so add the necessary binding compatible for it.
Signed-off-by: Heiko Stuebner
---
Documentation/devicetree/bindings/soc/rockchip/grf.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
The rk3399 gic-its was missing the #msi-cells property as found by
dt-schema checks, so add it.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip
complain now.
Fix this by using the names used in the wild by actual boards.
Signed-off-by: Heiko Stuebner
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml
b
Similar to all other Rockchip SoCs the px30 does not have a static
32kHz clock. Instead it again gets supplied from an external component
like the pmic.
So drop the static clock, so that we can hook up the right one.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 7
-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index a178d6e2c279..f2bbdfa0e4aa 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64
That gpio1-b0 can only be flash_cs apart from a regular gpio,
so there is no power-related pinmux for the emmc for this pin.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b
exposes uart5 through pin its pin headers, so it's way
saner to use these pins for serial output and keep the sdmmc working in
all cases.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot
Hook the reset line into an emmc-pwrseq for it to get initialized nicely.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts
b/arch/arm64/boot/dts/rockchip
The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel,
so fix that in the px30.dtsi
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b
them accordingly to the 2 crus to honor the loading direction.
Signed-off-by: Heiko Stuebner
---
.../bindings/clock/rockchip,px30-cru.txt | 5
arch/arm64/boot/dts/rockchip/px30.dtsi| 25 +++
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git
Add the board's pmic (rk809) and hook up the real supplies to their
consumers. This is especially important as cpufreq would otherwise hang
the system when scaling the frequency without adjusting the voltage.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 254
These are unused gpio-settings for specific function pins, that
are not used by anything and only clutter up the dtsi.
They can be re-added when a relevant user is added.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 40 --
1 file changed, 40
Enable i2c1 and adds the devices connected to it.
This includes a magnetometer, goodix-touchscreen and accelerometer.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts
The px30 soc from Rockchip shares the same register description as
the rk3328, so can re-use its definitions.
Signed-off-by: Heiko Stuebner
---
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 1 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c| 1 +
2 files
The clocks in the px30 critical clock section are from the regular cru not
the pmucru, so move them to the correct place.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-px30.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-px30.c
From: Finley Xiao
EMMC and SDIO already have these clock-ids (still unused) only sdmmc is
missing them, so fix that.
Signed-off-by: Finley Xiao
Signed-off-by: Heiko Stuebner
---
include/dt-bindings/clock/px30-cru.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings
Video-In and -Out interconnect clocks need to stay on all the
time for the peripheral to work and we do not model the actual
interconnect at this point. So mark them as critical for now.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-px30.c | 15 ++-
1 file changed, 10
From: Finley Xiao
Some IPs, such as NAND, EMMC, SDIO and SDMMC need clock of 50% duty
cycle, divfree50 can generate clock of 50% duty cycle even in odd
value divisor.
Signed-off-by: Finley Xiao
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-px30.c | 44
Make this clock a real critical clock, so that writes to the usbphy grf
always succeed.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-px30.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index
Do not open code the definition, instead use the nice DEFINE_RES_IRQ
macro for it.
Signed-off-by: Heiko Stuebner
---
drivers/mfd/rk808.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index c0e5e921766d..a69a6742ecdc 100644
The pwrkey integration seems to stem from the vendor kernel, as the
compatible is wrong and also the order of key-irqs is swapped.
So fix these issues to make the pwrkey on rk817 actually work.
Signed-off-by: Heiko Stuebner
---
drivers/mfd/rk808.c | 14 +++---
1 file changed, 3
to any devicetrees so far, so this
won't break anything.
Signed-off-by: Heiko Stuebner
---
drivers/mfd/rk808.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index 966841744ee6..c0e5e921766d 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers
to 0x8180.
Fixes: 9d6105e19f61 ("mfd: rk808: Fix up the chip id get failed")
Cc: sta...@vger.kernel.org
Cc: Elaine Zhang
Cc: Joseph Chen
Signed-off-by: Daniel Schultz
Acked-by: Lee Jones
[resend as it seems to have dropped on the floor]
Signed-off-by: Heiko Stuebner
---
include/linux
Hi Finley,
Am Dienstag, 3. September 2019, 13:59:44 CEST schrieb Finley Xiao:
> Finley Xiao (3):
> dt-bindings: Add bindings for rk3308 clock controller
> clk: rockchip: Add dt-binding header for rk3308
> clk: rockchip: Add clock controller for the RK3308
applied for (hopefully still) 5.4.
Hi Elon,
Am Montag, 5. August 2019, 03:57:55 CEST schrieb Elon Zhang:
> Add devicetree support for RK3399Pro TB-96AI board, one of
> the 96Boards family.
>
> The TB-96AI board is a 96Boards Compute SOM design, launched
> by Linaro, Rockchip and Beiqicloud.
>
> More information can be obtained
Hi Elon,
Am Donnerstag, 29. August 2019, 13:31:00 CEST schrieb Elon Zhang:
> On 8/27/2019 22:28, Heiko Stuebner wrote:
> > Am Dienstag, 27. August 2019, 09:14:39 CEST schrieb Elon Zhang:
> >> Not every board needs to enable crypto node, so the node should
> >> be set
erything into the core driver or exporting module
> symbols.
>
> Signed-off-by: Andrey Pronin
> Cc: Andrey Pronin
> Cc: Duncan Laurie
> Cc: Jason Gunthorpe
> Cc: Arnd Bergmann
> Cc: Greg Kroah-Hartman
> Cc: Guenter Roeck
> Cc: Alexander Steffen
> Cc: Heiko Stu
Am Mittwoch, 28. August 2019, 20:07:26 CEST schrieb Stephen Boyd:
> Quoting Heiko Stuebner (2019-08-28 10:36:29)
> > Am Mittwoch, 28. August 2019, 10:21:50 CEST schrieb Stephen Boyd:
> > > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
> > > fir
Am Mittwoch, 28. August 2019, 10:21:50 CEST schrieb Stephen Boyd:
> Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
> firmware. The firmware running on the currently supported H1 Secure
> Microcontroller requires a special driver to handle its specifics:
>
> - need to ensure a
Hi,
Am Dienstag, 27. August 2019, 09:14:39 CEST schrieb Elon Zhang:
> Not every board needs to enable crypto node, so the node should
> be set default disabled in rk3288.dtsi and enabled in specific
> board dts file.
Can you give a bit more rationale here? There would need to be a very
specific
-116169-1-git-send-email-apro...@chromium.org
Gave this a spin on a rk3399-gru-scarlet and it seems to have worked fine
and tpm2-tools was happy talking to it, so
Tested-by: Heiko Stuebner
>From looking through the patches everything also looks nice and peachy
but my tpm-insights are limi
Am Mittwoch, 21. August 2019, 19:54:38 CEST schrieb Jonas Karlman:
> This patch add a VPU device node for rk3328.
>
> Signed-off-by: Jonas Karlman
applied for 5.4
I'm still not sure where your original patch went though. I can see it
in patchwork but somehow not in my inbox ... in any case,
Am Mittwoch, 21. August 2019, 05:11:23 CEST schrieb Kever Yang:
> Since there is no one using this board, remove it.
>
> Signed-off-by: Kever Yang
applied both patches for 5.4
Thanks
Heiko
Am Donnerstag, 22. August 2019, 15:38:26 CEST schrieb Ulf Hansson:
> [...]
>
> > > > > > ---
> > > > > > Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 15
> > > ++-
> > > > >
> > > > > > 1 file changed, 10 insertions(+), 5 deletions(-)
> > > > > >
> > > > > > diff --git
Hi Kever,
Am Dienstag, 20. August 2019, 12:03:52 CEST schrieb Kever Yang:
> Since there is no one using this board, remove it.
so just to elaborate a bit, I guess this board was internal to Rockchip,
never went to the market and therefore is obsolete without any users,
right?
Also we should
Hi Kever,
Am Montag, 19. August 2019, 02:29:31 CEST schrieb Kever Yang:
> Hi Heiko,
>
> On 2019/8/16 下午8:24, Heiko Stuebner wrote:
> > Hi Kever, TL,
> >
> > [added TL Lim for clarification]
> >
> > Am Donnerstag, 15. August 2019, 10:12:52 CEST schri
Am Montag, 12. August 2019, 01:00:13 CEST schrieb Justin Swartz:
> The Mecer Xtreme Mini S6 features a Rockchip RK3229 SoC,
> 1GB DDR3 RAM, 8GB eMMC, MicroSD port, 10/100Mbps Ethernet,
> Realtek 8723BS WLAN module, 2 x USB 2.0 ports, HDMI output,
> and S/PDIF output.
>
> Signed-off-by: Justin
Am Montag, 5. August 2019, 14:40:37 CEST schrieb Andy Yan:
> P710 is a RK3399 based SBC, designed by Leez [0].
>
> Specification
> - Rockchip RK3399
> - 4/2GB LPDDR4
> - TF sd scard slot
> - eMMC
> - M.2 B-Key for 4G LTE
> - AP6256 for WiFi + BT
> - Gigabit ethernet
> - HDMI out
> - 40 pin header
Hi Kever, TL,
[added TL Lim for clarification]
Am Donnerstag, 15. August 2019, 10:12:52 CEST schrieb Kever Yang:
> According to rock64 schemetic V2 and V3, the VCC_HOST_5V output is
> controlled by USB_20_HOST_DRV, which is the same as VCC_HOST1_5V.
The v1 schematics I have do reference the
Am Donnerstag, 20. Juni 2019, 20:20:56 CEST schrieb Douglas Anderson:
> This reverts commit 1f45e8c6d0161f044d679f242fe7514e2625af4a.
>
> This 100 ms mystery delay is not on downstream kernels and no longer
> seems needed on upstream kernels either [1]. Presumably something in the
> meantime has
Hi Andy,
Am Sonntag, 4. August 2019, 10:38:26 CEST schrieb Andy Yan:
> Heiko Stuebner 于2019年8月4日周日 上午8:34写道:
> > Am Samstag, 3. August 2019, 13:46:12 CEST schrieb Andy Yan:
> > > Leez P710 is a RK3399 based SBC, designed by Leez team
> > > from lenovo [0]
Hi Andy,
Am Samstag, 3. August 2019, 13:46:12 CEST schrieb Andy Yan:
> Leez P710 is a RK3399 based SBC, designed by Leez team
> from lenovo [0].
>
> Specification
> - Rockchip RK3399
> - 4/2GB LPDDR4
> - TF sd scard slot
> - eMMC
> - M.2 B-Key for 4G LTE
> - AP6256 for WiFi + BT
> - Gigabit
Am Mittwoch, 31. Juli 2019, 17:15:27 CEST schrieb Matthias Kaehlcke:
> Fix/improve a few things for veyron fievel/tiger:
>
> - move 'vccsys' regulator from tiger to fievel, both boards
> have it (and tiger includes the fievel .dtsi)
> - move 'ext_gmac' node below regulators
> - fix GPIO ids of
Am Freitag, 2. August 2019, 00:03:54 CEST schrieb Matthias Kaehlcke:
> This is like commit 0ca87bd5baa6 ("ARM: dts: rockchip: Add pin names
> for rk3288-veyron-jerry") and other similar commits, but for the
> veyron fievel board (and tiger, which includes the fievel .dtsi).
>
> Signed-off-by:
Am Sonntag, 28. Juli 2019, 13:38:43 CEST schrieb Krzysztof Kozlowski:
> On Sat, 27 Jul 2019 at 17:33, Heiko Stuebner wrote:
> >
> > Hi Krzysztof,
> >
> > Am Samstag, 27. Juli 2019, 16:27:36 CEST schrieb Krzysztof Kozlowski:
> > > Fix DTC warning:
>
Am Samstag, 27. Juli 2019, 16:27:35 CEST schrieb Krzysztof Kozlowski:
> Use a space before and after assignment operator to have consistent
> style.
>
> Signed-off-by: Krzysztof Kozlowski
I've adapted the patch around recent chromebook display changes
(regarding veyron-chromebook.dtsi) and
Hi Krzysztof,
Am Samstag, 27. Juli 2019, 16:27:36 CEST schrieb Krzysztof Kozlowski:
> Fix DTC warning:
>
> arch/arm/boot/dts/rk3288-veyron.dtsi:21.9-24.4:
> Warning (unit_address_vs_reg): /memory: node has a reg or ranges
> property, but no unit name
please see the comment directly
Hi Justin,
Am Sonntag, 16. Juni 2019, 22:47:45 CEST schrieb Justin Swartz:
> The Mecer Xtreme Mini S6 features a Rockchip RK3229 SoC,
> 1GB DDR3 RAM, 8GB eMMC, MicroSD port, 10/100Mbps Ethernet,
> Realtek 8723BS WLAN module, 2 x USB 2.0 ports, HDMI output,
> and S/PDIF output.
>
> Signed-off-by:
Am Mittwoch, 3. Juli 2019, 06:54:58 CEST schrieb Doug Anderson:
> Hi,
>
> On Thu, Jun 20, 2019 at 1:31 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, Jun 20, 2019 at 11:21 AM Douglas Anderson
> > wrote:
> > >
> > > This reverts commit 1f45e8c6d0161f044d679f242fe7514e2625af4a.
> > >
> > >
Am Donnerstag, 25. Juli 2019, 18:26:42 CEST schrieb Matthias Kaehlcke:
> Also known as the AOpen Chromebase Mini.
>
> tiger and fievel are share the same board, tiger has a display and
> touchscreen, fievel not. Use the fievel .dts as base and add the
> extra bits.
>
> Signed-off-by: Matthias
Am Donnerstag, 25. Juli 2019, 18:26:41 CEST schrieb Matthias Kaehlcke:
> Also known as AOpen Chromebox Mini.
>
> Signed-off-by: Matthias Kaehlcke
> ---
> Changes in v3:
> - patch added to the series
> ---
> arch/arm/boot/dts/Makefile | 1 +
>
Am Donnerstag, 25. Juli 2019, 18:26:40 CEST schrieb Matthias Kaehlcke:
> Fievel is a Chromebox and Tiger a Chromebase with a 10" display and
> touchscreen. Tiger and Fievel are based on the same board.
>
> Signed-off-by: Matthias Kaehlcke
applied for 5.4
Am Donnerstag, 25. Juli 2019, 18:26:39 CEST schrieb Matthias Kaehlcke:
> veyron jaq, jerry, minnie and speedy have mostly redundant regulator
> and pinctrl configurations for the panel/backlight. Consolidate these
> pieces in the eDP .dtsi.
>
> Also change the default power supply for the panel
Am Donnerstag, 25. Juli 2019, 18:26:38 CEST schrieb Matthias Kaehlcke:
> The chromebook .dtsi file contains common settings for veyron
> Chromebooks with eDP displays. Some veyron devices with a display
> aren't Chromebooks (e.g. 'tiger' aka 'AOpen Chromebase Mini'), move
> display related bits
Am Mittwoch, 24. Juli 2019, 00:52:58 CEST schrieb Matthias Kaehlcke:
> The downstream Chrome OS 3.14 kernel for jerry limits WiFi TX power
> through calibration data in the device tree [1]. Add a DT node for
> the WiFi chip and use the downstream calibration data.
>
> Not all calibration data
Am Freitag, 28. Juni 2019, 00:32:38 CEST schrieb Nick Desaulniers:
> On Thu, Jun 27, 2019 at 3:22 PM 'Nathan Huckleberry' via Clang Built
> Linux wrote:
> >
> > Clang produces the following warning
> >
> > drivers/clk/rockchip/clk-rv1108.c:125:7: warning: unused variable
> > 'mux_pll_src_3plls_p'
Am Freitag, 28. Juni 2019, 00:22:20 CEST schrieb Nathan Huckleberry:
> Clang produces the following warning
>
> drivers/clk/rockchip/clk-rv1108.c:125:7: warning: unused variable
> 'mux_pll_src_3plls_p' [-Wunused-const-variable]
> PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
>
>
Hi Stephen,
Am Montag, 22. Juli 2019, 23:35:18 CEST schrieb Stephen Boyd:
> Quoting Nathan Huckleberry (2019-06-27 15:22:20)
> > Clang produces the following warning
> >
> > drivers/clk/rockchip/clk-rv1108.c:125:7: warning: unused variable
> > 'mux_pll_src_3plls_p' [-Wunused-const-variable]
> >
Hi,
Am Samstag, 13. Juli 2019, 13:38:45 CEST schrieb Alex Dewar:
> I initially thought my machine was failing to boot entirely, but it
> turns out it was just failing to start the display manager. I managed to
> escape to a tty by hammering the keyboard a bit.
>
> I suspect the culprit is the
Am Donnerstag, 13. Juni 2019, 18:27:45 CEST schrieb Enric Balletbo i Serra:
> As per binding documentation [1], the DWC3 core should have the "ref",
> "bus_early" and "suspend" clocks. As explained in the binding, those
> clocks are required for new platforms but not for existing platforms
>
Am Samstag, 15. Juni 2019, 17:30:30 CEST schrieb Heiko Stuebner:
> Needed to export that added clock.
>
> Signed-off-by: Heiko Stuebner
applied all 3 patches to relevant branches for 5.3
Cheers
Heiko
Am Freitag, 14. Juni 2019, 18:54:50 CEST schrieb Heiko Stuebner:
> The hdmiphy needs its clock reparented to the actual hdmiphy-pll
> that gets generated in the hdmiphy itself.
>
> This incorporates adapted versions of Justin's original patches
> and also the needed clock ad
Hi Lee,
Am Mittwoch, 26. Juni 2019, 13:52:51 CEST schrieb Lee Jones:
> On Fri, 21 Jun 2019, Tony Xie wrote:
>
> > Most of functions and registers of the rk817 and rk808 are the same,
> > so they can share allmost all codes.
> >
> > Their specifications are as follows:
> > 1) The RK809 and
Am Dienstag, 4. Juni 2019, 18:57:57 CEST schrieb Daniel Lezcano:
> Currently the common thermal zones definitions for the rk3399 assumes
> multiple thermal zones are supported by the governors. This is not the
> case and each thermal zone has its own governor instance acting
> individually without
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu
applied for 5.3
Thanks
Heiko
Am Dienstag, 18. Juni 2019, 20:45:31 CEST schrieb Matthias Kaehlcke:
> This reverts commit 288ceb85b505c19abe1895df068dda5ed20cf482.
>
> The commit assumes that the minnie panel is a AUO B101EAN01.1 (LVDS
> interface), however it is a AUO B101EAN01.8 (eDP interface). The eDP
> panel doesn't need
Am Mittwoch, 19. Juni 2019, 20:34:25 CEST schrieb Douglas Anderson:
> This is the other half of the hacky solution from commit f497ab6b4bb8
> ("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on
> veyron"). Specifically the LPM driver that the Broadcom Bluetooth
> expects to have
. The RK817 has one switch but The Rk809 has two.
The output voltages are configurable and are meant to supply power
to the main processor and other components.
Signed-off-by: Tony Xie
Acked-by: Lee Jones
Acked-by: Mark Brown
[rebased on top of 5.2-rc1]
Signed-off-by: Heiko Stuebner
you could try to find the offending
commit first, so that ideally the network maintainers can fix that
up.
Thanks
Heiko
> On 2019/06/22 17:33, Heiko Stuebner wrote:
> > Hi,
> >
> > Am Freitag, 21. Juni 2019, 20:00:17 CEST schrieb Katsuhiro Suzuki:
> >> This patch
Hi,
Am Freitag, 21. Juni 2019, 20:00:17 CEST schrieb Katsuhiro Suzuki:
> This patch adds missing mdio and ethernet PHY nodes for rk3328 ASUS
> tinker board.
>
> Signed-off-by: Katsuhiro Suzuki
just for my understanding, which problem does this solve?
Normally the gmac can establish connections
The watchdog pclk is controlled from the secure GRF but we still
want to mention it explicitly to not use arbitary parent clocks
in the devicetree wdt node, so add a SGRF_GATE for it.
Suggested-by: Leonidas P. Papadakos
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-rk3328.c | 3
Needed to export that added clock.
Signed-off-by: Heiko Stuebner
---
include/dt-bindings/clock/rk3328-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index afb811340382..555b4ff660ae 100644
--- a/include
From: Leonidas P. Papadakos
Add the missing clock property for the watchdog on rk3328.
Signed-off-by: Leonidas P. Papadakos
[set wdt node to always enabled, as it is not board-specific]
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
1 file changed, 1
Stephen,
Am Freitag, 14. Juni 2019, 22:36:09 CEST schrieb Stephen Boyd:
> Quoting Heiko Stuebner (2019-06-14 12:33:12)
> > Am Freitag, 14. Juni 2019, 20:32:35 CEST schrieb Justin Swartz:
> > > On 2019-06-14 19:45, Stephen Boyd wrote:
> > > >> diff --git a/arch/arm
Am Freitag, 14. Juni 2019, 20:32:35 CEST schrieb Justin Swartz:
> On 2019-06-14 19:45, Stephen Boyd wrote:
> >> diff --git a/arch/arm/boot/dts/rk322x.dtsi
> >> b/arch/arm/boot/dts/rk322x.dtsi
> >> index da102fff96a2..148f9b5157ea 100644
> >> --- a/arch/arm/boot/dts/rk322x.dtsi
> >> +++
Am Donnerstag, 6. Juni 2019, 11:09:33 CEST schrieb Heiko Stuebner:
> Some clk gates on Rockchip SoCs are part of the SGRF (secure general
> register files) and thus only controllable from secure mode, with the
> most prominent example being the watchdog.
>
> In most cases we still
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