> -Original Message-
> From: Frieder Schrempf [mailto:frieder.schre...@kontron.de]
> Sent: Thursday, February 25, 2021 4:23 PM
> To: Abel Vesa ; Dong Aisheng
> Cc: Aisheng Dong ; Rob Herring ;
> Peng Fan ; Jacky Bai ; Anson Huang
> ; devicetree ;
> Stephen B
> -Original Message-
> From: Richard Zhu
> Sent: Thursday, February 18, 2021 2:19 PM
> To: Jacky Bai ; shawn...@kernel.org
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: RE: [PATCH] clk: imx8mp: Remove the n
> -Original Message-
> From: Richard Zhu [mailto:hongxing@nxp.com]
> Sent: Thursday, February 18, 2021 1:54 PM
> To: shawn...@kernel.org; Jacky Bai
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Richard Zhu
> Subject
> -Original Message-
> From: Abel Vesa [mailto:abel.v...@nxp.com]
> Sent: Tuesday, November 3, 2020 7:18 PM
> To: Mike Turquette ; Stephen Boyd
> ; Adam Ford ; Marek Vasut
> ; Lucas Stach ; Rob
> Herring ; Shawn Guo ; Sascha
> Hauer ; Fabio Estevam ;
> Anson Hua
. I'm
> > > still thinking about how to solve this properly.
> > >
> >
> > I remember we had something similar in our internal tree with the
> > bus_blk_clk on 8MP, which was added by the media BLK_CTL. What I did
> > was to just drop the registration of that clock entirely. My rationale
> > was that if the clock is part of the BLK_CTL but also needed by the
> > BLK_CTL to work, I can leave it alone (that is, enabled by default)
> > since when the PD will be powered off the clock will gated too. I
> > guess another option would be to mark it as critical, that way, it
> > will never be disabled (will be left alone by the clk_disable_unused
> > too) but at the same time will be visible in the clock hierarchy.
> >
>
> Do ignore evrything I said about the bus_blk_ctl, that did work on our tree
> since the whole PD power on/off "magic" is done in TF-A.
>
> So the problem, as I understand it now, is the fact that the blk_ctl driver
> won't
> probe because it needs its PD, but the PD is not registered because the
> ADB400 can't power up since it needs the bus_blk_ctl clock enabled, clock
> which is registered by the blk_ctl.
1. For some MIX's BLK_CTL GPRs, it can only be accessed when the MIX PD is on
2. for some MIX's ADB handshake, need to config some BLK_CTL clock_en bit to
enable the MIX internal bus clock.
That's why I have concern on implementing such MIX GPR as clock & reset driver,
and implementing GPC PD in linux kernel.
It will introduce some chicken-egg issue that not easy to handle in linux
kernel.
BR
Jacky Bai
>
> > > Regards,
> > > Lucas
> > >
ernel.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Cc: Jacky Bai ; Krzysztof Kozlowski
> Subject: [PATCH 3/3] arm64: dts: imx8mp: adjust GIC CPU mask to match
> number of CPUs
>
> i.MX 8M Plus has four Cortex-A CPUs, not six. Using higher value is
OK for me.
BR
Jacky Bai
> -Original Message-
> From: anson.hu...@nxp.com [mailto:anson.hu...@nxp.com]
> Sent: Tuesday, June 25, 2019 3:06 PM
> To: mturque...@baylibre.com; sb...@kernel.org; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail
Jacky Bai would like to recall the message, "[PATCH 2/2] clk: imx8mm: GPT1
clock mux option #5 should be sys_pll1_80m".
From: Bai Ping
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
From: Bai Ping
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
Reviewed-by: Rob Herring
---
change v1->v2
- remove the blank line at EOF
change v2->v3
- update the binding example based on the driver change
change v3->v4
- no change
change v4->v5
- no
> -Original Message-
> From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org]
> Sent: Tuesday, May 21, 2019 8:20 PM
> To: Jacky Bai ; t...@linutronix.de; robh...@kernel.org;
> shawn...@kernel.org; mark.rutl...@arm.com; Aisheng Dong
>
> Cc: linux-kernel@vge
> -Original Message-
> From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org]
> Sent: Tuesday, May 21, 2019 6:08 PM
> To: Jacky Bai ; t...@linutronix.de; robh...@kernel.org;
> shawn...@kernel.org; mark.rutl...@arm.com; Aisheng Dong
>
> Cc: linux-kernel@vge
From: Bai Ping
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
From: Bai Ping
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
Reviewed-by: Rob Herring
---
change v1->v2
- remove the blank line at EOF
change v2->v3
- update the binding example based on the driver change
change v3->v4
- no change
---
Sorry for delayed response to you, my mail client did something wrong. :(
> On Wed, 3 Apr 2019, Jacky Bai wrote:
>
> > From: Bai Ping
> >
> > The system counter (sys_ctr) is a programmable system counter which
> > provides a shared time base to the
From: Bai Ping
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
From: Bai Ping
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
---
change v1->v2
- remove the blank line at EOF
change v2->v3
- update the binding example based on the driver change
---
.../devicetree/bindings/timer/nxp,sysctr-timer.txt | 25
> Subject: Re: [PATCH v2 2/2] driver: clocksource: Add nxp system counter timer
> driver support
>
> On 12/12/2018 06:28, Jacky Bai wrote:
> > The system counter (sys_ctr) is a programmable system counter which
> > provides a shared time base to the Corte
Ping...
BR
Jacky Bai
> -Original Message-
> From: Jacky Bai
> Sent: 2018年12月12日 13:28
> To: daniel.lezc...@linaro.org; t...@linutronix.de; robh...@kernel.org;
> shawn...@kernel.org; mark.rutl...@arm.com; Aisheng Dong
>
> Cc: linux-kernel@vger.kernel.org; devicet..
> Subject: Re: [PATCH v2 2/2] driver: clocksource: Add nxp system counter timer
> driver support
>
> Hi,
>
> On 12/11/18 9:28 PM, Jacky Bai wrote:
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index c57b156..7e5f2de 100644
> &g
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
---
change v1->v2
- remove the blank line at EOF
---
.../devicetree/bindings/timer/nxp,sysctr_timer.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
supports:
- 56-bit
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
supports:
- 56-bit
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
---
.../devicetree/bindings/timer/nxp,sysctr_timer.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr_timer.txt
diff --git
The system counter (sys_ctr) is a programmable system counter
which provides a shared time base to the Cortex A15, A7, A53 etc cores.
It is intended for use in applications where the counter is always
powered on and supports multiple, unrelated clocks. The sys_ctr hardware
supports:
- 56-bit
Add the binding doc for nxp system counter timer module.
Signed-off-by: Bai Ping
---
.../devicetree/bindings/timer/nxp,sysctr_timer.txt | 28 ++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr_timer.txt
diff --git
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> On 09.05.2018 03:26, Jacky Bai wrote:
> >> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate
> >> change
> >>
> >> Quoting Stefan Agner (2018-05-08 06:20:03
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> On 09.05.2018 03:26, Jacky Bai wrote:
> >> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate
> >> change
> >>
> >> Quoting Stefan Agner (2018-05-08 06:20:03
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> Quoting Stefan Agner (2018-05-08 06:20:03)
> > On 08.05.2018 09:32, Jacky Bai wrote:
> > >
> > > I have tried two 6ULL board, I don't meet such issue. System can
> > > boo
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> Quoting Stefan Agner (2018-05-08 06:20:03)
> > On 08.05.2018 09:32, Jacky Bai wrote:
> > >
> > > I have tried two 6ULL board, I don't meet such issue. System can
> > > boo
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> Hi Jacky,
>
> On 02.05.2018 09:38, Shawn Guo wrote:
> > Hi Jacky,
> >
> > Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?
>
> Any comment to this?
>
> It is 4.17.0-rc4 is out and i.MX 6ULL is
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>
> Hi Jacky,
>
> On 02.05.2018 09:38, Shawn Guo wrote:
> > Hi Jacky,
> >
> > Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?
>
> Any comment to this?
>
> It is 4.17.0-rc4 is out and i.MX 6ULL is
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