dead.org/users/jcooper/linux.git irqchip/gic
> (per Jason Cooper request)
> * Misc fix/clean up per Mark Rutland comments
> * Minor Clean up in the driver/irqchip/irq-gic-v2m.c: alloc_msi_irqs()
> * Patch 4 is new to the series:
> * Add ARM64-
Suthikulpanit
>
> This patch extend GICv2m MSI to support multiple MSI in ARM64.
>
> This requires the common arch_setup_msi_irqs() to be overwriten
> with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
> nvec > 1.
>
> Cc: Mark Rutland
> Cc: Marc
ntains an "msi_chip" structure. To discover the msi_chip,
> PCI host driver can do the following:
>
> struct device_node *gic_node = of_irq_find_parent(pdev->dev.of_node);
> pcie_bus->msi_chip = of_pci_find_msi_chip_by_node(gic_node);
>
> Cc: Mark R
rnel/irq.c | 25 +
> 2 files changed, 23 insertions(+), 4 deletions(-)
Please place in Russell's patch tracker,
Acked-by: Jason Cooper
Once it lands in a release, we'll apply the rest. Please send me a
gentle reminder ;-)
thx,
Jason.
--
To unsubscribe from thi
changed, 23 insertions(+), 4 deletions(-)
Please place in Russell's patch tracker,
Acked-by: Jason Cooper ja...@lakedaemon.net
Once it lands in a release, we'll apply the rest. Please send me a
gentle reminder ;-)
thx,
Jason.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel
host driver can do the following:
struct device_node *gic_node = of_irq_find_parent(pdev-dev.of_node);
pcie_bus-msi_chip = of_pci_find_msi_chip_by_node(gic_node);
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Jason Cooper ja...@lakedaemon.net
Cc
marc.zyng...@arm.com
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
arch/arm64/include/asm/msi.h | 15
arch/arm64/kernel/Makefile| 1
/linux.git irqchip/gic
(per Jason Cooper request)
* Misc fix/clean up per Mark Rutland comments
* Minor Clean up in the driver/irqchip/irq-gic-v2m.c: alloc_msi_irqs()
* Patch 4 is new to the series:
* Add ARM64-specific version arch_setup_msi_irqs() to allow support
On Fri, Jul 11, 2014 at 06:56:26PM +0530, Amit Shah wrote:
> On (Wed) 09 Jul 2014 [12:07:25], Jason Cooper wrote:
> > Amit, Kees,
>
> (snip)
>
> > I'm cooling to the idea of the init function for virtio-rng, and it
> > might be best just to admit that there's n
On Fri, Jul 11, 2014 at 06:56:26PM +0530, Amit Shah wrote:
On (Wed) 09 Jul 2014 [12:07:25], Jason Cooper wrote:
Amit, Kees,
(snip)
I'm cooling to the idea of the init function for virtio-rng, and it
might be best just to admit that there's no way to seed the entropy pool
from
be read
> from them.
>
> This commit makes the call to rng_get_data() depend on no init fn
> pointer being registered by the device. If an init function is
> registered, this call is made after device init.
>
> CC: Kees Cook
> CC: Jason Cooper
> CC: Herbert Xu
> CC: # For v3
makes the call to rng_get_data() depend on no init fn
pointer being registered by the device. If an init function is
registered, this call is made after device init.
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
CC: Herbert Xu herb...@gondor.apana.org.au
CC: sta
t out of our probe routine when this call is made. This
> causes the host to not acknowledge any requests we put in the virtqueue,
> and the insmod or kernel boot process just waits for data to arrive from
> the host, which never happens.
>
> CC: Kees Cook
> CC: Jason
Amit, Kees,
On Wed, Jul 09, 2014 at 06:55:24PM +0530, Amit Shah wrote:
> On (Wed) 09 Jul 2014 [09:17:37], Jason Cooper wrote:
> > On Wed, Jul 09, 2014 at 06:38:22PM +0530, Amit Shah wrote:
> > > On (Wed) 09 Jul 2014 [07:53:17], Jason Cooper wrote:
> > > > On Sat, Ju
On Wed, Jul 09, 2014 at 06:38:22PM +0530, Amit Shah wrote:
> On (Wed) 09 Jul 2014 [07:53:17], Jason Cooper wrote:
> > On Sat, Jul 05, 2014 at 11:04:52AM +0530, Amit Shah wrote:
> > > Commit d9e7972619334 "hwrng: add randomness to system from rng sources"
> > >
On Mon, Jul 07, 2014 at 12:04:09PM +0530, Amit Shah wrote:
> On (Sun) 06 Jul 2014 [23:09:49], Kees Cook wrote:
> > On Sun, Jul 6, 2014 at 10:51 PM, Amit Shah wrote:
> > > On (Sun) 06 Jul 2014 [21:38:36], Kees Cook wrote:
> > >> On Fri, Jul 4, 2014 at 10:34 PM, Amit Shah wrote:
> > >> > The hwrng
be read
> from them.
>
> This commit makes the call to rng_get_data() depend on no init fn
> pointer being registered by the device. If an init function is
> registered, this call is made after device init.
>
> CC: Kees Cook
> CC: Jason Cooper
> CC: Herbert Xu
> CC: # For v3
makes the call to rng_get_data() depend on no init fn
pointer being registered by the device. If an init function is
registered, this call is made after device init.
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
CC: Herbert Xu herb...@gondor.apana.org.au
CC: sta
On Mon, Jul 07, 2014 at 12:04:09PM +0530, Amit Shah wrote:
On (Sun) 06 Jul 2014 [23:09:49], Kees Cook wrote:
On Sun, Jul 6, 2014 at 10:51 PM, Amit Shah amit.s...@redhat.com wrote:
On (Sun) 06 Jul 2014 [21:38:36], Kees Cook wrote:
On Fri, Jul 4, 2014 at 10:34 PM, Amit Shah
On Wed, Jul 09, 2014 at 06:38:22PM +0530, Amit Shah wrote:
On (Wed) 09 Jul 2014 [07:53:17], Jason Cooper wrote:
On Sat, Jul 05, 2014 at 11:04:52AM +0530, Amit Shah wrote:
Commit d9e7972619334 hwrng: add randomness to system from rng sources
added a call to rng_get_data() from
Amit, Kees,
On Wed, Jul 09, 2014 at 06:55:24PM +0530, Amit Shah wrote:
On (Wed) 09 Jul 2014 [09:17:37], Jason Cooper wrote:
On Wed, Jul 09, 2014 at 06:38:22PM +0530, Amit Shah wrote:
On (Wed) 09 Jul 2014 [07:53:17], Jason Cooper wrote:
On Sat, Jul 05, 2014 at 11:04:52AM +0530, Amit Shah
probe routine when this call is made. This
causes the host to not acknowledge any requests we put in the virtqueue,
and the insmod or kernel boot process just waits for data to arrive from
the host, which never happens.
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
On Thu, Jul 03, 2014 at 01:58:52PM +0200, Matthias Brugger wrote:
> Patch 0a68214b "ARM: DT: Add binding for GIC virtualization extentions
> (VGIC)" added
> the "arm,cortex-a7-gic" compatible string, but the corresponding
> IRQCHIP_DECLARE
> was never added to the gic driver.
>
> To let real
Feng,
On Wed, Jul 02, 2014 at 02:18:58PM -0700, Feng Kan wrote:
> This is to cleanup some hex numbers used in the code and replace
> then with defines to make the code cleaner.
>
> Signed-off-by: Feng Kan
> Reviewed-by: Anup Patel
> ---
> drivers/irqchip/irq-gic.c | 62
>
Feng,
On Wed, Jul 02, 2014 at 02:18:57PM -0700, Feng Kan wrote:
> This patch series cleans up hex number in the gic driver and then adds
> the code to preserve GIC v2 bypass disable bits in the GIC driver.
>
> V3 Change: remove incorrect Signoff by
>
> V2 Change:
> seem my send email was
Suravee,
On Wed, Jul 02, 2014 at 10:21:05AM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> This patch set introduces support for MSI(-X) in GICv2m specification,
> which is implemented in some variation of GIC400 (e.g. gic-400+).
>
> This depends on and has been
Jon,
On Tue, Jul 08, 2014 at 09:02:14AM -0500, Jon Loeliger wrote:
> My IP block provides software-assignable interrupts. That
> is, I have a large pool of interrupt sources, and a large pool
> of interrupt bits in the controller, but they are not physically
> tied together. Instead they are
Nick,
Please don't top-post. I've fixed it up ...
On Mon, Jul 07, 2014 at 01:35:24PM -0400, Nick Krause wrote:
> On Mon, Jul 7, 2014 at 9:46 AM, Theodore Ts'o wrote:
> > On Mon, Jul 07, 2014 at 01:22:13AM -0400, Nick Krause wrote:
> >> Here are my logs of the builds attached with warnings if
)
irqchip core changes for v3.17 (incremental #2)
- or1k-pic
- Migrate driver from arch/openrisc
- crossbar
- cleanup series
Jason Cooper (1):
Merge branch 'irqchip/crossbar' into irqchip/core
Nishanth Menon (14
Ezequiel,
On Mon, Jul 07, 2014 at 08:37:58PM -0300, Ezequiel Garcia wrote:
> On 07 Jul 11:30 AM, Greg Kroah-Hartman wrote:
> > On Mon, Jul 07, 2014 at 07:58:18AM -0300, Ezequiel Garcia wrote:
> [..]
> > >
> > > I guess I snipped the thread and lost most of the information about the
> > > panic.
Ezequiel,
On Mon, Jul 07, 2014 at 08:37:58PM -0300, Ezequiel Garcia wrote:
On 07 Jul 11:30 AM, Greg Kroah-Hartman wrote:
On Mon, Jul 07, 2014 at 07:58:18AM -0300, Ezequiel Garcia wrote:
[..]
I guess I snipped the thread and lost most of the information about the
panic.
Here's
)
irqchip core changes for v3.17 (incremental #2)
- or1k-pic
- Migrate driver from arch/openrisc
- crossbar
- cleanup series
Jason Cooper (1):
Merge branch 'irqchip/crossbar' into irqchip/core
Nishanth Menon (14
Nick,
Please don't top-post. I've fixed it up ...
On Mon, Jul 07, 2014 at 01:35:24PM -0400, Nick Krause wrote:
On Mon, Jul 7, 2014 at 9:46 AM, Theodore Ts'o ty...@mit.edu wrote:
On Mon, Jul 07, 2014 at 01:22:13AM -0400, Nick Krause wrote:
Here are my logs of the builds attached with
Jon,
On Tue, Jul 08, 2014 at 09:02:14AM -0500, Jon Loeliger wrote:
My IP block provides software-assignable interrupts. That
is, I have a large pool of interrupt sources, and a large pool
of interrupt bits in the controller, but they are not physically
tied together. Instead they are
Suravee,
On Wed, Jul 02, 2014 at 10:21:05AM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400 (e.g. gic-400+).
This
Feng,
On Wed, Jul 02, 2014 at 02:18:57PM -0700, Feng Kan wrote:
This patch series cleans up hex number in the gic driver and then adds
the code to preserve GIC v2 bypass disable bits in the GIC driver.
V3 Change: remove incorrect Signoff by
V2 Change:
seem my send email was not
Feng,
On Wed, Jul 02, 2014 at 02:18:58PM -0700, Feng Kan wrote:
This is to cleanup some hex numbers used in the code and replace
then with defines to make the code cleaner.
Signed-off-by: Feng Kan f...@apm.com
Reviewed-by: Anup Patel apa...@apm.com
---
drivers/irqchip/irq-gic.c |
On Thu, Jul 03, 2014 at 01:58:52PM +0200, Matthias Brugger wrote:
Patch 0a68214b ARM: DT: Add binding for GIC virtualization extentions
(VGIC) added
the arm,cortex-a7-gic compatible string, but the corresponding
IRQCHIP_DECLARE
was never added to the gic driver.
To let real Cortex-A7
On Wed, Jul 02, 2014 at 06:56:35PM +0530, Amit Shah wrote:
> Hi Jason,
>
> On (Wed) 02 Jul 2014 [13:00:19], Jason Cooper wrote:
> > Commit d9e7972619334 "hwrng: add randomness to system from rng sources"
> > added a call to rng_get_data() from the hwrng_register()
g at probe, new
patch, copied Amit's commit message. ]
CC: Kees Cook
CC: Jason Cooper
CC: Herbert Xu
CC: # v3.15+
Signed-off-by: Amit Shah
Signed-off-by: Jason Cooper
---
drivers/char/hw_random/core.c | 8 +---
include/linux/hw_random.h | 4
2 files changed, 9 insertions(+), 3
, the request for random data isn't made, and the stall when
loading the module doesn't happen.
[jac: reworked to use a flag instead of an init function. Reused most
of Amit's commit message. ]
CC: Kees Cook
CC: Jason Cooper
CC: Herbert Xu
CC: # v3.15+
Signed-off-by: Amit Shah
Signed-off-by: Jason
On Wed, Jul 02, 2014 at 05:41:20PM +0530, Amit Shah wrote:
> On (Wed) 02 Jul 2014 [07:58:23], Jason Cooper wrote:
> > On Wed, Jul 02, 2014 at 03:58:15PM +0530, Amit Shah wrote:
> > > Commit d9e7972619334 "hwrng: add randomness to system from rng sources"
> > >
boot process just
> sits there doing nothing.
>
> This commit makes the call to rng_get_data() depend on no init fn
> pointer being registered by the device. If an init function is
> registered, this call isn't made.
>
> CC: Kees Cook
> CC: Jason Cooper
> CC:
.
This commit makes the call to rng_get_data() depend on no init fn
pointer being registered by the device. If an init function is
registered, this call isn't made.
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
CC: Herbert Xu herb...@gondor.apana.org.au
CC: sta
On Wed, Jul 02, 2014 at 05:41:20PM +0530, Amit Shah wrote:
On (Wed) 02 Jul 2014 [07:58:23], Jason Cooper wrote:
On Wed, Jul 02, 2014 at 03:58:15PM +0530, Amit Shah wrote:
Commit d9e7972619334 hwrng: add randomness to system from rng sources
added a call to rng_get_data() from
, the request for random data isn't made, and the stall when
loading the module doesn't happen.
[jac: reworked to use a flag instead of an init function. Reused most
of Amit's commit message. ]
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
CC: Herbert Xu herb
patch, copied Amit's commit message. ]
CC: Kees Cook keesc...@chromium.org
CC: Jason Cooper ja...@lakedaemon.net
CC: Herbert Xu herb...@gondor.apana.org.au
CC: sta...@vger.kernel.org # v3.15+
Signed-off-by: Amit Shah amit.s...@redhat.com
Signed-off-by: Jason Cooper ja...@lakedaemon.net
---
drivers
On Wed, Jul 02, 2014 at 06:56:35PM +0530, Amit Shah wrote:
Hi Jason,
On (Wed) 02 Jul 2014 [13:00:19], Jason Cooper wrote:
Commit d9e7972619334 hwrng: add randomness to system from rng sources
added a call to rng_get_data() from the hwrng_register() function.
However, some rng devices
Russell,
On Tue, Jul 01, 2014 at 02:10:26PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jul 01, 2014 at 03:04:31PM +0200, Sebastian Hesselbarth wrote:
> > + pdev = platform_device_register_full(_drm_dev_info);
> > + /* assign last found lcd node to drm device for clk lookup */
> > +
On Sat, Jun 21, 2014 at 04:02:02PM -0400, Jason Cooper wrote:
> Stefan,
>
> On Mon, May 26, 2014 at 11:31:42PM +0300, Stefan Kristiansson wrote:
> > In addition to consolidating the or1k-pic with other interrupt
> > controllers, this makes OpenRISC less tied to its on-cpu
>
On Tue, Jul 01, 2014 at 03:06:36PM +0530, Sricharan R wrote:
> Hi Tony,
>
> On Tuesday 01 July 2014 01:29 PM, Tony Lindgren wrote:
> > * Jason Cooper [140630 12:30]:
> >>
> >> Whole series applied to irqchip/crossbar, I'll give it a day or two in
> >> -
On Tue, Jul 01, 2014 at 03:06:36PM +0530, Sricharan R wrote:
Hi Tony,
On Tuesday 01 July 2014 01:29 PM, Tony Lindgren wrote:
* Jason Cooper ja...@lakedaemon.net [140630 12:30]:
Whole series applied to irqchip/crossbar, I'll give it a day or two in
-next, then I'll merge it into irqchip
On Sat, Jun 21, 2014 at 04:02:02PM -0400, Jason Cooper wrote:
Stefan,
On Mon, May 26, 2014 at 11:31:42PM +0300, Stefan Kristiansson wrote:
In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller
Russell,
On Tue, Jul 01, 2014 at 02:10:26PM +0100, Russell King - ARM Linux wrote:
On Tue, Jul 01, 2014 at 03:04:31PM +0200, Sebastian Hesselbarth wrote:
+ pdev = platform_device_register_full(armada_drm_dev_info);
+ /* assign last found lcd node to drm device for clk lookup */
+
On Fri, Jun 27, 2014 at 08:00:35AM -0400, Jason Cooper wrote:
> On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
> > From: Nishanth Menon
> >
> > Currently we attempt to map any crossbar value to an IRQ, however,
> > this is not correct from hardware
On Thu, Jun 26, 2014 at 12:40:18PM +0530, Sricharan R wrote:
> This series does some cleanups, fixes for handling two interrupts
> getting mapped twice to same crossbar and provides support for
> hardwired IRQ and crossbar definitions.
>
> On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6,
On Tue, Jun 24, 2014 at 07:19:26PM -0500, Suravee Suthikulanit wrote:
> On 6/24/2014 7:26 AM, Jason Cooper wrote:
> >On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com
> >wrote:
> >>This patch set introduces support for MSI(-X) in GICv2m
On Tue, Jun 24, 2014 at 07:19:26PM -0500, Suravee Suthikulanit wrote:
On 6/24/2014 7:26 AM, Jason Cooper wrote:
On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com
wrote:
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some
On Thu, Jun 26, 2014 at 12:40:18PM +0530, Sricharan R wrote:
This series does some cleanups, fixes for handling two interrupts
getting mapped twice to same crossbar and provides support for
hardwired IRQ and crossbar definitions.
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10,
On Fri, Jun 27, 2014 at 08:00:35AM -0400, Jason Cooper wrote:
On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
From: Nishanth Menon n...@ti.com
Currently we attempt to map any crossbar value to an IRQ, however,
this is not correct from hardware perspective. There is a max
):
irqchip: nvic: Use the generic noop function
Jason Cooper (1):
Merge branch 'irqchip/urgent' into irqchip/core
Thomas Gleixner (13):
irqchip: spear_shirq: Kill pointless static
irqchip: spear_shirq: Move private structs to source
irqchip: spear_shirq: No point
Gregory,
Since you'll be resending this:
On Fri, Jun 27, 2014 at 12:55:47AM +0200, Gregory CLEMENT wrote:
> On 27/06/2014 00:43, Gregory CLEMENT wrote:
> > The first bit of the SCU control register is actually the enable
> > it. So let's name it instead of using literal constant.
nit:
On Thu, Jun 26, 2014 at 12:42:09AM -0700, Tony Lindgren wrote:
> * Sricharan R [140626 00:14]:
> > This series does some cleanups, fixes for handling two interrupts
> > getting mapped twice to same crossbar and provides support for
> > hardwired IRQ and crossbar definitions.
> >
> > On certain
On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
> From: Nishanth Menon
>
> Currently we attempt to map any crossbar value to an IRQ, however,
> this is not correct from hardware perspective. There is a max crossbar
> event number upto which hardware supports. So describe the same in
On Thu, Jun 26, 2014 at 12:40:33PM +0530, Sricharan R wrote:
> From: Nishanth Menon
>
> The current crossbar description does not include the description
> required for the consumer of the crossbar, a.k.a devices whoes events
> pass through the crossbar into the GIC interrupt controller.
>
>
On Thu, Jun 26, 2014 at 09:48:25AM -0700, Feng Kan wrote:
> On Wed, Jun 25, 2014 at 6:05 PM, Thomas Gleixner wrote:
> > On Wed, 25 Jun 2014, Feng Kan wrote:
> >
> >> This change is made to preserve the GIC v2 bypass bits in the
> >> GIC_CPU_CTRL register (also known as the GICC_CTLR register in
On Thu, Jun 26, 2014 at 09:48:25AM -0700, Feng Kan wrote:
On Wed, Jun 25, 2014 at 6:05 PM, Thomas Gleixner t...@linutronix.de wrote:
On Wed, 25 Jun 2014, Feng Kan wrote:
This change is made to preserve the GIC v2 bypass bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR
On Thu, Jun 26, 2014 at 12:40:33PM +0530, Sricharan R wrote:
From: Nishanth Menon n...@ti.com
The current crossbar description does not include the description
required for the consumer of the crossbar, a.k.a devices whoes events
pass through the crossbar into the GIC interrupt controller.
On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
From: Nishanth Menon n...@ti.com
Currently we attempt to map any crossbar value to an IRQ, however,
this is not correct from hardware perspective. There is a max crossbar
event number upto which hardware supports. So describe the
On Thu, Jun 26, 2014 at 12:42:09AM -0700, Tony Lindgren wrote:
* Sricharan R r.sricha...@ti.com [140626 00:14]:
This series does some cleanups, fixes for handling two interrupts
getting mapped twice to same crossbar and provides support for
hardwired IRQ and crossbar definitions.
On
Gregory,
Since you'll be resending this:
On Fri, Jun 27, 2014 at 12:55:47AM +0200, Gregory CLEMENT wrote:
On 27/06/2014 00:43, Gregory CLEMENT wrote:
The first bit of the SCU control register is actually the enable
it. So let's name it instead of using literal constant.
nit: s/^it/bit/
):
irqchip: nvic: Use the generic noop function
Jason Cooper (1):
Merge branch 'irqchip/urgent' into irqchip/core
Thomas Gleixner (13):
irqchip: spear_shirq: Kill pointless static
irqchip: spear_shirq: Move private structs to source
irqchip: spear_shirq: No point
Thomas,
Here's a round of fixes for irqchip. They've been in -next a few days
and are based on v3.16-rc1.
Please pull.
thx,
Jason.
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository
Thomas,
Here's a round of fixes for irqchip. They've been in -next a few days
and are based on v3.16-rc1.
Please pull.
thx,
Jason.
The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:
Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)
are available in the git repository
On Thu, Jun 19, 2014 at 09:34:36PM -, Thomas Gleixner wrote:
> The driver is broken for spear320 since commit 80515a5a(ARM: SPEAr3xx:
> shirq: simplify and move the shared irq multiplexor to DT). Clearly
> never tested on spear320.
>
> Aside of that it's an unreadable overengineered
On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com wrote:
> This patch set introduces support for MSI(-X) in GICv2m specification,
> which is implemented in some variation of GIC400.
>
> This depends on and has been tested with the V7 of "Add support for PCI in
> AArch64"
>
Suravee,
Please follow the convention for patch subject lines in this sub-system:
"irqchip: gic: ..."
thx,
Jason.
On Mon, Jun 23, 2014 at 07:32:59PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> Add new Irqchip declaration for GIC400. This was mentioned in
>
On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> This patch set introduces support for MSI(-X) in GICv2m specification,
> which is implemented in some variation of GIC400.
>
> This depends on and has been tested with the V7 of "Add
On Tue, Jun 24, 2014 at 09:55:27AM +0200, Gregory CLEMENT wrote:
> Hi Jason,
>
> >> This fix should be merged in 3.16 and maybe sent as a fix for 3.15
> >> too.
>
> [...]
>
> > Applied to mvebu/dt with Andrew's Ack.
>
> I think it should go mvebu/fixes as this patch modifies the binding,
>
On Tue, Jun 24, 2014 at 09:55:27AM +0200, Gregory CLEMENT wrote:
Hi Jason,
This fix should be merged in 3.16 and maybe sent as a fix for 3.15
too.
[...]
Applied to mvebu/dt with Andrew's Ack.
I think it should go mvebu/fixes as this patch modifies the binding,
sooner is better.
On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been
Suravee,
Please follow the convention for patch subject lines in this sub-system:
irqchip: gic: ...
thx,
Jason.
On Mon, Jun 23, 2014 at 07:32:59PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add new Irqchip declaration for GIC400.
On Mon, Jun 23, 2014 at 07:32:58PM -0500, suravee.suthikulpa...@amd.com wrote:
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 of Add support for PCI in
AArch64
On Thu, Jun 19, 2014 at 09:34:36PM -, Thomas Gleixner wrote:
The driver is broken for spear320 since commit 80515a5a(ARM: SPEAr3xx:
shirq: simplify and move the shared irq multiplexor to DT). Clearly
never tested on spear320.
Aside of that it's an unreadable overengineered trainwreck
On Mon, Jun 23, 2014 at 04:16:51PM +0200, Gregory CLEMENT wrote:
> Wildcards in compatible strings should be avoid. "marvell,armada38x"
> was recently introduced but was not yet used.
>
> The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs
> and more PCIe slots). So this patch
c: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: Russell King
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Gregory CLEMENT
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-ke
On Mon, Jun 23, 2014 at 10:57:41AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the mvebu tree got a conflict in
> arch/arm/mach-mvebu/Kconfig between commit 21278aeafbfa ("ARM: use
> menuconfig for sub-arch menus") from Linus' tree and commit
> 55fc83023212 ("ARM:
: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc: Gregory CLEMENT gregory.clem
On Mon, Jun 23, 2014 at 04:16:51PM +0200, Gregory CLEMENT wrote:
Wildcards in compatible strings should be avoid. marvell,armada38x
was recently introduced but was not yet used.
The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs
and more PCIe slots). So this patch
On Mon, Jun 23, 2014 at 10:57:41AM +1000, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the mvebu tree got a conflict in
arch/arm/mach-mvebu/Kconfig between commit 21278aeafbfa (ARM: use
menuconfig for sub-arch menus) from Linus' tree and commit
55fc83023212 (ARM: Kirkwood:
On Thu, Jun 19, 2014 at 09:34:37PM -, Thomas Gleixner wrote:
> The ras3 block on spear320 claims to have 3 interrupts. In fact it has
> one and 6 reserved interrupts. Account the 6 reserved to this block so
> it has 7 interrupts total. That matches the datasheet and the device
> tree entries.
Stefan,
On Mon, May 26, 2014 at 11:31:42PM +0300, Stefan Kristiansson wrote:
> In addition to consolidating the or1k-pic with other interrupt
> controllers, this makes OpenRISC less tied to its on-cpu
> interrupt controller.
>
> All or1k-pic specific parts are moved out of irq.c and into
>
Stefan,
On Mon, May 26, 2014 at 11:31:42PM +0300, Stefan Kristiansson wrote:
In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller.
All or1k-pic specific parts are moved out of irq.c and into
On Thu, Jun 19, 2014 at 09:34:37PM -, Thomas Gleixner wrote:
The ras3 block on spear320 claims to have 3 interrupts. In fact it has
one and 6 reserved interrupts. Account the 6 reserved to this block so
it has 7 interrupts total. That matches the datasheet and the device
tree entries.
uninitialized in this
function [-Wmaybe-uninitialized]
fs/direct-io.c:913:10: note: ‘from’ was declared here
are not necessary because dio_get_page() either fails, or sets both
'from' and 'to'.
Make the compiler happy so we can more easily detect legitimate
warnings.
Signed-off-by: Jason Cooper
On Mon, Jun 16, 2014 at 04:53:16PM +0530, Sricharan R wrote:
> From: Nishanth Menon
>
> On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131,
> 132, 133 are direct wired to hardware blocks bypassing crossbar.
> This quirky implementation is *NOT* supposed to be the expectation
> of
Sricharan,
Your subject line seems truncated:
"irqchip: crossbar: introduce ti,irqs-skip to skip"
maybe "... Introduce DT property to skip hardwired irqs" ?
Also note that you need to correct the subject line for *every* patch in
the series wrt capitalization.
I don't mind correcting it
On Wed, Jun 04, 2014 at 04:01:52PM +0100, Daniel Thompson wrote:
> Using the generic function saves looking up this custom one in a source
> navigator.
>
> Signed-off-by: Daniel Thompson
> Cc: Thomas Gleixner
> Cc: Jason Cooper
> ---
> drivers/irqchip/irq-nvic.c | 13
On Mon, Jun 09, 2014 at 11:05:02AM -0700, Florian Fainelli wrote:
> The driver was configuring the interrupt handler for the Level-2
> interrupts to be "level" triggered while they are in fact "edge"
> triggered. Fix this by using the correct handler.
>
> Reported-by: Brian Norris
>
On Thu, May 29, 2014 at 11:28:08PM +0300, Stefan Kristiansson wrote:
> On Tue, May 27, 2014 at 08:47:36AM +0200, Jonas Bonn wrote:
> > On 05/26/2014 10:52 PM, Geert Uytterhoeven wrote:
> > > CC devicetree for the bindings
> > >
> > > On Mon, May 26, 2014 at 10:31 PM, Stefan Kristiansson
> > >
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