On 27/07/18 13:59, Jorge Sanjuan wrote:
> From: Edward Cragg
>
> The CIF configuration and clock setting is currently hard coded for 2
> channels. Since the hardware is capable of supporting 1-8 channels add
> support for reading the channel count from the supplied parameters to
> allow for bet
On 27/07/18 13:59, Jorge Sanjuan wrote:
> From: Edward Cragg
>
> Add a callback to configure TDM settings for the Tegra30
> I2S ASoC 'platform' driver.
>
> Signed-off-by: Ben Dooks
> Signed-off-by: Edward Cragg
> [jorge.sanj...@codethink.co.uk: Style fixes]
> Signed-off-by: Jorge Sanjuan
>
L_TOTAL_SLOT_SHIFT)
> +#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK
> (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
> TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
>
> /* TDM mode slot enable bitmask */
> #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8
Thanks for fixing.
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
ra_alc5632_remove(struct platform_device
> *pdev)
>
> tegra_asoc_utils_fini(&machine->util_data);
>
> + of_node_put(tegra_alc5632_dai.cpu_of_node);
> + tegra_alc5632_dai.cpu_of_node = NULL;
> + tegra_alc5632_dai.platform_of_node = NULL;
> + of_node_put(tegra_alc5632_dai.codec_of_node);
> + tegra_alc5632_dai.codec_of_node = NULL;
> +
> return 0;
> }
Thanks!
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 18/07/18 07:30, Marcel Ziswiler wrote:
> On Tue, 2018-07-17 at 13:57 +0300, Mikko Perttunen wrote:
>> Thanks!
>
> Yes, that fixes Apalis TK1 crashing as of late as well.
>
>> Reviewed-by: Mikko Perttunen
>
> Tested-by: Marcel Ziswiler
Tested-by: Jon Hun
Adding Linus ...
On 17/07/18 16:30, Aapo Vienamo wrote:
...
> +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> +
> +The values accepted by power-source property are
> +TEGRA_IO_PAD_VOLTAGE_1V8 and TEGRA_IO_PAD_VOLTAGE_3V3, which are defined
> +in dt-bindings
7 +44,7 @@ Optional subnode-properties:
> - nvidia,tristate: Integer.
> 0: drive, 1: tristate.
> - nvidia,enable-input: Integer. Enable the pin's input path.
> -enable :TEGRA_PIN_ENABLE0 and
> +enable :TEGRA_PIN_ENABLE and
> disable or output only: TEGRA_PIN_DISABLE.
> - nvidia,open-drain: Integer.
> enable: TEGRA_PIN_ENABLE.
Acked-by: Jon Hunter
Thanks!
Jon
--
nvpublic
On 20/07/18 08:52, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> This fixes a spelling mistake.
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
> Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On 19/07/18 16:38, Dmitry Osipenko wrote:
> On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
>> On 19/07/18 14:24, Dmitry Osipenko wrote:
>>> This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
>>> timings for RAM code 0 registered&qu
On 19/07/18 14:24, Dmitry Osipenko wrote:
> This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
> timings for RAM code 0 registered" warning message during of kernels
> boot-up on Tegra20.
Looking at the tegra20-emc.txt bindings doc [0], the 'nvidia,ram-code'
property is also v
LEVEL_HIGH))
> irq_set_handler_locked(d, handle_level_irq);
> else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thanks for reporting this. I am seeing this as well on Tegra20 Ventana
and Tegra30 Cardhu looking at the boot log. Given that gpiochip_lock_as_irq
is checking the direction, the above fix looks good to me. So ...
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 17/07/18 10:08, Aapo Vienamo wrote:
> On Mon, 16 Jul 2018 21:03:08 +0100
> Jon Hunter wrote:
>
>> On 16/07/18 15:34, Aapo Vienamo wrote:
>>> Tegra SDHCI controllers require the SDHCI clock divider to be configured
>>> to divide the clock by two in DDR50
On 16/07/18 15:34, Aapo Vienamo wrote:
> Tegra SDHCI controllers require the SDHCI clock divider to be configured
> to divide the clock by two in DDR50/52 modes. Incorrectly configured
> clock divider results in corrupted data.
>
> Prevent the possibility of incorrectly calculating the divider v
On 13/07/18 16:39, Aapo Vienamo wrote:
...
>>> that it returns the current clock rate of the host instead of the
>>> maximum one, which can lead to unnecessarily small clock rates.
>>>
>>> This differs from the previous implementation of
>>> tegra_sdhci_get_max_clock() in that it doesn't divide
On 13/07/18 13:55, Aapo Vienamo wrote:
> This happens because sdhci_pltfm_clk_get_max_clock() does not actually
> return the maximum clock rate but the current one, leading to smaller
> clock rates on some platforms. I'll send a patch that fixes this for
> sdhci-tegra. Although this raises the qu
On 13/07/18 14:17, Aapo Vienamo wrote:
> Implement and use tegra_sdhci_get_max_clock() which returns the true
> maximum host clock rate. The issue with tegra_sdhci_get_max_clock() is
Don't you mean sdhci_pltfm_clk_get_max_clock above? Does this function
need fixing then? Or at least should there
On 12/07/18 14:11, Aapo Vienamo wrote:
> On Thu, 12 Jul 2018 13:59:58 +0100
> Jon Hunter wrote:
>
>> On 12/07/18 12:53, Aapo Vienamo wrote:
>>> From: Peter De-Schrijver
>>>
>>> These clocks have low jitter paths to certain parents. To model these
>
gates,
> @@ -1846,6 +2021,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
> .needs_mbist_war = true,
> .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
> .io_pads = tegra210_io_pads,
> + .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
> + .pin_descs = tegra210_pin_descs,
> .regs = &tegra20_pmc_regs,
> .init = tegra20_pmc_init,
> .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
> @@ -1896,6 +2073,10 @@ static const struct tegra_io_pad_soc
> tegra186_io_pads[] = {
> TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
> };
>
> +static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
> + TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
> +};
> +
> static const struct tegra_pmc_regs tegra186_pmc_regs = {
> .scratch0 = 0x2000,
> .dpd_req = 0x74,
> @@ -1949,6 +2130,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
> .has_impl_33v_pwr = true,
> .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
> .io_pads = tegra186_io_pads,
> + .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
> + .pin_descs = tegra186_pin_descs,
> .regs = &tegra186_pmc_regs,
> .init = NULL,
> .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 12/07/18 12:53, Aapo Vienamo wrote:
> From: Peter De-Schrijver
>
> These clocks have low jitter paths to certain parents. To model these
> correctly, use the sdmmc mux divider clock type.
>
> Signed-off-by: Peter De-Schrijver
> Signed-off-by: Aapo Vienamo
> Acked-by: Peter De Schrijver
>
clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -706,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char
> *name,
> const char * const *parent_names, u8 num_parents,
> unsigned long flags, void __iomem *reg, u8 clk_super_flags,
> spinlock_t *lock);
> +
> +/**
> + * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @reg: register controlling mux and divider
> + * @flags: hardware-specific flags
> + * @lock:optional register lock
> + * @gate:gate clock
> + * @gate_ops:gate clock ops
> + */
> +struct tegra_sdmmc_mux {
> + struct clk_hw hw;
> + void __iomem*reg;
> + spinlock_t *lock;
> + const struct clk_ops*gate_ops;
> + struct tegra_clk_periph_gategate;
> + u8 div_flags;
> +};
> +
> +#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
> +
> +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
> + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
> + unsigned long flags, void *lock);
> +
> /**
> * struct clk_init_table - clock initialization table
> * @clk_id: clock id as mentioned in device tree bindings
Acked-by: Jon Hunter
Cheers!
Jon
--
nvpublic
On 12/07/18 12:20, Peter De Schrijver wrote:
> On Thu, Jul 12, 2018 at 11:52:31AM +0100, Jon Hunter wrote:
>>
>> On 11/07/18 15:39, Aapo Vienamo wrote:
>>> From: Peter De-Schrijver
>>>
>>> Add a clock type to model the sdmmc switch divider clocks which
On 11/07/18 15:39, Aapo Vienamo wrote:
> From: Peter De-Schrijver
>
> Add a clock type to model the sdmmc switch divider clocks which have paths
> to source clocks bypassing the divider (Low Jitter paths). These
> are handled by selecting the lj path when the divider is 1 (ie the
> rate is the
gt; + return 0;
> +
> + divider_ux1 -= mul;
> +
> + if (divider_ux1 > div_mask(width))
> + return div_mask(width);
> +
> + return divider_ux1;
> +}
I think that personally, I would have preferred a clk-utils.c for stuff
like this but at the same time I am OK with this for now. It can always
be change later if we have such other similar functions. I also would
have updated the $subject now the name has been changed too.
Otherwise ...
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
ion(+)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index e1f8846..e3b9c22 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -19,6 +19,7 @@
>
> #include
> #include
> +#include
>
> /**
> * struct tegra_cl
On 12/07/18 08:52, Aapo Vienamo wrote:
> On Wed, 11 Jul 2018 16:26:42 +0100
> Jon Hunter wrote:
>
>> On 11/07/18 16:23, Jon Hunter wrote:
>>>
>>> On 11/07/18 15:01, Aapo Vienamo wrote:
>>>> Implement a function to query whether a pad is in deep po
a_io_pad_power_enable(enum tegra_io_pad id);
> int tegra_io_pad_power_disable(enum tegra_io_pad id);
> int tegra_io_pad_is_powered(enum tegra_io_pad id);
> -int tegra_io_pad_set_voltage(enum tegra_io_pad id,
> - enum tegra_io_pad_voltage voltage);
> -int tegra_io_pad_get_voltage(enum tegra_io_pad id);
>
> /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
> int tegra_io_rail_power_on(unsigned int id);
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
-1876,6 +1896,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
> .cpu_powergates = NULL,
> .has_tsense_reset = false,
> .has_gpu_clamps = false,
> + .has_impl_33v_pwr = true,
> .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
> .io_pads = tegra186_io_pads,
> .regs = &tegra186_pmc_regs,
> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
> index c32bf91..445aa66 100644
> --- a/include/soc/tegra/pmc.h
> +++ b/include/soc/tegra/pmc.h
> @@ -134,6 +134,7 @@ enum tegra_io_pad {
> TEGRA_IO_PAD_USB2,
> TEGRA_IO_PAD_USB3,
> TEGRA_IO_PAD_USB_BIAS,
> + TEGRA_IO_PAD_AO_HV,
> };
>
> /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 11/07/18 16:23, Jon Hunter wrote:
>
> On 11/07/18 15:01, Aapo Vienamo wrote:
>> Implement a function to query whether a pad is in deep power down mode.
> Can you elaborate on why this public function is needed and who will be
> using this?
Or I should say does this need
On 11/07/18 15:01, Aapo Vienamo wrote:
> Implement a function to query whether a pad is in deep power down mode.
Can you elaborate on why this public function is needed and who will be
using this?
Cheers
Jon
--
nvpublic
On 11/07/18 12:17, Peter De Schrijver wrote:
> On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:
>>
>> On 11/07/18 09:00, Peter De Schrijver wrote:
>>> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>>>>
>>>> On 09/07/18
On 11/07/18 11:12, Aapo Vienamo wrote:
> On Wed, 11 Jul 2018 10:46:21 +0100
> Jon Hunter wrote:
>
>> On 11/07/18 10:38, Aapo Vienamo wrote:
>>> On Wed, 11 Jul 2018 09:40:01 +0100
>>> Jon Hunter wrote:
>>>
>>>> On 10/07/18 13:54, Aap
On 11/07/18 10:38, Aapo Vienamo wrote:
> On Wed, 11 Jul 2018 09:40:01 +0100
> Jon Hunter wrote:
>
>> On 10/07/18 13:54, Aapo Vienamo wrote:
>>> Register a pinctrl device and implement get and set functions for
>>> PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_
On 11/07/18 10:23, Aapo Vienamo wrote:
> On Wed, 11 Jul 2018 09:30:57 +0100
> Jon Hunter wrote:
>
>> On 10/07/18 13:47, Aapo Vienamo wrote:
>>> Refactor the IO pad tables into macro tables so that they can be reused
>>> to generate pinctrl pin descriptor
T20 board but I don't
> get the interrupt I'm expecting. However, I don't get interrupts with
> the offending patch reverted so hopefully, this fix is sufficient.
Yes this fixes the problem. Feel free to add my ...
Tested-by: Jon Hunter
Cheers!
Jon
--
nvpublic
On 11/07/18 09:00, Peter De Schrijver wrote:
> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>>
>> On 09/07/18 17:38, Aapo Vienamo wrote:
>>> From: Peter De Schrijver
>>>
>>> Move this to a separate file so it can be used to calculate the
On 10/07/18 13:54, Aapo Vienamo wrote:
> Register a pinctrl device and implement get and set functions for
> PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters.
>
> Signed-off-by: Aapo Vienamo
> ---
> drivers/soc/tegra/pmc.c | 192
> ++
On 10/07/18 13:47, Aapo Vienamo wrote:
> Refactor the IO pad tables into macro tables so that they can be reused
> to generate pinctrl pin descriptors. Also add a name field which is
> needed by pinctrl.
>
> Signed-off-by: Aapo Vienamo
> ---
> drivers/soc/tegra/pmc.c | 231
> +
;
> + pinctrl-0 = <&sdmmc1_3v3>;
> + pinctrl-1 = <&sdmmc1_1v8>;
> + };
> + ...
> + sor@5454 {
> + ...
> + pinctrl-0 = <&hdmi_off>;
> + pinctrl-1 = <&hdmi_on>;
> + pinctrl-names = "hdmi-on", "hdmi-off";
> + };
> diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> new file mode 100644
> index 000..20f4340
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration
> constants
> + * pinctrl bindings.
> + *
> + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
> + *
> + * Author: Aapo Vienamo
> + */
> +
> +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
> +#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
> +
> +/* Voltage levels of the I/O pad's source rail */
> +#define TEGRA_IO_PAD_VOLTAGE_1V8 0
> +#define TEGRA_IO_PAD_VOLTAGE_3V3 1
> +
> +#endif
Looks good to me.
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
t tegra_powergate_sequence_power_up(unsigned int id,
> struct clk *clk,
>
> int tegra_io_pad_power_enable(enum tegra_io_pad id);
> int tegra_io_pad_power_disable(enum tegra_io_pad id);
> +int tegra_io_pad_is_powered(enum tegra_io_pad id);
> int tegra_io_pad_set_voltage(enum tegra_io_pad id,
d, request, status, mask);
> + if (err)
> + return err;
> +
> if (pmc->clk) {
> rate = clk_get_rate(pmc->clk);
> if (!rate) {
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 10/07/18 13:47, Aapo Vienamo wrote:
> Implement support for the PMC_IMPL_E_33V_PWR register which replaces
> PMC_PWR_DET register interface of the SoC generations preceding
> Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[]
> table.
>
> Signed-off-by: Aapo Vienamo
> ---
>
On 09/07/18 17:38, Aapo Vienamo wrote:
> From: Peter De Schrijver
>
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.
Sorry for not commenting sooner, but what is the motivation for moving
this to its own file? I don't see why we need to do this in order
Hi Alexandre,
On 26/06/18 22:31, Alexandre Belloni wrote:
> On 26/06/2018 17:54:57+0100, Jon Hunter wrote:
>>
>> On 26/06/18 17:15, Alexandre Belloni wrote:
>>> Hi,
>>>
>>> On 26/06/2018 16:51:40+0100, Jon Hunter wrote:
>>>>> rtc: tps
t;i2c: tegra: proper handling of error cases")
Cc: sta...@vger.kernel.org
Signed-off-by: Jon Hunter
---
drivers/i2c/busses/i2c-tegra.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 5fc
gt;num_clocks; i++) {
> + struct tegra_bpmp_clk *clk = bpmp->clocks[i];
> +
> + if (!clk)
> + continue;
> +
> + if (clk->id == id)
> + return &clk->hw;
> + }
>
> return NULL;
> }
Acked-by: Jon Hunter
Cheers!
Jon
--
nvpublic
On 26/06/18 17:15, Alexandre Belloni wrote:
> Hi,
>
> On 26/06/2018 16:51:40+0100, Jon Hunter wrote:
>>> rtc: tps6586x: let the core handle rtc range
>>
>> Sorry I am missing the original mail with the above change, but I
>> have noticed on v4.18-rc1 t
Hi Alexandre,
On 10/06/18 23:16, Alexandre Belloni wrote:
> Hi Linus,
>
> Here is the pull-request for the RTC subsystem for 4.18.
>
> Setting the supported range from drivers for RTCs failing soon has
> started. A few fixes are developed along the way.
> Some drivers have been switched to SPDX
};
>
> @@ -382,6 +403,13 @@
> };
> };
>
> + tcu: tcu {
> + compatible = "nvidia,tegra194-tcu";
> + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
> + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
> + mbox-names = "rx", "tx";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts =
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 20/06/18 13:20, Mikko Perttunen wrote:
> The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
> multiplexing multiple "virtual UARTs" into a single hardware serial
> port. The TCU is the primary serial port on Tegra194 devices.
>
> Add a TCU driver utilizing the mailbox fram
to request doorbell IRQ#%u: %d\n",
> + hsp->doorbell_irq, err);
> + goto unregister_mbox_controller;
> + }
> + }
> +
> + if (hsp->shared_irq) {
> + err = devm_request_irq(&pdev->dev, hsp->shared_irq,
> +tegra_hsp_shared_irq, 0,
> +dev_name(&pdev->dev), hsp);
> + if (err < 0) {
> + dev_err(&pdev->dev,
> + "failed to request shared0 IRQ%u: %d\n",
> + hsp->shared_irq, err);
> + goto unregister_mbox_controller;
> + }
> }
>
> return 0;
> +
> +unregister_mbox_controller:
> + mbox_controller_unregister(&hsp->mbox);
> +remove_doorbells:
> + if (hsp->doorbell_irq)
> + tegra_hsp_remove_doorbells(hsp);
This bit looks like it should have been a separate patch to fix the
clean-up if probe fails. However, unless there is a reason to re-spin
the series, probably OK.
> +
> + return err;
> }
>
> static int tegra_hsp_remove(struct platform_device *pdev)
> @@ -482,7 +651,8 @@ static int tegra_hsp_remove(struct platform_device *pdev)
> struct tegra_hsp *hsp = platform_get_drvdata(pdev);
>
> mbox_controller_unregister(&hsp->mbox);
> - tegra_hsp_remove_doorbells(hsp);
> + if (hsp->doorbell_irq)
> + tegra_hsp_remove_doorbells(hsp);
>
> return 0;
> }
>
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
hsp->mbox.txdone_poll = false;
> - hsp->mbox.ops = &tegra_hsp_doorbell_ops;
> + hsp->mbox.ops = &tegra_hsp_ops;
>
> hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans,
> sizeof(*hsp->mbox.chans),
> @@ -427,11 +465,12 @@ static int tegra_hsp_probe(struct platform_device *pdev)
> return err;
> }
>
> - err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq,
> -IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp);
> + err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
> +tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
> +dev_name(&pdev->dev), hsp);
> if (err < 0) {
> - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
> - hsp->irq, err);
> + dev_err(&pdev->dev, "failed to request doorbell IRQ#%u: %d\n",
> + hsp->doorbell_irq, err);
> return err;
> }
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
mailbox subsystem, and the specifiers implemented by the relevant
> +provider(s):
> +
> +- .../mailbox/mailbox.txt
> +- .../mailbox/nvidia,tegra186-hsp.txt
> +
> +Example bindings:
> +-
> +
> +tcu: tcu {
> + compatible = "nvidia,tegra194-tcu";
> + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
> + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
> + mbox-names = "rx", "tx";
> +};
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
pts supported by the HSP instance minus one.
> Users of this binding MUST look up entries in the interrupt property
> by name, using this interrupt-names property to do so.
> - interrupts
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 31/05/18 12:40, Lucas Stach wrote:
> Hi Ulf,
>
> Am Donnerstag, den 31.05.2018, 12:59 +0200 schrieb Ulf Hansson:
>> To support devices being partitioned across multiple PM domains, let's
>> begin with extending genpd to cope with these kind of configurations.
>>
>> Therefore, add a new export
On 31/05/18 11:44, Ulf Hansson wrote:
> On 31 May 2018 at 10:03, Jon Hunter wrote:
>>
>> On 31/05/18 07:17, Ulf Hansson wrote:
>>> [...]
>>>
>>>>> +/**
>>>>> + * genpd_dev_pm_attach_by_id() - Attach a device to one of its PM domain.
On 31/05/18 07:17, Ulf Hansson wrote:
> [...]
>
>>> +/**
>>> + * genpd_dev_pm_attach_by_id() - Attach a device to one of its PM domain.
>>> + * @dev: Device to attach.
>>
>> Can you update the description of the above as well?
>
> Yes, like below?
>
> genpd_dev_pm_attach_by_id() - Associate a
/*
> + * Devices with multiple PM domains must be attached separately, as we
> + * can only attach one PM domain per device.
> + */
> + if (of_count_phandle_with_args(dev->of_node, "power-domains",
> +"#power-domain-cells") != 1)
> + return 0;
> +
> + return __genpd_dev_pm_attach(dev, dev->of_node, 0);
> +}
> EXPORT_SYMBOL_GPL(genpd_dev_pm_attach);
>
> static const struct of_device_id idle_state_match[] = {
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Cheers
Jon
--
nvpublic
and prevent it from attach any PM domain for this case. Instead,
> leave this to be managed separately, from following changes to genpd.
>
> Cc: Rob Herring
> Cc: devicet...@vger.kernel.org
> Suggested-by: Jon Hunter
> Signed-off-by: Ulf Hansson
> ---
>
> Chang
On 29/05/18 11:04, Ulf Hansson wrote:
> To support devices being partitioned across multiple PM domains, let's
> begin with extending genpd to cope with these kind of configurations.
>
> Therefore, add a new exported function genpd_dev_pm_attach_by_id(), which
> is similar to the existing genpd_
On 30/05/18 16:12, Jon Hunter wrote:
> The call to hw_params for a component fails the error code is held by
> the variable '__ret' but the error message displays the value held by
> the variable 'ret'. Fix the return code shown when hw_params fails for
> a compon
_soc_component_driver has snd_pcm_ops")
Signed-off-by: Jon Hunter
---
sound/soc/soc-pcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 2df4719a84db..9376eb476364 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
nt_driver has snd_pcm_ops")
Signed-off-by: Jon Hunter
---
sound/soc/soc-pcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 2df4719a84db..9376eb476364 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -956,7 +956,7 @
On 30/05/18 12:31, Ulf Hansson wrote:
> On 30 May 2018 at 11:19, Jon Hunter wrote:
>> Hi Ulf,
>>
>> On 29/05/18 11:04, Ulf Hansson wrote:
>>> The existing dev_pm_domain_attach() function, allows a single PM domain to
>>> be attached per device. To be able
Hi Ulf,
On 29/05/18 11:04, Ulf Hansson wrote:
> The existing dev_pm_domain_attach() function, allows a single PM domain to
> be attached per device. To be able to support devices that are partitioned
> across multiple PM domains, let's introduce a new interface,
> dev_pm_domain_attach_by_id().
>
On 25/05/18 11:45, Ulf Hansson wrote:
...
Right, but this case still seems like an error. My understanding is that
only drivers will use this API directly and it will not be used by the
device driver core (unlike dev_pm_domain_attach), so if anyone calls this
attempting to attach another PM d
On 24/05/18 22:11, Ulf Hansson wrote:
On 24 May 2018 at 17:48, Jon Hunter wrote:
On 18/05/18 11:31, Ulf Hansson wrote:
The existing dev_pm_domain_attach() function, allows a single PM domain to
be attached per device. To be able to support devices that are partitioned
across multiple PM
On 24/05/18 22:21, Ulf Hansson wrote:
...
OK, so this bit is a to-do as that is not yet exposed AFAICT. I see that you
said 'although we need to extend it to cover cleanup of the earlier
registered device, via calling device_unregister().' So if we do this then
that would be fine.
Let me cla
On 18/05/18 11:31, Ulf Hansson wrote:
The existing dev_pm_domain_attach() function, allows a single PM domain to
be attached per device. To be able to support devices that are partitioned
across multiple PM domains, let's introduce a new interface,
dev_pm_domain_attach_by_id().
The dev_pm_domai
On 24/05/18 13:17, Ulf Hansson wrote:
On 24 May 2018 at 11:36, Jon Hunter wrote:
On 24/05/18 08:04, Ulf Hansson wrote:
...
Any reason why we could not add a 'boolean' argument to the API to
indicate
whether the new device should be linked? I think that I prefer the API
handles
On 24/05/18 08:04, Ulf Hansson wrote:
...
Any reason why we could not add a 'boolean' argument to the API to indicate
whether the new device should be linked? I think that I prefer the API
handles it, but I can see there could be instances where drivers may wish to
handle it themselves.
Comi
On 23/05/18 10:47, Ulf Hansson wrote:
On 23 May 2018 at 11:45, Jon Hunter wrote:
On 23/05/18 10:33, Ulf Hansson wrote:
On 23 May 2018 at 11:27, Rajendra Nayak wrote:
On 05/23/2018 02:37 PM, Jon Hunter wrote:
On 23/05/18 07:12, Ulf Hansson wrote:
...
Thanks for sending this
On 23/05/18 10:33, Ulf Hansson wrote:
On 23 May 2018 at 11:27, Rajendra Nayak wrote:
On 05/23/2018 02:37 PM, Jon Hunter wrote:
On 23/05/18 07:12, Ulf Hansson wrote:
...
Thanks for sending this. Believe it or not this has still been on my to-do list
and so we definitely need a solution
On 23/05/18 07:12, Ulf Hansson wrote:
...
Thanks for sending this. Believe it or not this has still been on my to-do list
and so we definitely need a solution for Tegra.
Looking at the above it appears that additional power-domains exposed as devices
to the client device. So I assume that thi
On 22/05/18 15:47, Ulf Hansson wrote:
[...]
+/**
+ * genpd_dev_pm_attach_by_id() - Attach a device to one of its PM domain.
+ * @dev: Device to attach.
+ * @index: The index of the PM domain.
+ *
+ * Parse device's OF node to find a PM domain specifier at the provided @index.
+ * If such is f
sdhci@346";
sdhci1 = "/cbb/sdhci@340";
- serial0 = &uartb;
+ serial0 = &tcu;
i2c0 = "/bpmp/i2c";
i2c1 = "/cbb/i2c@316";
i2c2 = "/cbb/i2c@c24";
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 08/05/18 12:44, Mikko Perttunen wrote:
Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
for the TOP0 HSP instance, and finally the TCU node itself. Also
mark the HSP instances as compatible to tegra194-hsp,
On 08/05/18 12:44, Mikko Perttunen wrote:
The Tegra HSP block supports 'shared mailboxes' that are simple 32-bit
registers consisting of a FULL bit in MSB position and 31 bits of data.
The hardware can be configured to trigger interrupts when a mailbox
is empty or full. Add support for these sha
On 08/05/18 12:43, Mikko Perttunen wrote:
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code.
Signed-off-by: Mikko Perttunen
---
drivers
On 08/05/18 12:43, Mikko Perttunen wrote:
Non-doorbell interrupts are routed through "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp device
tree bindings.
Reading the Tegra documentation
On 08/05/18 12:43, Mikko Perttunen wrote:
Add bindings for the Tegra Combined UART device used to talk to the
UART console on Tegra194 systems.
Signed-off-by: Mikko Perttunen
---
.../bindings/serial/nvidia,tegra194-tcu.txt| 35 ++
1 file changed, 35 insertions(+)
Hi Ulf,
On 18/05/18 11:31, Ulf Hansson wrote:
> To support devices being partitioned across multiple PM domains, let's
> start by extending genpd to cope with these configurations.
>
> More precisely, add a new exported function, genpd_dev_pm_attach_by_id(),
> similar to genpd_dev_pm_attach(), bu
to usb_create_hcd()
before we enable the hardware.
Signed-off-by: Jon Hunter
Acked-by: Thierry Reding
---
Changes since V2:
- Add Thierry's ACK
Changes since V1:
- None
drivers/usb/host/xhci-tegra.c | 34 +-
1 file changed, 17 insertions(+), 17 dele
Add runtime PM support to the Tegra XHCI driver and move the function
calls to enable/disable the clocks, regulators and PHY into the runtime
PM callbacks.
Signed-off-by: Jon Hunter
Acked-by: Thierry Reding
---
Changes since V2:
- Remove extra unnecessary blank line
- Add Thierry'
PM domain provider and so these are only these are only
needed in the case where there is no generic PM domain.
Signed-off-by: Jon Hunter
Acked-by: Thierry Reding
---
Changes since V2:
- Add Thierry's ACK
Changes since V1:
- None
drivers/usb/host/xh
PM domain provider and so these are only these are only
needed in the case where there is no generic PM domain.
Signed-off-by: Jon Hunter
---
Changes since V1:
- None
drivers/usb/host/xhci-tegra.c | 68 +++
1 file changed, 49 insertions(+), 19 deletions(-)
Add runtime PM support to the Tegra XHCI driver and move the function
calls to enable/disable the clocks, regulators and PHY into the runtime
PM callbacks.
Signed-off-by: Jon Hunter
---
Changes since V1:
- Re-worked change to handle case where runtime PM is disabled.
drivers/usb/host/xhci
to usb_create_hcd()
before we enable the hardware.
Signed-off-by: Jon Hunter
---
Changes since V1:
- None
drivers/usb/host/xhci-tegra.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci
gt; TEGRA KBC DRIVER
> -M: Rakesh Iyer
> M: Laxman Dewangan
> S: Supported
> F: drivers/input/keyboard/tegra-kbc.c
>
Acked-by: Jon Hunter
Cheers!
Jon
#include
> #include
> @@ -725,7 +726,7 @@ static int tegra_powergate_of_get_clks(struct
> tegra_powergate *pg,
> unsigned int i, count;
> int err;
>
> - count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
> + count = of_clk_get_parent_count(np);
> if (count == 0)
> return -ENODEV;
>
>
Acked-by: Jon Hunter
Cheers
Jon
On 13/03/18 09:51, Peter De Schrijver wrote:
> On Mon, Mar 12, 2018 at 12:15:22PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
>>> support in this driver. Also
On 13/03/18 09:03, Peter De Schrijver wrote:
> On Mon, Mar 12, 2018 at 11:08:51AM +0000, Jon Hunter wrote:
>>
>> On 12/03/18 09:14, Peter De Schrijver wrote:
>>> On Thu, Mar 08, 2018 at 10:50:06PM +, Jon Hunter wrote:
>>>>
>>>> On 06/02/18 1
On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> support in this driver. Also allow for the case where the CPU voltage is
> controlled directly by the DFLL rather than by a separate regulator object.
>
> Signed-off-by: Peter De
On 12/03/18 09:14, Peter De Schrijver wrote:
> On Thu, Mar 08, 2018 at 10:50:06PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> This patch prepares the dfll driver to work with PWM regulators.
>>> To do this we introduce a new arr
On 09/03/18 08:14, Peter De Schrijver wrote:
> On Thu, Mar 08, 2018 at 11:25:04PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
>>> support in this driver. Also
On 09/03/18 09:13, Mathias Nyman wrote:
> On 09.03.2018 10:36, Thierry Reding wrote:
>> On Thu, Mar 08, 2018 at 09:31:07PM +0000, Jon Hunter wrote:
>>>
>>> On 01/03/18 14:18, Mathias Nyman wrote:
>>>> On 14.02.2018 18:34, Jon Hunter wrote:
>>>>&g
On 09/03/18 08:36, Thierry Reding wrote:
> On Thu, Mar 08, 2018 at 09:31:07PM +0000, Jon Hunter wrote:
>>
>> On 01/03/18 14:18, Mathias Nyman wrote:
>>> On 14.02.2018 18:34, Jon Hunter wrote:
>>>> Add runtime PM support to the Tegra XHCI driver and move the f
On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> support in this driver. Also allow for the case where the CPU voltage is
> controlled directly by the DFLL rather than by a separate regulator object.
>
> Signed-off-by: Peter De
ra124.o
> obj-y += cvb.o
> obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
>
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 06/02/18 16:34, Peter De Schrijver wrote:
> Add new properties to configure the DFLL PWM regulator support. Also
> add an example and make the I2C clock only required when I2C support is
> used.
>
> Signed-off-by: Peter De Schrijver
> ---
> .../bindings/clock/nvidia,tegra124-dfll.txt
On 06/02/18 16:34, Peter De Schrijver wrote:
> The DFLL can directly generate a PWM signal to control the regulator IC
> rather then sending i2c messages. This patch adds support for this mode.
> In this mode the hardware LUT is not used and also there is no regulator
> object involved because the
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