No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9..f7ba0
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" s
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
b/Documentation
) Fix error handling code
5) Include DT patches in this series (I can send this separately to DT
MAINTAINER once the driver patches are merged)
[1] -> http://lore.kernel.org/r/20201103035556.21260-1-kis...@ti.com
Kishon Vijay Abraham I (14):
phy: cadence: Sierra: Fix PHY power_on sequence
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file
Hi,
On 21/12/20 4:36 am, Ahmad Fatoum wrote:
> Hello,
>
> I just noticed that USB controller drivers differ in the order in which they
> do phy_init and phy_power_on. For example:
>
> __dwc2_lowlevel_hw_enable():
>
> ret = phy_power_on(hsotg->phy);
> if (ret == 0)
Hi Rob,
On 05/11/20 11:33 pm, Rob Herring wrote:
> On Tue, Nov 03, 2020 at 09:25:48AM +0530, Kishon Vijay Abraham I wrote:
>> Add binding for the PLLs within SERDES.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> .../bindings/phy/
Hi Rob,
On 16/12/20 10:31 pm, Rob Herring wrote:
> On Wed, Dec 16, 2020 at 9:01 AM Kishon Vijay Abraham I wrote:
>>
>> Hi Rob,
>>
>> On 15/12/20 9:23 pm, Rob Herring wrote:
>>> On Tue, Dec 15, 2020 at 1:00 AM Kishon Vijay Abraham I
>>> wrote:
>
Hi Rob,
On 15/12/20 9:23 pm, Rob Herring wrote:
> On Tue, Dec 15, 2020 at 1:00 AM Kishon Vijay Abraham I wrote:
>>
>> From: Nadeem Athani
>>
>> Cadence controller will not initiate autonomous speed change if strapped as
>> Gen2. The Retrain Link bit is set as
Hi,
On 14/12/20 8:35 pm, Rob Herring wrote:
> On Sun, Dec 13, 2020 at 10:21 PM Kishon Vijay Abraham I wrote:
>>
>> Hi Nadeem,
>>
>> On 12/12/20 12:37 pm, Athani Nadeem Ladkhan wrote:
>>> Hi Rob / Kishon,
>>>
>>>> -Original Message---
From: Nadeem Athani
Cadence controller will not initiate autonomous speed change if strapped as
Gen2. The Retrain Link bit is set as quirk to enable this speed change.
Signed-off-by: Nadeem Athani
[kis...@ti.com: Enable the workaround for TI's J721E SoC]
Signed-off-by: Kishon Vijay Abra
t; ; Bjorn Helgaas ; PCI
>> ; linux-kernel@vger.kernel.org; Kishon Vijay
>> Abraham I ; devicet...@vger.kernel.org; Milind Parab
>> ; Swapnil Kashinath Jakhade
>> ; Parshuram Raju Thombare
>>
>> Subject: Re: [PATCH v4 1/2] dt-bindings: pci: Retrain Link to work around
&
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts| 15 +++
1 file changed, 15 insertions
Add dt node for the single instance of WIZ and SERDES module
shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
dts: ti: k3-j721e-main: Add PCIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ---
1 file changed, 8 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.
value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4
1 file changed, 4 deletions(-)
v1 of the patch series is sent [1]
Changes from v1:
1) Include only the device tree patches here (the binding patch is sent
separately)
2) Include couple of patches that fixes J721E DTS.
[1] -> http://lore.kernel.org/r/20201102101154.13598-1-kis...@ti.com
Kishon Vijay Abraham I (6):
ar
Add host mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,
Add PCIe EP mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/p
o76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
drivers/pci/controller/cadence/pci-j721e.c | 28 +++---
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/cadence/
usjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's
J721E SoC")
Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E
SoC")
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
://lore.kernel.org/r/20201105165627.GA1474647@bogus
Ack for "PCI: j721e: Get offset within "syscon" from
"ti,syscon-pcie-ctrl" phandle arg"
http://lore.kernel.org/r/cal_jsqkqwx2qkjb5easutdhh5devc+xh33yxrcbwe+ocrrq...@mail.gmail.com
Kishon Vijay Abraham I (4):
dt-b
Hi Lorenzo,
On 10/12/20 12:17 pm, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 04/12/20 1:21 pm, Kishon Vijay Abraham I wrote:
>> Previously a subnode to syscon node was added which has the
>> exact memory mapped address of pcie_ctrl but based on review comment
>&g
Hi Lorenzo,
On 04/12/20 1:21 pm, Kishon Vijay Abraham I wrote:
> Previously a subnode to syscon node was added which has the
> exact memory mapped address of pcie_ctrl but based on review comment
> provided by Rob [1], the offset is now being passed as argument to
> "ti,syscon-p
Hi Dave,
On 07/12/20 9:25 pm, Jiang, Dave wrote:
>
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: Wednesday, November 11, 2020 8:36 AM
>> To: Bjorn Helgaas ; Jonathan Corbet
>> ; Kishon Vijay Abraham I ; Lorenzo
>> Pieral
Hi Dave,
On 07/12/20 9:27 pm, Jiang, Dave wrote:
>
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I
>> Sent: Wednesday, November 11, 2020 8:36 AM
>> To: Bjorn Helgaas ; Jonathan Corbet
>> ; Kishon Vijay Abraham I ; Lorenzo
>> Pieral
+Lorenzo, Bjorn, Rob
Hi Guennadi,
On 04/12/20 11:21 pm, Mathieu Poirier wrote:
> I am adding Vincent Whitchurch and the virtualization mailing list...
>
> On Thu, 3 Dec 2020 at 13:42, Guennadi Liakhovetski
> wrote:
>>
>> (adding vhost maintainers and the author of [1])
>>
>> Hi,
>>
>> I'm worki
dts: ti: k3-j721e-main: Add PCIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ---
1 file changed, 8 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dt
o76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 28 +++---
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/control
usjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's
J721E SoC")
Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E
SoC")
Signed-off-by: Kishon Vijay Abraham I
---
.../d
ver change
should be merged first and the driver takes care of maintaining old
DT compatibility.
Changes frm v1:
*) Remove use of allOf in schema
*) Added Fixes tag
*) Maintain old DT compatibility
[1] ->
http://lore.kernel.org/r/cal_jsqkiuco76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Hi Tom, Nadeem,
On 27/10/20 12:50 am, Rob Herring wrote:
> On Fri, Oct 23, 2020 at 1:57 AM Kishon Vijay Abraham I wrote:
>>
>> Hi Nadeem,
>>
>> On 19/10/20 10:48 pm, Athani Nadeem Ladkhan wrote:
>>> Hi Kishon,
>>>
>>>> -----Original
Hi Rob,
On 20/11/20 10:39 am, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 19/11/20 2:41 am, Rob Herring wrote:
>> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle
Hi Rob,
On 19/11/20 2:41 am, Rob Herring wrote:
> On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote:
>> Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
>> argument. The argument is the register offset within "sys
igned-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,
has to
get in together in the -rc cycle.
[1] -> Link:
http://lore.kernel.org/r/cal_jsqkiuco76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Kishon Vijay Abraham I (3):
dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
PCI: j721e: Get offset within "
rgument to "ti,syscon-pcie-ctrl"
phandle.
Link:
http://lore.kernel.org/r/cal_jsqkiuco76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 28 +++---
1 file changed, 19 inser
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node
point to the parent with an offset argument.
Link:
http://lore.kernel.org/r/cal_jsqkiuco76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e
Hi Arnd,
On 16/11/20 9:07 pm, Arnd Bergmann wrote:
> On Mon, Nov 16, 2020 at 6:19 AM Kishon Vijay Abraham I wrote:
>> On 12/11/20 6:54 pm, Arnd Bergmann wrote:
>>>
>>> This looks very promising indeed, I need to read up on the whole
>>> discussion there. I al
Hi Arnd,
On 12/11/20 6:54 pm, Arnd Bergmann wrote:
> On Tue, Nov 10, 2020 at 4:42 PM Kishon Vijay Abraham I wrote:
>> On 10/11/20 8:29 pm, Arnd Bergmann wrote:
>>> On Tue, Nov 10, 2020 at 3:20 PM Kishon Vijay Abraham I
>>> wrote:
>>>> On 10/11/20 7:55
Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 44 ++---
.../pci/controller/dwc/pcie
Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 207 --
drivers/pci/controller/cadence/pcie-cadence.h
Add binding to specify virtual function (associated with each physical
function) in endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-ep.yaml | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci
]
v1 of the patch series can be found @ [1]
[1] -> http://lore.kernel.org/r/20191231113534.30405-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/2020153559.19050-1-kis...@ti.com
Kishon Vijay Abraham I (6):
dt-bindings: PCI: pci-ep: Add binding to specify virtual function
PCI: endpoin
Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index
Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint
While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 24
Hi Sherry,
On 11/11/20 8:19 am, Sherry Sun wrote:
> Hi Kishon,
>
>> Subject: Re: [PATCH v7 15/18] NTB: Add support for EPF PCI-Express Non-
>> Transparent Bridge
>>
>> Hi Sherry, Arnd,
>>
>> On 10/11/20 8:29 pm, Arnd Bergmann wrote:
>>> On
Hi Rob,
On 12/11/20 2:58 am, Rob Herring wrote:
> On Mon, Nov 09, 2020 at 10:34:03PM +0530, Kishon Vijay Abraham I wrote:
>> Add binding documentation for "syscon" which should be a subnode of
>> the system controller (scm-conf).
>>
>> Signed-off-by: Kishon V
device has configurable number of memory windows
(Max 4), configurable number of doorbell (Max 32), and configurable
number of scratch-pad registers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/ntb/hw/Kconfig | 1 +
drivers/ntb/hw/Makefile | 1 +
drivers/ntb/hw/epf
Add binding documentation for pci-ntb endpoint function that helps in
adding and configuring pci-ntb endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/function/binding/pci-ntb.rst | 38 +++
Documentation/PCI/endpoint/index.rst | 1 +
2 files
Add documentation to help users use pci-epf-ntb function driver and
existing host side NTB infrastructure for NTB functionality.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Randy Dunlap
---
Documentation/PCI/endpoint/index.rst | 1 +
Documentation/PCI/endpoint/pci-ntb
Invoke ntb_link_enable() to enable the NTB/PCIe link on the local
or remote side of the bridge.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/ntb/test/ntb_tool.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c
index b7bf3f863d79
Add a new endpoint function driver to provide NTB functionality
using multiple PCIe endpoint instances.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile |1 +
drivers/pci/endpoint/functions/pci-epf
ributes that has to be exposed to the user.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 23 +++
include/linux/pci-epf.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c
b/drivers/p
Add TI J721E device to the pci id database. Since this device has
a configurable PCIe endpoint, it could be used with different
drivers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 -
include/linux/pci_ids.h | 1 +
2 files changed, 1 insertion(+), 1
ace).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index 1fe6b8baca97..4e4eb30cd
Implement ->msi_map_irq() ops in order to map physical address to
MSI address and return MSI data.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/controller/cadence/p
single EPC device with a EPF device will continue to work.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/pci-endpoint-cfs.rst | 10 ++
drivers/pci/endpoint/pci-ep-cfs.c | 147 ++
2 files changed, 157 insertions(+)
diff --git a/Documentat
. This is in
preparation for adding NTB endpoint function driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 11 ++--
drivers/pci/endpoint/pci-ep-cfs.c | 6 +-
drivers/pci/endpoint/pci-epc-core.c | 47 +++
drivers/pci
directly write to the physical address (in outbound
region) of the other interface to ring doorbell using MSI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 41 +
include/linux/pci-epc.h | 8 ++
2 files changed, 49
be populated by the function driver if it has to
expose any function specific attributes and pci_epf_type_add_cfs() to
be invoked by pci-ep-cfs.c when sub-directory to main function directory
is created.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c |
Remove unused pci_epf_match_device() function added in pci-epf-core.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 16
include/linux/pci-epf.h | 2 --
2 files changed, 18 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epf
m
[7] -> http://lore.kernel.org/r/20200918064227.1463-1-kis...@ti.com
[8] -> http://lore.kernel.org/r/20200924092519.17082-1-kis...@ti.com
[9] -> https://youtu.be/dLKKxrg5-rY
[10] -> http://lore.kernel.org/r/20200930153519.7282-1-kis...@ti.com
Kishon Vijay Abraham I (18):
Documentation: PCI:
Add specification for the *PCI NTB* function device. The endpoint function
driver and the host PCI driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/endpoint/index.rst | 1 +
.../PCI/endpoint/pci-ntb-function.rst
Modify pci_epc_get_next_free_bar() and pci_epc_get_first_free_bar() to
return error values if there are no free BARs available.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 2 ++
drivers/pci/endpoint/pci-epc-core.c | 12
Add an API to get the next unreserved BAR starting from a given BAR
number that can be used by the endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 26 ++
include/linux/pci-epc.h | 2 ++
2 files changed, 24
ount 64 bit BAR while
returning the first free unreserved BAR.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epc-core.c
b/drivers/pci/endpoint/pci-e
Hi Sherry, Arnd,
On 10/11/20 8:29 pm, Arnd Bergmann wrote:
> On Tue, Nov 10, 2020 at 3:20 PM Kishon Vijay Abraham I wrote:
>> On 10/11/20 7:55 am, Sherry Sun wrote:
>
>>> But for VOP, only two boards are needed(one board as host and one board as
>>> card) to
>>
>>>> Subject: [PATCH v7 15/18] NTB: Add support for EPF PCI-Express Non-
>>>> Transparent Bridge
>>>>
>>>> From: Kishon Vijay Abraham I
>>>>
>>>> Add support for EPF PCI-Express Non-Transparent Bridge (NTB) device.
&g
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts| 15 +++
1 file changed, 15 insertions
Add PCIe EP mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/p
Add host mode dt-bindings for TI's J7200 SoC.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
.../bindings/pci/ti,j721e-pci-host.yaml | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
Add dt node for the single instance of WIZ and SERDES module
shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 57 +++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b
Add binding documentation for "syscon" which should be a subnode of
the system controller (scm-conf).
Signed-off-by: Kishon Vijay Abraham I
---
.../mfd/ti,j721e-system-controller.yaml | 40 +++
1 file changed, 40 insertions(+)
diff --git
a/Documentation/
bound-regions" for RC mode.
*) Remove patches specific to J721E
V1 of the patch series can be found @:
http://lore.kernel.org/r/20201102101154.13598-1-kis...@ti.com
Kishon Vijay Abraham I (7):
dt-bindings: mfd: ti,j721e-system-controller.yaml: Document "syscon"
dt-bindings: PCI
Hi Sherry,
On 09/11/20 3:07 pm, Sherry Sun wrote:
> Hi Kishon,
>
>> Subject: [PATCH v7 15/18] NTB: Add support for EPF PCI-Express Non-
>> Transparent Bridge
>>
>> From: Kishon Vijay Abraham I
>>
>> Add support for EPF PCI-Express Non-Transparent Bridg
Hi Rob,
On 05/11/20 10:24 pm, Rob Herring wrote:
> On Mon, Nov 02, 2020 at 03:41:47PM +0530, Kishon Vijay Abraham I wrote:
>> Add binding documentation for "pcie-ctrl" which should be a subnode of
>> the system controller.
>>
>> Signed-off-by: Kishon Vijay
Now that "cdns,max-outbound-regions" is made an optional property, do
not error out if "cdns,max-outbound-regions" device tree property is
not found.
Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/
Make "cdns,max-outbound-regions" optional DT property in all the
platforms using Cadence PCIe core.
Kishon Vijay Abraham I (2):
dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
PCI: cadence: Do not error if "cdns,max-outbound-regions"
Make "cdns,max-outbound-regions" optional property with the default
being 32.
Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml| 3 ---
Documentation/devicetree/bindings/pc
Hi Rob,
On 05/11/20 10:23 pm, Rob Herring wrote:
> On Mon, Nov 02, 2020 at 10:41:37AM -0600, Nishanth Menon wrote:
>> On 15:41-20201102, Kishon Vijay Abraham I wrote:
>>> PCIe controller in J721E supports a maximum of 32 outbound regions.
>>> commit 4e5833884f66 (&qu
3631.GA3026331@bogus
[2] ->
http://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakh...@cadence.com
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721e-main: Fix PCIe maximum outbound regions
arm64: dts: ti: k3-j721e-common-proc-board: Re-name link name as "phy"
arch/ar
ommon-proc-board: Configure
the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for
USB0")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
CIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e2a96b2c423c.
+Alan
Hi Jon Mason, Allen Hubbe, Dave Jiang,
On 20/10/20 6:48 pm, Lorenzo Pieralisi wrote:
> On Tue, Oct 20, 2020 at 01:45:45PM +0530, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On 05/10/20 11:27 am, Kishon Vijay Abraham I wrote:
>>> Hi Jon Mason, Allen Hubbe, Dav
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 39 +++-
1 file changed, 38 insertions
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as
clocks so that it's possible to select one of these two inputs from
device tree.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadenc
any of the plls are
already locked. This is done by adding an already_configured flag
and using it to gate every register access as well as any phy_ops.
Signed-off-by: Faiz Abbas
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 127 ++-
1
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
b/Documentation
actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 453ef26fa1c7..4429f41a8f58 100644
--- a/drivers/phy/cadence/p
node's name is "phy".
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index c9cfafe89cbf..d57d29382ce4 100644
--- a/drivers/phy/ti/p
seamlessly use any of the external reference clocks.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 177 +++
1 file changed, 177 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
any of the lanes has
already been enabled.
While we are here, also fix the wiz_init() to be called before the
of_platform_device_create() call.
Signed-off-by: Faiz Abbas
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 36 +-
1 file
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