his reasoning to the commit message of v2.
Best regards,
Krzysztof Adamski
his reasoning to the commit message of v2.
Best regards,
Krzysztof Adamski
be switched
for example via sysfs. The same strategy is used for Orange Pi Zero
board DTS.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Changes since version 1:
- nodes sorted alphabetically
- added explanation why enabling ohci/ehci still makes sense
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dt
be switched
for example via sysfs. The same strategy is used for Orange Pi Zero
board DTS.
Signed-off-by: Krzysztof Adamski
---
Changes since version 1:
- nodes sorted alphabetically
- added explanation why enabling ohci/ehci still makes sense
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 17
Similarly to Orange Pi Zero, NanoPi Neo board has an USB OTG port with
an ID pin but with unpowered VBUS. This patch enables this port in
forced peripheral mode.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 17 +
1 file c
Similarly to Orange Pi Zero, NanoPi Neo board has an USB OTG port with
an ID pin but with unpowered VBUS. This patch enables this port in
forced peripheral mode.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 17 +
1 file changed, 17 insertions
bage will be used on next calls.
This patch moves the val pointer used for _regmap_raw_read() to point
to a part of work_buf intended for storing value read.
Signed-off-by: Krzysztof Adamski <krzysztof.adam...@nokia.com>
---
drivers/base/regmap/regmap.c | 6 --
1 file changed, 4 insertions(+
bage will be used on next calls.
This patch moves the val pointer used for _regmap_raw_read() to point
to a part of work_buf intended for storing value read.
Signed-off-by: Krzysztof Adamski
---
drivers/base/regmap/regmap.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/dr
tree (
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/
sunxi/for-next). This build error can be ignored.
Best regards,
Krzysztof Adamski
tree (
https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/
sunxi/for-next). This build error can be ignored.
Best regards,
Krzysztof Adamski
OrangePi Plus board has dwo leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Changes compared to v1:
- Fixed leds labels
- Merged two led sections i
OrangePi Plus board has dwo leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski
---
Changes compared to v1:
- Fixed leds labels
- Merged two led sections into one
arch/
] (kthread) from [] (ret_from_fork+0x14/0x3c)
Signed-off-by: Krzysztof Adamski <krzysztof.adam...@tieto.com>
Reported-by: Jon Hunter <jonath...@nvidia.com>
Acked-by: Jon Hunter <jonath...@nvidia.com>
Tested-by: Jon Hunter <jonath...@nvidia.com>
---
Changes compared to v2:
] (kthread) from [] (ret_from_fork+0x14/0x3c)
Signed-off-by: Krzysztof Adamski
Reported-by: Jon Hunter
Acked-by: Jon Hunter
Tested-by: Jon Hunter
---
Changes compared to v2:
- Extended commit message
Changes compared to v1:
- Fixed error path of device_register too, as noticed by Jon
This problem was introduced by:
commit daad134d6649 ("regulator: core: Request GPIO before creating
sysfs entries")
The error path was not updated correctly and in case
regulator_ena_gpio_free failed, device_unregister was called even though
it was not registered yet.
Signed-off-by:
This problem was introduced by:
commit daad134d6649 ("regulator: core: Request GPIO before creating
sysfs entries")
The error path was not updated correctly and in case
regulator_ena_gpio_free failed, device_unregister was called even though
it was not registered yet.
Signed-off-by:
On Tue, Feb 23, 2016 at 03:18:59PM +, Jon Hunter wrote:
On 23/02/16 14:47, Krzysztof Adamski wrote:
Signed-off-by: Krzysztof Adamski <krzysztof.adam...@tieto.com>
Reported-by: Jon Hunter <jonath...@nvidia.com>
Nit ... I think that order of the above should be reversed.
C
On Tue, Feb 23, 2016 at 03:18:59PM +, Jon Hunter wrote:
On 23/02/16 14:47, Krzysztof Adamski wrote:
Signed-off-by: Krzysztof Adamski
Reported-by: Jon Hunter
Nit ... I think that order of the above should be reversed.
Couldn't find any reference stating proper order of those tags
This problem was introduced by:
commit daad134d6649 ("regulator: core: Request GPIO before creating
sysfs entries")
The error path was not updated correctly and in case
regulator_ena_gpio_free failed, device_unregister was called even though
it was not registered yet.
Signed-off-by:
This problem was introduced by:
commit daad134d6649 ("regulator: core: Request GPIO before creating
sysfs entries")
The error path was not updated correctly and in case
regulator_ena_gpio_free failed, device_unregister was called even though
it was not registered yet.
Signed-off-by:
On Tue, Feb 23, 2016 at 02:15:21PM +, Jon Hunter wrote:
Hi Krzysztof,
On 23/02/16 13:56, Krzysztof Adamski wrote:
On Tue, Feb 23, 2016 at 01:22:38PM +, Jon Hunter wrote:
Hi Mark, Krzysztof,
It appears that commit daad134d6649 ("regulator: core: Request GPIO
before creating
On Tue, Feb 23, 2016 at 02:15:21PM +, Jon Hunter wrote:
Hi Krzysztof,
On 23/02/16 13:56, Krzysztof Adamski wrote:
On Tue, Feb 23, 2016 at 01:22:38PM +, Jon Hunter wrote:
Hi Mark, Krzysztof,
It appears that commit daad134d6649 ("regulator: core: Request GPIO
before creating
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/su
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++
drivers/clk/sunxi/clk-simple-g
OrangePi Plus board has two leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63 +++
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++
drivers/clk/sunxi/clk-simple-gates.c | 4
OrangePi Plus board has two leds - green ("pwr") and red ("status")
and a switch ("sw4"). This patch describes them in a devicetree.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 63
1 file changed
in sunxi_pinctrl_gpio_get for getting pin value when in irq
mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (4):
clk: sunxi: Add apb0 gates for H3
dts: sun8i-h3: Add APB0 related clocks and resets
ARM: dts: sun8i-h
in sunxi_pinctrl_gpio_get for getting pin value when in irq
mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (4):
clk: sunxi: Add apb0 gates for H3
dts: sun8i-h3: Add APB0 related clocks and resets
ARM: dts: sun8i-h
.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3ba65c2..1348b69 100644
--- a/arch/arm/boot/dts/sun8i-h
.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3ba65c2..1348b69 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm
r() otherwise this test will always fail, causing "status"
file to not be visible.
Since regulator_attr_is_visible also tests for is_enabled() op, this
problem is only visible for regulators that does not define this
callback, like regulator-fixed.c.
Signed-off-by: Krzysztof Adamski <k
r() otherwise this test will always fail, causing "status"
file to not be visible.
Since regulator_attr_is_visible also tests for is_enabled() op, this
problem is only visible for regulators that does not define this
callback, like regulator-fixed.c.
Signed-off-by: Krzysztof Adamski
---
d
On Sun, Feb 21, 2016 at 11:27:46AM -0800, Henry Paulissen wrote:
Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?
Its a fix
On Sun, Feb 21, 2016 at 11:27:46AM -0800, Henry Paulissen wrote:
Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?
Its a fix
allwinner,sun8i-h3-r-pinctrl was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Documentation/devicetree/
allwinner,sun8i-h3-r-pinctrl was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/pinctrl/allwi
On Thu, Feb 18, 2016 at 09:07:16AM -0800, Chen-Yu Tsai wrote:
On Thu, Feb 18, 2016 at 7:03 AM, Krzysztof Adamski
<krzysztof.adam...@tieto.com> wrote:
allwinner,sun8i-h3-apb0-gates-clk was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the p
On Thu, Feb 18, 2016 at 09:07:16AM -0800, Chen-Yu Tsai wrote:
On Thu, Feb 18, 2016 at 7:03 AM, Krzysztof Adamski
wrote:
allwinner,sun8i-h3-apb0-gates-clk was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding doc
allwinner,sun8i-h3-apb0-gates-clk was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Documentation/devicetre
allwinner,sun8i-h3-apb0-gates-clk was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sun
On Mon, Feb 15, 2016 at 11:04:26PM +0100, Linus Walleij wrote:
On Mon, Feb 8, 2016 at 3:37 PM, Krzysztof Adamski
<krzysztof.adam...@tieto.com> wrote:
Default function of a pin in sunxi SoCs is "disabled". By default gpios
exported by sysfs are set as input and indeed, when re
On Mon, Feb 15, 2016 at 11:04:26PM +0100, Linus Walleij wrote:
On Mon, Feb 8, 2016 at 3:37 PM, Krzysztof Adamski
wrote:
Default function of a pin in sunxi SoCs is "disabled". By default gpios
exported by sysfs are set as input and indeed, when reading "direction&quo
On Thu, Feb 11, 2016 at 02:21:15PM +0100, Linus Walleij wrote:
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k...@japko.eu> wrote:
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Sign
On Thu, Feb 11, 2016 at 02:21:15PM +0100, Linus Walleij wrote:
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski wrote:
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski
On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote:
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski wrote:
sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert
On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote:
On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k...@japko.eu> wrote:
sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset
if I use only specific compatible string
right now and provide separate patch that adds generic compatible string
to all current SoCs at once? The downside of this is that it's easier to
get merge conflicts unless I wait for applying this patchset.
Best regards,
Krzysztof Adamski
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski
Acked-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2
GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski
Acked-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 +++--
1 file
.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 6f6b4e4..a7b2c53 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm
uot; typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (5):
clk: sunxi: Add apb0 gates for H3
dts: sun8i-h3: Add APB0 related clocks and resets
pinctrl: sunxi: Add H3 R_PIO controller support
ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
pinctrl: sunxi: Use
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-g
uot; typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (5):
clk: sunxi: Add apb0 gates for H3
dts: sun8i-h3: Add APB0 related clocks and resets
pinctrl: sunxi: Add H3 R_PIO controller support
ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
pinctrl: sunxi: Use
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/su
GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
Acked-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@fre
.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 6f6b4e4..a7b2c53 100644
--- a/arch/arm/boot/dts/sun8i-h
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
Acked-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Maxime Ripard <maxime.rip...@fre
if I use only specific compatible string
right now and provide separate patch that adds generic compatible string
to all current SoCs at once? The downside of this is that it's easier to
get merge conflicts unless I wait for applying this patchset.
Best regards,
Krzysztof Adamski
patch sets direction of a GPIO as input when exporting it.
Signed-off-by: Krzysztof Adamski
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinct
pinctrl-sunxi uses 3 cells to describe interrupt, not 2. It's bank
number, pin number and flags.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3
On Fri, Feb 05, 2016 at 05:46:32PM +0800, Chen-Yu Tsai wrote:
On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski wrote:
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot
On Fri, Feb 05, 2016 at 05:46:32PM +0800, Chen-Yu Tsai wrote:
On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k...@japko.eu> wrote:
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adam
pinctrl-sunxi uses 3 cells to describe interrupt, not 2. It's bank
number, pin number and flags.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/ar
patch sets direction of a GPIO as input when exporting it.
Signed-off-by: Krzysztof Adamski <krzysztof.adam...@tieto.com>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drive
On Fri, Feb 05, 2016 at 02:39:23PM +0100, Linus Walleij wrote:
On Wed, Feb 3, 2016 at 8:57 AM, Krzysztof Adamski wrote:
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value. When
value is read, GPIO function must
On Fri, Feb 05, 2016 at 12:11:52PM +0100, Maxime Ripard wrote:
Hi,
On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
On Thu, 4 Feb 2016 00:33:46 +0100
Krzysztof Adamski wrote:
> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs
On Fri, Feb 05, 2016 at 12:11:52PM +0100, Maxime Ripard wrote:
Hi,
On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
On Thu, 4 Feb 2016 00:33:46 +0100
Krzysztof Adamski <k...@japko.eu> wrote:
> This patch adds support for APB0 in H3. It seems to be c
On Fri, Feb 05, 2016 at 02:39:23PM +0100, Linus Walleij wrote:
On Wed, Feb 3, 2016 at 8:57 AM, Krzysztof Adamski <k...@japko.eu> wrote:
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value. When
value is read
On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
On Thu, 4 Feb 2016 00:33:46 +0100
Krzysztof Adamski wrote:
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off
On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
On Thu, 4 Feb 2016 00:33:46 +0100
Krzysztof Adamski <k...@japko.eu> wrote:
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_I
On Wed, Feb 03, 2016 at 11:21:17PM +0100, Krzysztof Adamski wrote:
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
I'm not sure what you mean there. The fixed factor clocks only take a
single parent, and you provided two.
True, I that's actually some stupid leftover
GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2
to two separate - dtsi and c files
- added APB0 clocks a parent for R_PIO
- added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq
mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (5):
clk
.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..bb37f52 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO
.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..bb37f52 100644
--- a/arch/arm/boot/dts/sun8i-h
to two separate - dtsi and c files
- added APB0 clocks a parent for R_PIO
- added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq
mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (5):
clk
On Wed, Feb 03, 2016 at 11:21:17PM +0100, Krzysztof Adamski wrote:
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
I'm not sure what you mean there. The fixed factor clocks only take a
single parent, and you provided two.
True, I that's actually some stupid leftover
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/su
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/K
GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 +++--
1 file changed, 3 insertions
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski <k...@japko.eu>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-g
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value. When
value is read, GPIO function must be temporary switched to input for
reads.
Signed-off-by: Krzysztof Adamski
---
Changes compared to v1:
- None
GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski
---
drivers/pinctrl/sunxi/Kconfig | 4 ++
drivers/pinctrl/sunxi/Makefile | 1 +
drivers
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
.../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
arch/arm/boot/dts/sun8i-h3.dtsi | 12
to
their peripherals on my board to test them.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..ce35e93 100644
--- a/arch
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2
uot; typo
- fixed order in allwinner,sunxi-pinctrl.txt
Krzysztof Adamski (5):
clk: sunxi: Add apb0 gates for H3
dts: sun8i-h3: Add APB0 related clocks and resets
pinctrl: sunxi: Add H3 R_PIO controller support
ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
pinctrl: sunxi: Use
On Tue, Feb 02, 2016 at 10:24:51AM +0100, Krzysztof Adamski wrote:
On Tue, Feb 02, 2016 at 02:25:18PM +0800, Chen-Yu Tsai wrote:
On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski wrote:
- reg: Should contain the register physical address and length for
the
diff --git a/arch/arm/boot/dts
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value. When
value is read, GPIO function must be temporary switched to input for
reads.
Signed-off-by: Krzysztof Adamski
---
drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 1
On Tue, Feb 02, 2016 at 02:25:18PM +0800, Chen-Yu Tsai wrote:
On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski wrote:
- reg: Should contain the register physical address and length for
the
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..745f64c
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